584 lines
16 KiB
Verilog
584 lines
16 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE DMA One Channel Register File ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: wb_dma_ch_rf.v,v 1.5 2002-02-01 01:54:45 rudi Exp $
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//
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// $Date: 2002-02-01 01:54:45 $
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// $Revision: 1.5 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2001/10/30 02:06:17 rudi
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//
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// - Fixed problem where synthesis tools would instantiate latches instead of flip-flops
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//
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// Revision 1.3 2001/10/19 04:35:04 rudi
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//
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// - Made the core parameterized
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//
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// Revision 1.2 2001/08/15 05:40:30 rudi
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//
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Added Section 3.10, describing DMA restart.
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//
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// Revision 1.1 2001/07/29 08:57:02 rudi
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//
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//
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// 1) Changed Directory Structure
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// 2) Added restart signal (REST)
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//
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// Revision 1.3 2001/06/14 08:50:01 rudi
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//
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// Changed Module Name to match file name.
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//
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// Revision 1.2 2001/06/13 02:26:48 rudi
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//
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//
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// Small changes after running lint.
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//
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// Revision 1.1 2001/06/05 10:25:27 rudi
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//
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//
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// Initial checkin of register file for one channel.
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//
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//
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//
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//
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`include "wb_dma_defines.v"
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module wb_dma_ch_rf( clk, rst,
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pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1,
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ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int,
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wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re,
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// DMA Registers Write Back Channel Select
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ch_sel, ndnr,
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// DMA Engine Status
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dma_busy, dma_err, dma_done, dma_done_all,
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// DMA Engine Reg File Update ctrl signals
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de_csr, de_txsz, de_adr0, de_adr1,
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de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we,
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de_fetch_descr, dma_rest,
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ptr_set
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);
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parameter [4:0] CH_NO = 5'h0; // This Instances Channel ID
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parameter [0:0] CH_EN = 1'b1; // This channel exists
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parameter [0:0] HAVE_ARS = 1'b1; // 1=this Instance Supports ARS
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parameter [0:0] HAVE_ED = 1'b1; // 1=this Instance Supports External Descriptors
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parameter [0:0] HAVE_CBUF= 1'b1; // 1=this Instance Supports Cyclic Buffers
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input clk, rst;
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output [31:0] pointer;
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output [31:0] pointer_s;
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output [31:0] ch_csr;
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output [31:0] ch_txsz;
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output [31:0] ch_adr0;
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output [31:0] ch_adr1;
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output [31:0] ch_am0;
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output [31:0] ch_am1;
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output [31:0] sw_pointer;
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output ch_stop;
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output ch_dis;
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output int;
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input [31:0] wb_rf_din;
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input [7:0] wb_rf_adr;
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input wb_rf_we;
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input wb_rf_re;
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input [4:0] ch_sel;
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input ndnr;
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// DMA Engine Status
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input dma_busy, dma_err, dma_done, dma_done_all;
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// DMA Engine Reg File Update ctrl signals
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input [31:0] de_csr;
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input [11:0] de_txsz;
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input [31:0] de_adr0;
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input [31:0] de_adr1;
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input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;
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input de_fetch_descr;
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input dma_rest;
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires and Registers
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//
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wire [31:0] pointer;
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reg [27:0] pointer_r;
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reg [27:0] pointer_sr;
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reg ptr_valid;
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reg ch_eol;
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wire [31:0] ch_csr, ch_txsz;
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reg [8:0] ch_csr_r;
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reg [2:0] ch_csr_r2;
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reg [2:0] ch_csr_r3;
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reg [2:0] int_src_r;
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reg ch_err_r;
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reg ch_stop;
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reg ch_busy;
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reg ch_done;
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reg ch_err;
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reg rest_en;
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reg [10:0] ch_chk_sz_r;
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reg [11:0] ch_tot_sz_r;
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reg [22:0] ch_txsz_s;
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reg ch_sz_inf;
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wire [31:0] ch_adr0, ch_adr1;
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reg [29:0] ch_adr0_r, ch_adr1_r;
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wire [31:0] ch_am0, ch_am1;
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reg [27:0] ch_am0_r, ch_am1_r;
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reg [29:0] ch_adr0_s, ch_adr1_s;
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reg [29:0] sw_pointer_r;
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wire sw_pointer_we;
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wire [28:0] cmp_adr;
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reg ch_dis;
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wire ch_enable;
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wire pointer_we;
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wire ch_csr_we, ch_csr_re, ch_txsz_we, ch_adr0_we, ch_adr1_we;
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wire ch_am0_we, ch_am1_we;
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reg ch_rl;
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wire ch_done_we;
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wire ch_err_we;
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wire chunk_done_we;
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wire ch_csr_dewe, ch_txsz_dewe, ch_adr0_dewe, ch_adr1_dewe;
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wire this_ptr_set;
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wire ptr_inv;
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////////////////////////////////////////////////////////////////////
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//
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// Aliases
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//
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assign ch_adr0 = CH_EN ? {ch_adr0_r, 2'h0} : 32'h0;
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assign ch_adr1 = CH_EN ? {ch_adr1_r, 2'h0} : 32'h0;
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assign ch_am0 = (CH_EN & HAVE_CBUF) ? {ch_am0_r, 4'h0} : 32'hffff_fff0;
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assign ch_am1 = (CH_EN & HAVE_CBUF) ? {ch_am1_r, 4'h0} : 32'hffff_fff0;
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assign sw_pointer = (CH_EN & HAVE_CBUF) ? {sw_pointer_r,2'h0} : 32'h0;
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assign pointer = CH_EN ? {pointer_r, 3'h0, ptr_valid} : 32'h0;
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assign pointer_s = CH_EN ? {pointer_sr, 4'h0} : 32'h0;
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assign ch_csr = CH_EN ? {9'h0, int_src_r, ch_csr_r3, rest_en, ch_csr_r2,
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ch_err, ch_done, ch_busy, 1'b0, ch_csr_r[8:1], ch_enable} : 32'h0;
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assign ch_txsz = CH_EN ? {5'h0, ch_chk_sz_r, ch_sz_inf, 3'h0, ch_tot_sz_r} : 32'h0;
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assign ch_enable = CH_EN ? (ch_csr_r[`WDMA_CH_EN] & (HAVE_CBUF ? !ch_dis : 1'b1) ) : 1'b0;
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////////////////////////////////////////////////////////////////////
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//
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// CH0 control signals
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//
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parameter [4:0] CH_ADR = CH_NO + 5'h1;
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assign ch_csr_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);
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assign ch_csr_re = CH_EN & wb_rf_re & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h0);
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assign ch_txsz_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h1);
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assign ch_adr0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h2);
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assign ch_am0_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h3);
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assign ch_adr1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h4);
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assign ch_am1_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h5);
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assign pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h6);
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assign sw_pointer_we = CH_EN & wb_rf_we & (wb_rf_adr[7:3] == CH_ADR) & (wb_rf_adr[2:0] == 3'h7);
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assign ch_done_we = CH_EN & (((ch_sel==CH_NO) & dma_done_all) | ndnr) &
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(ch_csr[`WDMA_USE_ED] ? ch_eol : !ch_csr[`WDMA_ARS]);
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assign chunk_done_we = CH_EN & (ch_sel==CH_NO) & dma_done;
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assign ch_err_we = CH_EN & (ch_sel==CH_NO) & dma_err;
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assign ch_csr_dewe = CH_EN & de_csr_we & (ch_sel==CH_NO);
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assign ch_txsz_dewe = CH_EN & de_txsz_we & (ch_sel==CH_NO);
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assign ch_adr0_dewe = CH_EN & de_adr0_we & (ch_sel==CH_NO);
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assign ch_adr1_dewe = CH_EN & de_adr1_we & (ch_sel==CH_NO);
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assign ptr_inv = CH_EN & ((ch_sel==CH_NO) & dma_done_all) | ndnr;
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assign this_ptr_set = CH_EN & ptr_set & (ch_sel==CH_NO);
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always @(posedge clk)
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ch_rl <= #1 CH_EN & HAVE_ARS & (
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(rest_en & dma_rest) |
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((ch_sel==CH_NO) & dma_done_all & ch_csr[`WDMA_ARS] & !ch_csr[`WDMA_USE_ED])
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);
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// ---------------------------------------------------
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// Pointers
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always @(posedge clk or negedge rst)
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if(!rst) ptr_valid <= #1 1'b0;
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else
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if(CH_EN & HAVE_ED)
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begin
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if( this_ptr_set | (rest_en & dma_rest) )
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ptr_valid <= #1 1'b1;
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else
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if(ptr_inv) ptr_valid <= #1 1'b0;
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end
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else ptr_valid <= #1 1'b0;
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always @(posedge clk or negedge rst)
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if(!rst) ch_eol <= #1 1'b0;
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else
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if(CH_EN & HAVE_ED)
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begin
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if(ch_csr_dewe) ch_eol <= #1 de_csr[`WDMA_ED_EOL];
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else
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if(ch_done_we) ch_eol <= #1 1'b0;
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end
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else ch_eol <= #1 1'b0;
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always @(posedge clk)
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if(CH_EN & HAVE_ED)
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begin
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if(pointer_we) pointer_r <= #1 wb_rf_din[31:4];
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else
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if(this_ptr_set) pointer_r <= #1 de_csr[31:4];
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end
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else pointer_r <= #1 1'b0;
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always @(posedge clk)
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if(CH_EN & HAVE_ED)
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begin
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if(this_ptr_set) pointer_sr <= #1 pointer_r;
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end
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else pointer_sr <= #1 1'b0;
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// ---------------------------------------------------
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// CSR
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always @(posedge clk or negedge rst)
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if(!rst) ch_csr_r <= #1 1'b0;
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else
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if(CH_EN)
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begin
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if(ch_csr_we) ch_csr_r <= #1 wb_rf_din[8:0];
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else
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begin
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if(ch_done_we) ch_csr_r[`WDMA_CH_EN] <= #1 1'b0;
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if(ch_csr_dewe) ch_csr_r[4:1] <= #1 de_csr[19:16];
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end
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end
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// done bit
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always @(posedge clk or negedge rst)
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if(!rst) ch_done <= #1 1'b0;
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else
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if(CH_EN)
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begin
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if(ch_csr_we) ch_done <= #1 !wb_rf_din[`WDMA_CH_EN];
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else
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if(ch_done_we) ch_done <= #1 1'b1;
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end
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// busy bit
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always @(posedge clk)
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ch_busy <= #1 CH_EN & (ch_sel==CH_NO) & dma_busy;
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// stop bit
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always @(posedge clk)
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ch_stop <= #1 CH_EN & ch_csr_we & wb_rf_din[`WDMA_STOP];
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// error bit
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always @(posedge clk or negedge rst)
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if(!rst) ch_err <= #1 1'b0;
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else
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if(CH_EN)
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begin
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if(ch_err_we) ch_err <= #1 1'b1;
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else
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if(ch_csr_re) ch_err <= #1 1'b0;
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end
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// Priority Bits
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always @(posedge clk or negedge rst)
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if(!rst) ch_csr_r2 <= #1 3'h0;
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else
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if(CH_EN & ch_csr_we) ch_csr_r2 <= #1 wb_rf_din[15:13];
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// Restart Enable Bit (REST)
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always @(posedge clk or negedge rst)
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if(!rst) rest_en <= #1 1'b0;
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else
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if(CH_EN & ch_csr_we) rest_en <= #1 wb_rf_din[16];
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// INT Mask
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always @(posedge clk or negedge rst)
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if(!rst) ch_csr_r3 <= #1 3'h0;
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else
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if(CH_EN & ch_csr_we) ch_csr_r3 <= #1 wb_rf_din[19:17];
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// INT Source
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always @(posedge clk or negedge rst)
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if(!rst) int_src_r[2] <= #1 1'b0;
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else
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if(CH_EN)
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begin
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if(chunk_done_we) int_src_r[2] <= #1 1'b1;
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else
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if(ch_csr_re) int_src_r[2] <= #1 1'b0;
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end
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always @(posedge clk or negedge rst)
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if(!rst) int_src_r[1] <= #1 1'b0;
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else
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if(CH_EN)
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begin
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if(ch_done_we) int_src_r[1] <= #1 1'b1;
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else
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if(ch_csr_re) int_src_r[1] <= #1 1'b0;
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end
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always @(posedge clk or negedge rst)
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if(!rst) int_src_r[0] <= #1 1'b0;
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else
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if(CH_EN)
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begin
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if(ch_err_we) int_src_r[0] <= #1 1'b1;
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else
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if(ch_csr_re) int_src_r[0] <= #1 1'b0;
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end
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// Interrupt Output
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assign int = |(int_src_r & ch_csr_r3) & CH_EN;
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// ---------------------------------------------------
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// TXZS
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always @(posedge clk)
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if(CH_EN)
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begin
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if(ch_txsz_we)
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{ch_chk_sz_r, ch_tot_sz_r} <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
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else
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if(ch_txsz_dewe)
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ch_tot_sz_r <= #1 de_txsz;
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else
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if(ch_rl)
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{ch_chk_sz_r, ch_tot_sz_r} <= #1 ch_txsz_s;
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end
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// txsz shadow register
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always @(posedge clk)
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if(CH_EN & HAVE_ARS)
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begin
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if(ch_txsz_we) ch_txsz_s <= #1 {wb_rf_din[26:16], wb_rf_din[11:0]};
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else
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if(rest_en & ch_txsz_dewe & de_fetch_descr)
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ch_txsz_s[11:0] <= #1 de_txsz[11:0];
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end
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// Infinite Size indicator
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always @(posedge clk)
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if(CH_EN)
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begin
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if(ch_txsz_we) ch_sz_inf <= #1 wb_rf_din[15];
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end
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// ---------------------------------------------------
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// ADR0
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always @(posedge clk)
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if(CH_EN)
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begin
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if(ch_adr0_we) ch_adr0_r <= #1 wb_rf_din[31:2];
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else
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if(ch_adr0_dewe) ch_adr0_r <= #1 de_adr0[31:2];
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else
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if(ch_rl) ch_adr0_r <= #1 ch_adr0_s;
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end
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// Adr0 shadow register
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|
always @(posedge clk)
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if(CH_EN & HAVE_ARS)
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|
begin
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|
if(ch_adr0_we) ch_adr0_s <= #1 wb_rf_din[31:2];
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|
else
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|
if(rest_en & ch_adr0_dewe & de_fetch_descr)
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|
ch_adr0_s <= #1 de_adr0[31:2];
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|
end
|
|
|
|
// ---------------------------------------------------
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|
// AM0
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|
always @(posedge clk or negedge rst)
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|
if(!rst) ch_am0_r <= #1 28'hfffffff;
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|
else
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|
if(ch_am0_we) ch_am0_r <= #1 wb_rf_din[31:4];
|
|
|
|
// ---------------------------------------------------
|
|
// ADR1
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|
always @(posedge clk)
|
|
if(CH_EN)
|
|
begin
|
|
if(ch_adr1_we) ch_adr1_r <= #1 wb_rf_din[31:2];
|
|
else
|
|
if(ch_adr1_dewe) ch_adr1_r <= #1 de_adr1[31:2];
|
|
else
|
|
if(ch_rl) ch_adr1_r <= #1 ch_adr1_s;
|
|
end
|
|
|
|
// Adr1 shadow register
|
|
always @(posedge clk)
|
|
if(CH_EN & HAVE_ARS)
|
|
begin
|
|
if(ch_adr1_we) ch_adr1_s <= #1 wb_rf_din[31:2];
|
|
else
|
|
if(rest_en & ch_adr1_dewe & de_fetch_descr)
|
|
ch_adr1_s <= #1 de_adr1[31:2];
|
|
end
|
|
|
|
// ---------------------------------------------------
|
|
// AM1
|
|
always @(posedge clk or negedge rst)
|
|
if(!rst) ch_am1_r <= #1 28'hfffffff;
|
|
else
|
|
if(ch_am1_we & CH_EN & HAVE_CBUF) ch_am1_r <= #1 wb_rf_din[31:4];
|
|
|
|
// ---------------------------------------------------
|
|
// Software Pointer
|
|
always @(posedge clk or negedge rst)
|
|
if(!rst) sw_pointer_r <= #1 28'h0;
|
|
else
|
|
if(sw_pointer_we & CH_EN & HAVE_CBUF) sw_pointer_r <= #1 wb_rf_din[31:4];
|
|
|
|
// ---------------------------------------------------
|
|
// Software Pointer Match logic
|
|
|
|
assign cmp_adr = ch_csr[2] ? ch_adr1[30:2] : ch_adr0[30:2];
|
|
|
|
always @(posedge clk)
|
|
ch_dis <= #1 CH_EN & HAVE_CBUF & (sw_pointer[30:2] == cmp_adr) & sw_pointer[31];
|
|
|
|
endmodule
|
|
|
|
|
|
module wb_dma_ch_rf_dummy(clk, rst,
|
|
pointer, pointer_s, ch_csr, ch_txsz, ch_adr0, ch_adr1,
|
|
ch_am0, ch_am1, sw_pointer, ch_stop, ch_dis, int,
|
|
|
|
wb_rf_din, wb_rf_adr, wb_rf_we, wb_rf_re,
|
|
|
|
// DMA Registers Write Back Channel Select
|
|
ch_sel, ndnr,
|
|
|
|
// DMA Engine Status
|
|
dma_busy, dma_err, dma_done, dma_done_all,
|
|
|
|
// DMA Engine Reg File Update ctrl signals
|
|
de_csr, de_txsz, de_adr0, de_adr1,
|
|
de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we,
|
|
de_fetch_descr, dma_rest,
|
|
ptr_set
|
|
|
|
);
|
|
|
|
parameter CH_NO = 0;
|
|
parameter HAVE_ARS = 1;
|
|
parameter HAVE_ED = 1;
|
|
parameter HAVE_CBUF= 1;
|
|
|
|
input clk, rst;
|
|
|
|
output [31:0] pointer;
|
|
output [31:0] pointer_s;
|
|
output [31:0] ch_csr;
|
|
output [31:0] ch_txsz;
|
|
output [31:0] ch_adr0;
|
|
output [31:0] ch_adr1;
|
|
output [31:0] ch_am0;
|
|
output [31:0] ch_am1;
|
|
output [31:0] sw_pointer;
|
|
output ch_stop;
|
|
output ch_dis;
|
|
output int;
|
|
|
|
input [31:0] wb_rf_din;
|
|
input [7:0] wb_rf_adr;
|
|
input wb_rf_we;
|
|
input wb_rf_re;
|
|
|
|
input [4:0] ch_sel;
|
|
input ndnr;
|
|
|
|
// DMA Engine Status
|
|
input dma_busy, dma_err, dma_done, dma_done_all;
|
|
|
|
// DMA Engine Reg File Update ctrl signals
|
|
input [31:0] de_csr;
|
|
input [11:0] de_txsz;
|
|
input [31:0] de_adr0;
|
|
input [31:0] de_adr1;
|
|
input de_csr_we, de_txsz_we, de_adr0_we, de_adr1_we, ptr_set;
|
|
input de_fetch_descr;
|
|
input dma_rest;
|
|
|
|
assign pointer = 32'h0;
|
|
assign pointer_s = 32'h0;
|
|
assign ch_csr = 32'h0;
|
|
assign ch_txsz = 32'h0;
|
|
assign ch_adr0 = 32'h0;
|
|
assign ch_adr1 = 32'h0;
|
|
assign ch_am0 = 32'h0;
|
|
assign ch_am1 = 32'h0;
|
|
assign sw_pointer = 32'h0;
|
|
assign ch_stop = 1'b0;
|
|
assign ch_dis = 1'b0;
|
|
assign int = 1'b0;
|
|
|
|
endmodule
|