117 lines
4.8 KiB
Verilog
117 lines
4.8 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE DMA Definitions ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: wb_dma_defines.v,v 1.5 2002-02-01 01:54:45 rudi Exp $
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//
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// $Date: 2002-02-01 01:54:45 $
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// $Revision: 1.5 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.4 2001/10/19 04:35:04 rudi
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//
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// - Made the core parameterized
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//
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// Revision 1.3 2001/09/07 15:34:38 rudi
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//
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// Changed reset to active high.
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//
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// Revision 1.2 2001/08/15 05:40:30 rudi
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//
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Added Section 3.10, describing DMA restart.
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//
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// Revision 1.1 2001/07/29 08:57:02 rudi
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//
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//
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// 1) Changed Directory Structure
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// 2) Added restart signal (REST)
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//
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// Revision 1.2 2001/06/05 10:22:37 rudi
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//
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//
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// - Added Support of up to 31 channels
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// - Added support for 2,4 and 8 priority levels
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// - Now can have up to 31 channels
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// - Added many configuration items
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// - Changed reset to async
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//
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// Revision 1.1.1.1 2001/03/19 13:11:09 rudi
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// Initial Release
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//
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//
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//
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`timescale 1ns / 10ps
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// This define selects how the slave interface determines if
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// the internal register file or pass through mode are selected.
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// This should be a simple address decoder. "wb_addr_i" is the
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// WISHBONE address bus (32 bits wide).
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// NOTE: The entire pass-through mode is implemented in combinatorial
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// logic only. So the more address lines we look at and compare here
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// the higher will be the initial delay when pass-through mode is selected.
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// Here we look at the top 8 address bit. If they are all 1, the
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// register file is selected. Use this with caution !!!
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`define WDMA_REG_SEL (wb_addr_i[31:28] == rf_addr)
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// DO NOT MODIFY BEYOND THIS POINT
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// CSR Bits
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`define WDMA_CH_EN 0
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`define WDMA_DST_SEL 1
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`define WDMA_SRC_SEL 2
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`define WDMA_INC_DST 3
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`define WDMA_INC_SRC 4
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`define WDMA_MODE 5
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`define WDMA_ARS 6
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`define WDMA_USE_ED 7
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`define WDMA_WRB 8
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`define WDMA_STOP 9
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`define WDMA_BUSY 10
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`define WDMA_DONE 11
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`define WDMA_ERR 12
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`define WDMA_ED_EOL 20
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