24 lines
780 B
VHDL
24 lines
780 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.axi3intercon_pkg.all;
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package axi_aw_router_pkg is
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type axi_aw_masters_in_t is array (natural range <>) of master_aw_in_t;
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type axi_aw_masters_out_t is array (natural range <>) of master_aw_out_t;
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type axi_aw_slaves_out_t is array (natural range <>) of slave_aw_out_t;
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type axi_aw_slaves_in_t is array (natural range <>) of slave_aw_in_t;
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type write_lock_t is record
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locked : std_logic;
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slave_idx : integer range 0 to SLAVE_COUNT - 1;
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end record write_lock_t;
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type write_locks_t is array (natural range <>) of write_lock_t;
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subtype write_release_t is std_logic_vector(0 to MASTER_COUNT - 1);
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end package axi_aw_router_pkg;
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-- package body filename is
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-- end package body filename;
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