add uart and top vhd
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commit
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.gitignore
vendored
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.gitignore
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#*#
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*#
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*.bak
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*~
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.#*
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45
top.vhd
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top.vhd
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-------------------------------------------------------------------------------
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-- Title : MachXO2 Serial Configuration
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-- Project : tiny-xo2
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-------------------------------------------------------------------------------
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-- File : top.vhd
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-- Author : マリオ <mario.huettel@gmx.net>
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-- Company :
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-- Created : 2017-11-21
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-- Last update: 2017-11-21
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description:
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-------------------------------------------------------------------------------
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-- Copyright (c) 2017 GPLv2
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity config_top is
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generic (
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BAUD_RATE : integer := 9600);
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port (
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clk : in std_logic; -- input clock 12 MHz
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dts : in std_logic; -- DTS Strobe signal
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uart_tx : out std_logic; -- UART TX
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uart_rx : in std_logic); -- UART RX
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end entity config_top;
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architecture RTL of config_top is
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begin -- architecture RTL
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end architecture RTL;
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161
uart_rx.vhd
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uart_rx.vhd
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-- -------------------------------------------------------------------------- --
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-- uart_rx.vhd: Basic UART (rx)
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--
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-- Copyright (C) 2017 Markus Koch <markus@notsyncing.net>
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--
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-- This Source Code Form is subject to the terms of the Mozilla Public
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-- License, v. 2.0. If a copy of the MPL was not distributed with this
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-- file, You can obtain one at http://mozilla.org/MPL/2.0/.
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity uart_rx is
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port(
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clk : in std_logic;
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rst : in std_logic;
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data : out std_logic_vector(7 downto 0);
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byte_ready : out std_logic;
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error : out std_logic;
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ckDiv : in std_logic_vector(15 downto 0);
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parityEnable : in std_logic;
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parityOdd : in std_logic;
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twoStopBits : in std_logic;
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rx : in std_logic
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);
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end entity uart_rx;
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architecture RTL of uart_rx is
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constant SYNCH_COUNT : integer := 11; -- Min. 8
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constant BITCOUNT : integer := 8;
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type state_t is (SYNCH, IDLE, START, RECEIVE, PARITY, STOP);
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signal state : state_t;
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signal clkDivider : unsigned(15 downto 0);
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signal bitCounter : integer range 0 to SYNCH_COUNT;
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signal data_i : std_logic_vector(7 downto 0);
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-- signal rx_edge : std_logic;
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signal parity_calc : std_logic;
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signal rx_i : std_logic;
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begin
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synchronizer_inst : entity work.synchronizer
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generic map(
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COUNT => 1
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)
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port map(
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clk => clk,
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rst => rst,
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dIn(0) => rx,
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dOut(0) => rx_i
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);
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-- edgeDetector_inst : entity work.edgeDetector
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-- port map(clk => clk,
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-- rst => rst,
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-- sig => rx_i,
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-- risingEdge => open,
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-- fallingEdge => open,
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-- anyEdge => rx_edge);
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rxFSM : process(clk, rst, parityOdd, ckDiv) is
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begin
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if rst = '1' then
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state <= SYNCH;
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bitCounter <= SYNCH_COUNT;
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clkDivider <= unsigned(ckDiv);
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error <= '0';
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parity_calc <= parityOdd;
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data_i <= x"00";
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data <= x"00";
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byte_ready <= '0';
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elsif rising_edge(clk) then
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byte_ready <= '0';
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error <= '0';
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if (clkDivider = 0) then
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clkDivider <= unsigned(ckDiv);
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else
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clkDivider <= clkDivider - 1;
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end if;
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case state is
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when SYNCH => -- Wait for 11 consecutive ones
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if (clkDivider = to_unsigned(0, clkDivider'length)) then
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if rx_i = '1' then
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if bitCounter = 0 then
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state <= IDLE;
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else
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bitCounter <= bitcounter - 1;
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end if;
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else
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bitCounter <= SYNCH_COUNT;
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end if;
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end if;
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when IDLE => -- Detect transition for sync
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if rx_i = '0' then
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state <= START;
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clkDivider <= unsigned('0' & ckDiv(15 downto 1)); -- cMax_half. After that we are in the middle of the start bit
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parity_calc <= parityOdd;
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end if;
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when START =>
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if (clkDivider = to_unsigned(0, clkDivider'length)) then
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if rx_i = '0' then
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state <= RECEIVE;
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bitCounter <= 0;
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else
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report "uart_rx: START BIT ERROR" severity warning;
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error <= '1';
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state <= SYNCH;
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end if;
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end if;
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when RECEIVE =>
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if (clkDivider = to_unsigned(0, clkDivider'length)) then
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data_i(bitCounter) <= rx_i;
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if rx_i = '1' then
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parity_calc <= not parity_calc;
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end if;
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if bitCounter = BITCOUNT - 1 then
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bitCounter <= 0;
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if parityEnable = '1' then
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state <= PARITY;
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else
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state <= STOP;
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end if;
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else
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bitCounter <= bitCounter + 1;
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end if;
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end if;
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when PARITY =>
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if (clkDivider = to_unsigned(0, clkDivider'length)) then
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if parity_calc = rx_i then
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state <= STOP;
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else
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state <= SYNCH;
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error <= '1';
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report "uart_rx: PARITY ERROR" severity warning;
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end if;
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end if;
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when STOP =>
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if (clkDivider = to_unsigned(0, clkDivider'length)) then
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if (rx_i = '1') then
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bitCounter <= bitCounter + 1;
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if bitCounter = 1 or twoStopBits = '0' then
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state <= IDLE;
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data <= data_i;
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byte_ready <= '1';
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end if;
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else
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error <= '1';
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state <= SYNCH;
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report "uart_rx: STOP BIT ERROR" severity warning;
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end if;
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end if;
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end case;
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end if;
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end process rxFSM;
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end architecture RTL;
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110
uart_tx.vhd
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110
uart_tx.vhd
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-- -------------------------------------------------------------------------- --
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-- uart_tx.vhd: Basic UART (tx)
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--
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-- Copyright (C) 2017 Markus Koch <markus@notsyncing.net>
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--
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-- This Source Code Form is subject to the terms of the Mozilla Public
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-- License, v. 2.0. If a copy of the MPL was not distributed with this
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-- file, You can obtain one at http://mozilla.org/MPL/2.0/.
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-- -------------------------------------------------------------------------- --
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity uart_tx is
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port(
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clk : in std_logic;
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rst : in std_logic;
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data : in std_logic_vector(7 downto 0);
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byte_ready : in std_logic;
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busy : out std_logic;
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ckDiv : in std_logic_vector(15 downto 0);
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parityEnable : in std_logic;
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parityOdd : in std_logic;
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twoStopBits : in std_logic;
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tx : out std_logic
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);
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end entity uart_tx;
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architecture RTL of uart_tx is
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type state_t is (IDLE, START, TRANSMIT, PARITY, STOP);
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signal state : state_t;
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signal clkDivider : unsigned(15 downto 0);
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signal data_i : std_logic_vector(7 downto 0);
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signal bitCounter : integer range 0 to 7;
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signal parity_calc : std_logic;
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begin
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txFSM : process(clk, rst, ckDiv, parityOdd) is
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begin
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if rst = '1' then
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data_i <= x"00";
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state <= IDLE;
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tx <= '1';
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bitCounter <= 0;
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busy <= '0';
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clkDivider <= unsigned(ckDiv);
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parity_calc <= parityOdd;
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elsif rising_edge(clk) then
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busy <= '1';
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if (clkDivider = 0) then
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clkDivider <= unsigned(ckDiv);
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else
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clkDivider <= clkDivider - 1;
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end if;
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case state is
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when IDLE =>
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busy <= '0';
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tx <= '1';
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if byte_ready = '1' then
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data_i <= data;
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state <= START;
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clkDivider <= unsigned(ckDiv);
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bitCounter <= 0;
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parity_calc <= '0';
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busy <= '1';
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tx <= '1';
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end if;
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when START =>
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tx <= '0';
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state <= TRANSMIT;
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when TRANSMIT =>
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if (clkDivider = to_unsigned(0, clkDivider'length)) then
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tx <= data_i(bitCounter);
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if data_i(bitCounter) = '1' then
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parity_calc <= not parity_calc;
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end if;
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if bitCounter = 7 then
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bitCounter <= 0;
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if parityEnable = '1' then
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state <= PARITY;
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else
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state <= STOP;
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end if;
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else
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bitCounter <= bitCounter + 1;
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end if;
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end if;
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when PARITY =>
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if (clkDivider = to_unsigned(0, clkDivider'length)) then
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tx <= parity_calc;
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state <= STOP;
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end if;
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when STOP =>
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if (clkDivider = to_unsigned(0, clkDivider'length)) then
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tx <= '1';
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bitCounter <= bitCounter + 1;
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if (bitCounter = 1 and twoStopBits = '0') or (bitCounter = 2 and twoStopBits = '1') then
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state <= IDLE;
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end if;
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end if;
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end case;
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end if;
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end process txFSM;
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end architecture RTL;
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