43 lines
746 B
VHDL
43 lines
746 B
VHDL
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library ieee;
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library design;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use design.all;
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entity ws2812test_bench is
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end entity ws2812test_bench;
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architecture RTL of ws2812test_bench is
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signal clk : std_logic;
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signal rst : std_logic;
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signal ws_out : std_logic;
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begin
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clock_driver : process
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constant period : time := 20 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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resetprovider : process is
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begin
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rst <= '0';
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wait for 3 ns;
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rst <= '1';
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wait;
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end process resetprovider;
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ws2812test_inst : entity design.ws2812test
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port map(
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clk => clk,
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reset => rst,
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ws_out => ws_out,
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gamma_req => '1'
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);
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end architecture RTL;
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