Demo Code for WS2812b LEDs created
This commit is contained in:
commit
5bdf863277
3
.gitignore
vendored
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3
.gitignore
vendored
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*.bak
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quartus
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.library_mapping.xml
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.library_mapping.xml
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<?xml version="1.0" encoding="UTF-8"?>
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<com.sigasi.hdt.shared.librarymapping.model:LibraryMappings xmlns:com.sigasi.hdt.shared.librarymapping.model="com.sigasi.hdt.vhdl.scoping.librarymapping" Version="2">
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<Mappings Location="bench" Library="bench"/>
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<Mappings Location="src" Library="design"/>
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<Mappings Location="Common Libraries/IEEE" Library="ieee"/>
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<Mappings Location="Common Libraries" Library="not mapped"/>
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<Mappings Location="quartus" Library="not mapped"/>
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<Mappings Location="Common Libraries/STD" Library="std"/>
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<Mappings Location="" Library="work"/>
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</com.sigasi.hdt.shared.librarymapping.model:LibraryMappings>
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.project
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.project
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<?xml version="1.0" encoding="UTF-8"?>
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<projectDescription>
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<name>ws2812b</name>
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<comment></comment>
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<projects>
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</projects>
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<buildSpec>
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<buildCommand>
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<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
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<arguments>
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</arguments>
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</buildCommand>
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</buildSpec>
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<natures>
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<nature>com.sigasi.hdt.vhdl.ui.vhdlNature</nature>
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<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
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</natures>
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<linkedResources>
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<link>
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<name>Common Libraries</name>
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<type>2</type>
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<locationURI>virtual:/virtual</locationURI>
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</link>
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<link>
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<name>Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt</name>
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<type>1</type>
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<locationURI>sigasiresource:/vhdl/readme2.txt</locationURI>
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</link>
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<link>
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<name>Common Libraries/IEEE</name>
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<type>2</type>
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<locationURI>sigasiresource:/vhdl/93/IEEE</locationURI>
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</link>
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<link>
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<name>Common Libraries/STD</name>
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<type>2</type>
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<locationURI>sigasiresource:/vhdl/93/STD</locationURI>
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</link>
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<link>
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<name>Common Libraries/IEEE/Synopsys</name>
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<type>2</type>
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<locationURI>sigasiresource:/vhdl/93/IEEE%20Synopsys</locationURI>
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</link>
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</linkedResources>
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</projectDescription>
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5
.settings/org.eclipse.core.resources.prefs
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5
.settings/org.eclipse.core.resources.prefs
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eclipse.preferences.version=1
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encoding//Common\ Libraries/IEEE=utf-8
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encoding//Common\ Libraries/IEEE/Synopsys=utf-8
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encoding//Common\ Libraries/STD=utf-8
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encoding/Common\ Libraries=utf-8
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42
bench/ws2812test_bench.vhd
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bench/ws2812test_bench.vhd
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library ieee;
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library design;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use design.all;
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entity ws2812test_bench is
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end entity ws2812test_bench;
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architecture RTL of ws2812test_bench is
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signal clk : std_logic;
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signal rst : std_logic;
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signal ws_out : std_logic;
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begin
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clock_driver : process
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constant period : time := 20 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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resetprovider : process is
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begin
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rst <= '0';
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wait for 3 ns;
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rst <= '1';
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wait;
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end process resetprovider;
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ws2812test_inst : entity design.ws2812test
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port map(
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clk => clk,
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reset => rst,
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ws_out => ws_out,
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gamma_req => '1'
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);
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end architecture RTL;
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35
src/gamma8bit.vhd
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src/gamma8bit.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity gamma8bit is
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port(
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color_in : in unsigned(7 downto 0);
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color_out : out unsigned(7 downto 0)
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);
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end entity gamma8bit;
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architecture RTL of gamma8bit is
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type gammatable_t is array (0 to 255) of integer range 0 to 255;
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signal table : gammatable_t;
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begin
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table <= (0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 2, 2, 2,
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2, 3, 3, 3, 3, 3, 3, 3, 4, 4, 4, 4, 4, 5, 5, 5,
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5, 6, 6, 6, 6, 7, 7, 7, 7, 8, 8, 8, 9, 9, 9, 10,
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10, 10, 11, 11, 11, 12, 12, 13, 13, 13, 14, 14, 15, 15, 16, 16,
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17, 17, 18, 18, 19, 19, 20, 20, 21, 21, 22, 22, 23, 24, 24, 25,
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25, 26, 27, 27, 28, 29, 29, 30, 31, 32, 32, 33, 34, 35, 35, 36,
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37, 38, 39, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 50,
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51, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 66, 67, 68,
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69, 70, 72, 73, 74, 75, 77, 78, 79, 81, 82, 83, 85, 86, 87, 89,
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90, 92, 93, 95, 96, 98, 99, 101, 102, 104, 105, 107, 109, 110, 112, 114,
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115, 117, 119, 120, 122, 124, 126, 127, 129, 131, 133, 135, 137, 138, 140, 142,
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144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 167, 169, 171, 173, 175,
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177, 180, 182, 184, 186, 189, 191, 193, 196, 198, 200, 203, 205, 208, 210, 213,
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215, 218, 220, 223, 225, 228, 231, 233, 236, 239, 241, 244, 247, 249, 252, 255);
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color_out <= to_unsigned(table(to_integer(color_in)), color_out'length);
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end architecture RTL;
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123
src/ws2812b-phy/ws2812bphy.vhd
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123
src/ws2812b-phy/ws2812bphy.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ws2812bphy is
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generic(
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constant HIGH1 : integer := 40;
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constant LOW1 : integer := 23;
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constant HIGH0 : integer := 20;
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constant LOW0 : integer := 43
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);
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port(
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clk : in std_logic;
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rst : in std_logic;
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busy : out std_logic;
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ws_out : out std_logic;
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strb : in std_logic;
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red : in unsigned(7 downto 0);
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green : in unsigned(7 downto 0);
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blue : in unsigned(7 downto 0)
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);
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end entity ws2812bphy;
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architecture RTL of ws2812bphy is
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type ws_output_state_t is (IDLE, TRANSMITTING, INTERLEDDELAY);
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signal ws_output_state : ws_output_state_t;
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type bitstate_t is (LOW, HIGH);
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signal bitstate : bitstate_t;
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begin
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ws_output : process(clk, rst) is
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variable counter : integer range 0 to 255 := 0;
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variable color_vector : std_logic_vector(23 downto 0);
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variable bitnum : integer range 0 to 23;
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begin
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if rst = '1' then
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ws_output_state <= IDLE;
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color_vector := (others => '0');
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counter := 0;
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bitstate <= LOW;
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bitnum := 0;
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elsif rising_edge(clk) then
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case ws_output_state is
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when IDLE =>
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bitstate <= LOW;
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if strb = '1' then
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ws_output_state <= TRANSMITTING;
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bitnum := 23;
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color_vector := std_logic_vector(green) & std_logic_vector(red) & std_logic_vector(blue);
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counter := 0;
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bitstate <= HIGH;
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end if;
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when TRANSMITTING =>
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case bitstate is
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when HIGH =>
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if color_vector(bitnum) = '1' then
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if counter < HIGH1 then
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counter := counter + 1;
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else
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bitstate <= LOW;
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counter := 0;
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end if;
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else
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if counter < HIGH0 then
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counter := counter + 1;
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else
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bitstate <= LOW;
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counter := 0;
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end if;
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end if;
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when LOW =>
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if color_vector(bitnum) = '1' then
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if counter < LOW1 then
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counter := counter + 1;
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else
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bitstate <= HIGH;
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counter := 0;
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if bitnum = 0 then
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ws_output_state <= INTERLEDDELAY;
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counter := 0;
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bitstate <= LOW;
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else
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bitnum := bitnum - 1;
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end if;
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end if;
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else
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if counter < LOW0 then
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counter := counter + 1;
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else
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bitstate <= HIGH;
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counter := 0;
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if bitnum = 0 then
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ws_output_state <= INTERLEDDELAY;
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counter := 0;
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bitstate <= LOW;
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else
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bitnum := bitnum - 1;
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end if;
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end if;
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end if;
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end case;
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when INTERLEDDELAY =>
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if counter < HIGH1+LOW1+LOW1 then
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counter := counter + 1;
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else
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counter := 0;
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ws_output_state <= IDLE;
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end if;
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end case;
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end if;
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end process ws_output;
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busy <= '0' when ws_output_state = IDLE else '1';
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ws_out <= '1' when bitstate = HIGH else '0';
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end architecture RTL;
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197
src/ws2812test.vhd
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197
src/ws2812test.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ws2812test is
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port(
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clk : in std_logic;
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reset : in std_logic;
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ws_out : out std_logic;
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gamma_req : in std_logic
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);
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end entity ws2812test;
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architecture RTL of ws2812test is
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constant LEDCNT_c : integer := 60;
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constant HEARTBEATMAX_c : integer := 700000;
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signal rst : std_logic;
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signal ws_busy : std_logic;
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signal ws_strb : std_logic;
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signal red_gamma : unsigned(7 downto 0);
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signal green_gamma : unsigned(7 downto 0);
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signal blue_gamma : unsigned(7 downto 0);
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-- Signals for renderer
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signal render_active : std_logic;
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type transition_t is (RY, YG, GC, CB, BM, MR);
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signal transition_active : transition_t;
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type color_rec_t is record
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red : unsigned(7 downto 0);
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green : unsigned(7 downto 0);
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blue : unsigned(7 downto 0);
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end record color_rec_t;
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signal color_active : color_rec_t;
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signal lednum : integer range 0 to LEDCNT_c - 1;
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-- Signals for rainbow
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signal heartbeat : std_logic;
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signal transition_start : transition_t;
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signal color_start : color_rec_t;
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signal red_ws : unsigned(7 downto 0);
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signal green_ws : unsigned(7 downto 0);
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signal blue_ws : unsigned(7 downto 0);
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begin
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rst <= not reset;
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beatgen : process(clk, rst) is
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variable beat_counter : integer range 0 to HEARTBEATMAX_c := 0;
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begin
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if rst = '1' then
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beat_counter := 0;
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heartbeat <= '0';
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elsif rising_edge(clk) then
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heartbeat <= '0';
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if beat_counter /= HEARTBEATMAX_c then
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beat_counter := beat_counter + 1;
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else
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beat_counter := 0;
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heartbeat <= '1';
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end if;
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end if;
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end process beatgen;
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gamma_red : entity work.gamma8bit
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port map(
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color_in => color_active.red,
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color_out => red_gamma
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);
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gamma_green : entity work.gamma8bit
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port map(
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color_in => color_active.green,
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color_out => green_gamma
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);
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gamma_blue : entity work.gamma8bit
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port map(
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color_in => color_active.blue,
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color_out => blue_gamma
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);
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red_ws <= red_gamma when gamma_req = '1' else color_active.red;
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green_ws <= green_gamma when gamma_req = '1' else color_active.green;
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blue_ws <= blue_gamma when gamma_req = '1' else color_active.blue;
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ws2812bphy_inst : entity work.ws2812bphy
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generic map(
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HIGH1 => 40,
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LOW1 => 23,
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HIGH0 => 20,
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LOW0 => 43
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)
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port map(
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clk => clk,
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rst => rst,
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busy => ws_busy,
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ws_out => ws_out,
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strb => ws_strb,
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red => red_ws,
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green => green_ws,
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blue => blue_ws
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);
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rainbow : process(clk, rst) is
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procedure increment_col(signal color : inout unsigned(7 downto 0); is_renderer : boolean; next_state : transition_t) is
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begin
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color <= color + 20;
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if color = 220 then
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if is_renderer then
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transition_active <= next_state;
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else
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transition_start <= next_state;
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end if;
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end if;
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end procedure increment_col;
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procedure decrement_col(signal color : inout unsigned(7 downto 0); is_renderer : boolean; next_state : transition_t) is
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begin
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color <= color - 20;
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if color = 20 then
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if is_renderer then
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transition_active <= next_state;
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else
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transition_start <= next_state;
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end if;
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end if;
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end procedure decrement_col;
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begin
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if rst = '1' then
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render_active <= '1';
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color_active.red <= to_unsigned(240, color_start.red'length);
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color_active.green <= x"00";
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color_active.blue <= x"00";
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color_start.red <= to_unsigned(240, color_start.red'length);
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color_start.green <= x"00";
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color_start.blue <= x"00";
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transition_active <= RY;
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transition_start <= RY;
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lednum <= 0;
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elsif rising_edge(clk) then
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-- renderer
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if render_active = '1' then
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ws_strb <= '0';
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if ws_busy = '0' and ws_strb = '0' then
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ws_strb <= '1';
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case transition_active is
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when RY =>
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increment_col(color_active.green, true, YG);
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when YG =>
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decrement_col(color_active.red, true, GC);
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when GC =>
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increment_col(color_active.blue, true, CB);
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when CB =>
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decrement_col(color_active.green, true, BM);
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when BM =>
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increment_col(color_active.red, true, MR);
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when MR =>
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decrement_col(color_active.blue, true, RY);
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end case;
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end if; -- phy ready
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if ws_strb = '1' then
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if lednum < (LEDCNT_c - 1) then
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lednum <= lednum + 1;
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else
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lednum <= 0;
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render_active <= '0';
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end if;
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end if;
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elsif heartbeat = '1' then
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case transition_start is
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when RY =>
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increment_col(color_start.green, false, YG);
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when YG =>
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decrement_col(color_start.red, false, GC);
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when GC =>
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increment_col(color_start.blue, false, CB);
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when CB =>
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decrement_col(color_start.green, false, BM);
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when BM =>
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increment_col(color_start.red, false, MR);
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when MR =>
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decrement_col(color_start.blue, false, RY);
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end case;
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color_active <= color_start;
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transition_active <= transition_start;
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render_active <= '1';
|
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end if; -- rainbow
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end if; -- rising edge
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||||
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end process rainbow;
|
||||
|
||||
end architecture RTL;
|
||||
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