43 lines
746 B
VHDL
43 lines
746 B
VHDL
library ieee;
|
|
library design;
|
|
|
|
use ieee.std_logic_1164.all;
|
|
use ieee.numeric_std.all;
|
|
use design.all;
|
|
|
|
entity ws2812test_bench is
|
|
end entity ws2812test_bench;
|
|
|
|
architecture RTL of ws2812test_bench is
|
|
signal clk : std_logic;
|
|
signal rst : std_logic;
|
|
signal ws_out : std_logic;
|
|
|
|
begin
|
|
clock_driver : process
|
|
constant period : time := 20 ns;
|
|
begin
|
|
clk <= '0';
|
|
wait for period / 2;
|
|
clk <= '1';
|
|
wait for period / 2;
|
|
end process clock_driver;
|
|
|
|
resetprovider : process is
|
|
begin
|
|
rst <= '0';
|
|
wait for 3 ns;
|
|
rst <= '1';
|
|
wait;
|
|
end process resetprovider;
|
|
|
|
ws2812test_inst : entity design.ws2812test
|
|
port map(
|
|
clk => clk,
|
|
reset => rst,
|
|
ws_out => ws_out,
|
|
gamma_req => '1'
|
|
);
|
|
|
|
end architecture RTL;
|