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7
c/README
7
c/README
@ -1,4 +1,4 @@
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./prog [<mode> <IFNAME>]
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./prog [<mode> <options>]
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mode:
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mode:
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0 is default
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0 is default
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@ -9,7 +9,4 @@ mode:
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3: blue
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3: blue
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4: off
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4: off
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5: white
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5: white
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6: whole string with <options> color
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IFNAME:
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Interface name like "eth0" or "enp5s0"
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enp5s0 is default
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19
c/prog.c
19
c/prog.c
@ -34,17 +34,14 @@ int main(int argc, char *argv[])
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int tx_len = 0;
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int tx_len = 0;
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int mode;
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int mode;
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int i;
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int i;
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unsigned char r,g,b;
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char sendbuf[BUF_SIZ];
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char sendbuf[BUF_SIZ];
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struct ether_header *eh = (struct ether_header *) sendbuf;
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struct ether_header *eh = (struct ether_header *) sendbuf;
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struct iphdr *iph = (struct iphdr *) (sendbuf + sizeof(struct ether_header));
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struct iphdr *iph = (struct iphdr *) (sendbuf + sizeof(struct ether_header));
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struct sockaddr_ll socket_address;
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struct sockaddr_ll socket_address;
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char ifName[IFNAMSIZ];
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char ifName[IFNAMSIZ];
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/* Get interface name */
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strcpy(ifName, DEFAULT_IF);
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if (argc > 2)
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strcpy(ifName, argv[2]);
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else
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strcpy(ifName, DEFAULT_IF);
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if (argc > 1)
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if (argc > 1)
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mode = atoi(argv[1]);
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mode = atoi(argv[1]);
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@ -349,6 +346,18 @@ sendbuf[tx_len++] = 0x00;
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for (i = 0; i< 3*60; i++) {
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for (i = 0; i< 3*60; i++) {
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sendbuf[tx_len++] = 0xff;
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sendbuf[tx_len++] = 0xff;
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}
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}
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} else if (mode == 6) {
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if (argc < 5) return 0;
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r = (unsigned char) atoi(argv[2]);
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g = (unsigned char) atoi(argv[3]);
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b = (unsigned char) atoi(argv[4]);
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for (i = 0; i< 60; i++) {
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sendbuf[tx_len++] = r;
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sendbuf[tx_len++] = g;
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sendbuf[tx_len++] = b;
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}
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}
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}
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39
lattice_wrapper.vhd
Normal file
39
lattice_wrapper.vhd
Normal file
@ -0,0 +1,39 @@
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity lattice_top is
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port (
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clk : in std_logic;
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rst : in std_logic;
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mdio : inout std_logic;
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mdc : out std_logic;
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dv : in std_logic;
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rx : in std_logic_vector(1 downto 0);
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ws_out : out std_logic);
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end entity lattice_top;
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architecture RTL of lattice_top is
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signal rst_hw : std_logic;
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begin -- architecture RTL
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rst_hw <= not rst;
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top_1: entity work.top
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port map (
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clk => clk,
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rst_hw => rst_hw,
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mdio => mdio,
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mdc => mdc,
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rx => rx,
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dv => dv,
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led1 => open,
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led2 => open,
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dat_cnt => open,
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ws_out => ws_out);
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end architecture RTL;
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