fpga/ws2812b-eth
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implemented

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This commit is contained in:
Mario Hüttel 2018-04-13 21:35:44 +02:00
parent 763edd1900
commit ee5da6812c
1 changed files with 13 additions and 6 deletions
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15
top.vhd
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@ -308,12 +308,19 @@ begin -- architecture RTL
dat_cnt_s <= dat_cnt_s +1;
end if;
if eof = '1' then
if crc_valid = '1' then -- or crc_valid = '0' then
recv_state <= WAITFORACK;
if crc_valid = '1' then
if pkg_type = PIPE_PKG then
-- Wait for further frames
-- This is also called with any
-- undefined TYPEFIELD
recv_state <= PRE;
elsif pkg_type = FIN_PKG then
fifo_data_avail <= '1';
--led2 <= '0';
recv_state <= WAITFORACK;
else
--led2 <= '1';
recv_state <= PRE;
end if;
else -- Eth Frame invalid. Discard
fifo_rst <= '1';
recv_state <= PRE;
end if;