edited simulation files

bench/test.vhd

@@ -15,23 +15,25 @@ architecture bench of test is
 	signal mdio    : std_logic;
 	signal led     : std_logic_vector(1 downto 0);
 	signal ws      : std_logic;
+	signal rst_hw  : std_logic;
+	signal dat_cnt : std_logic_vector(3 downto 0);
 begin  -- architecture bench
 
 
 	top_1 : entity work.top
 		port map (
 			clk	=> clk,
-			rst    => rst,
+			rst_hw	=> rst_hw,
 			mdio	=> mdio,
 			mdc	=> mdc,
 			rx	=> rx,
 			dv	=> dv,
 			led1	=> led(0),
 			led2	=> led(1),
+			dat_cnt => dat_cnt,
 			ws_out	=> ws);
 
 
-
 	clkgen : process is
 	begin
 		clk <= '0';
@@ -41,7 +43,7 @@ begin  -- architecture bench
 	end process clkgen;
 
 
-
+	rst_hw <= not rst;
 
 
 	sendphy : process is
@@ -65,7 +67,7 @@ begin  -- architecture bench
 		rst <= '0';
 		dv  <= '0';
 		rx  <= "00";
-		wait for 100 us;
+		wait for 350 us;
 		sendRMII(x"55");
 		sendRMII(x"55");
 		sendRMII(x"55");
@@ -94,7 +96,6 @@ begin  -- architecture bench
 		sendRMII(x"02");
 
 		sendRMII(x"AA");
-
 		sendRMII(x"01");
 		sendRMII(x"02");
 
@@ -103,10 +104,10 @@ begin  -- architecture bench
 		sendRMII(x"AA");
 		sendRMII(x"55");
 		-- Send FCS
-		sendRMII(x"BD");
-		sendRMII(x"9B");
-		sendRMII(x"AC");
-		sendRMII(x"54");
+		sendRMII(x"3A");
+		sendRMII(x"97");
+		sendRMII(x"D9");
+		sendRMII(x"7A");
 
 		-- sendRMII(x"AB");
 

top.vhd

@@ -6,7 +6,7 @@
 -- Author     : Mario Hüttel <mario.huettel@gmx.net>
 -- Company    : 
 -- Created    : 2018-04-05
--- Last update: 2018-04-06
+-- Last update: 2018-04-07
 -- Platform   : 
 -- Standard   : VHDL'93/02
 -------------------------------------------------------------------------------
@@ -36,11 +36,12 @@ entity top is
 end entity top;
 
 architecture RTL of top is
-	constant DELAYCNTVAL : integer			     := 100000;
+	constant DELAYCNTVAL : integer := 100000; -- set to low value for
+						  -- simulation 
 	constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00";
 
 	type smi_state_t is (IDLE, STROBE);
-	type smi_init_state_t is (RESET, INIT, DELAY, INIT_COMPLETE);
+	type smi_init_state_t is (SMI_POR, RESET, INIT, DELAY, INIT_COMPLETE);
 	type ws_send_t is (WS_READY, WS_SYNC, WS_RED, WS_GREEN, WS_BLUE, WS_PIPE, WS_POST);
 	type receive_t is (PRE, DESTMAC, HEADER, RECV, WAITFORACK);
 
@@ -48,7 +49,8 @@ architecture RTL of top is
 	signal dat_cnt_s : unsigned(3 downto 0);
 
 	signal sendstate	 : smi_state_t;
-	signal initstate       : smi_init_state_t := RESET;
+	signal initstate	 : smi_init_state_t := SMI_POR;
+	signal after_delay_state : smi_init_state_t := RESET;
 	signal rst_rxtx		 : std_logic;
 	signal delaycounter	 : unsigned(19 downto 0);
 	signal smi_reg		 : std_logic_vector(4 downto 0);
@@ -186,19 +188,27 @@ begin  -- architecture RTL
 			smi_dat		  <= (others => '0');
 			smi_strb	  <= '0';
 			rst_rxtx	  <= '1';
-			initstate    <= RESET;
+			initstate	  <= SMI_POR;
 			sendstate	  <= IDLE;
+			after_delay_state <= RESET;
 			delaycounter	  <= (others => '0');
 		elsif rising_edge(clk) then
 			smi_strb <= '0';
 			rst_rxtx <= '1';
 			case initstate is
+				when SMI_POR =>
+					after_delay_state <= RESET;
+					delaycounter <= (others => '0');
+					initstate <= DELAY;
 				when RESET =>
+					after_delay_state <= INIT;
+					delaycounter <= (others => '0');
 					sendsmi((others => '0'), x"8000", DELAY);
+					
 				when DELAY =>
 					delaycounter <= delaycounter + 1;
 					if delaycounter = DELAYCNTVAL then  -- Set to 100000
-						initstate <= INIT;
+						initstate <= after_delay_state;
 					end if;
 				when INIT =>
 					sendsmi((others => '0'), "00" & '1' & '1' & "000" & '1' & "00000000", INIT_COMPLETE);