edited simulation files
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@ -67,7 +67,7 @@ begin -- architecture bench
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rst <= '0';
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dv <= '0';
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rx <= "00";
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wait for 100 us;
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wait for 350 us;
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sendRMII(x"55");
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sendRMII(x"55");
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sendRMII(x"55");
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@ -104,10 +104,10 @@ begin -- architecture bench
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sendRMII(x"AA");
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sendRMII(x"55");
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-- Send FCS
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sendRMII(x"2B");
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sendRMII(x"69");
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sendRMII(x"4E");
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sendRMII(x"A8");
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sendRMII(x"3A");
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sendRMII(x"97");
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sendRMII(x"D9");
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sendRMII(x"7A");
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-- sendRMII(x"AB");
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112
top.vhd
112
top.vhd
@ -6,7 +6,7 @@
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-- Author : Mario Hüttel <mario.huettel@gmx.net>
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-- Company :
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-- Created : 2018-04-05
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-- Last update: 2018-04-06
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-- Last update: 2018-04-07
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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@ -36,53 +36,55 @@ entity top is
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end entity top;
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architecture RTL of top is
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constant DELAYCNTVAL : integer := 100000;
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constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00";
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constant DELAYCNTVAL : integer := 100000; -- set to low value for
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-- simulation
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constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00";
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type smi_state_t is (IDLE, STROBE);
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type smi_init_state_t is (RESET, INIT, DELAY, INIT_COMPLETE);
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type smi_init_state_t is (SMI_POR, RESET, INIT, DELAY, INIT_COMPLETE);
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type ws_send_t is (WS_READY, WS_SYNC, WS_RED, WS_GREEN, WS_BLUE, WS_PIPE, WS_POST);
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type receive_t is (PRE, DESTMAC, HEADER, RECV, WAITFORACK);
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signal rst : std_logic;
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signal rst : std_logic;
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signal dat_cnt_s : unsigned(3 downto 0);
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signal sendstate : smi_state_t;
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signal initstate : smi_init_state_t := RESET;
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signal rst_rxtx : std_logic;
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signal delaycounter : unsigned(19 downto 0);
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signal smi_reg : std_logic_vector(4 downto 0);
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signal smi_dat : std_logic_vector(15 downto 0);
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signal smi_strb : std_logic;
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signal smi_busy : std_logic;
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signal sendstate : smi_state_t;
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signal initstate : smi_init_state_t := SMI_POR;
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signal after_delay_state : smi_init_state_t := RESET;
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signal rst_rxtx : std_logic;
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signal delaycounter : unsigned(19 downto 0);
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signal smi_reg : std_logic_vector(4 downto 0);
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signal smi_dat : std_logic_vector(15 downto 0);
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signal smi_strb : std_logic;
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signal smi_busy : std_logic;
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---
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signal sof : std_logic;
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signal eof : std_logic;
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signal eth_dat : std_logic_vector(7 downto 0);
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signal eth_strb : std_logic;
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signal crc_valid : std_logic;
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signal sof : std_logic;
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signal eof : std_logic;
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signal eth_dat : std_logic_vector(7 downto 0);
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signal eth_strb : std_logic;
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signal crc_valid : std_logic;
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--
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signal fifo_in : std_logic_vector(7 downto 0);
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signal fifo_out : std_logic_vector(7 downto 0);
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signal fifo_wr : std_logic;
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signal fifo_rd : std_logic;
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signal fifo_rst : std_logic;
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signal fifo_full : std_logic;
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signal fifo_empty : std_logic;
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signal fifo_in : std_logic_vector(7 downto 0);
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signal fifo_out : std_logic_vector(7 downto 0);
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signal fifo_wr : std_logic;
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signal fifo_rd : std_logic;
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signal fifo_rst : std_logic;
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signal fifo_full : std_logic;
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signal fifo_empty : std_logic;
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--
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signal fifo_data_avail : std_logic;
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signal fifo_data_ack : std_logic;
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signal recv_state : receive_t;
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signal mac : std_logic_vector(47 downto 0);
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signal recv_cnt : integer range 0 to 15;
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signal fifo_data_avail : std_logic;
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signal fifo_data_ack : std_logic;
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signal recv_state : receive_t;
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signal mac : std_logic_vector(47 downto 0);
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signal recv_cnt : integer range 0 to 15;
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--
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signal ws_busy : std_logic;
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signal ws_strb : std_logic;
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signal red : unsigned(7 downto 0);
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signal green : unsigned(7 downto 0);
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signal blue : unsigned(7 downto 0);
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signal ws_busy : std_logic;
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signal ws_strb : std_logic;
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signal red : unsigned(7 downto 0);
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signal green : unsigned(7 downto 0);
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signal blue : unsigned(7 downto 0);
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--
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signal ws_state : ws_send_t;
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signal ws_state : ws_send_t;
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begin -- architecture RTL
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@ -182,23 +184,31 @@ begin -- architecture RTL
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begin
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if rst = '1' then
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smi_reg <= (others => '0');
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smi_dat <= (others => '0');
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smi_strb <= '0';
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rst_rxtx <= '1';
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initstate <= RESET;
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sendstate <= IDLE;
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delaycounter <= (others => '0');
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smi_reg <= (others => '0');
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smi_dat <= (others => '0');
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smi_strb <= '0';
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rst_rxtx <= '1';
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initstate <= SMI_POR;
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sendstate <= IDLE;
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after_delay_state <= RESET;
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delaycounter <= (others => '0');
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elsif rising_edge(clk) then
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smi_strb <= '0';
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rst_rxtx <= '1';
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case initstate is
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when SMI_POR =>
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after_delay_state <= RESET;
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delaycounter <= (others => '0');
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initstate <= DELAY;
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when RESET =>
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after_delay_state <= INIT;
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delaycounter <= (others => '0');
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sendsmi((others => '0'), x"8000", DELAY);
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when DELAY =>
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delaycounter <= delaycounter + 1;
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if delaycounter = DELAYCNTVAL then -- Set to 100000
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initstate <= INIT;
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initstate <= after_delay_state;
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end if;
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when INIT =>
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sendsmi((others => '0'), "00" & '1' & '1' & "000" & '1' & "00000000", INIT_COMPLETE);
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@ -218,9 +228,9 @@ begin -- architecture RTL
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fifo_in <= (others => '0');
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fifo_data_avail <= '0';
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recv_state <= PRE;
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dat_cnt_s <= (others => '0');
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led1 <= '1';
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led2 <= '1';
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dat_cnt_s <= (others => '0');
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led1 <= '1';
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led2 <= '1';
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recv_cnt <= 0;
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mac <= (others => '0');
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elsif rising_edge(clk) then -- rising clock edge
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@ -257,7 +267,7 @@ begin -- architecture RTL
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if recv_cnt = 7 then
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if mac = DEFMAC then
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recv_state <= RECV;
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dat_cnt_s <= (others =>'0');
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dat_cnt_s <= (others => '0');
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else
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recv_state <= PRE;
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@ -267,12 +277,12 @@ begin -- architecture RTL
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when RECV =>
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led2 <= '0';
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if eth_strb = '1' and fifo_full /= '1' then
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fifo_in <= eth_dat;
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fifo_wr <= '1';
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fifo_in <= eth_dat;
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fifo_wr <= '1';
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dat_cnt_s <= dat_cnt_s +1;
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end if;
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if eof = '1' then
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if crc_valid = '1' then-- or crc_valid = '0' then
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if crc_valid = '1' then -- or crc_valid = '0' then
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recv_state <= WAITFORACK;
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fifo_data_avail <= '1';
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--led2 <= '0';
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