fpga/ws2812b-eth
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Compare commits

base: fpga:c909e0c7030ef98a6c130c17e6f8edaa09d3ca24
Branches Tags
fpga:master
fpga:dev-multipack
..
compare: fpga:75c50b63c12576283976f755e591e9e48c1b2452
Branches Tags
fpga:dev-multipack
fpga:master

No commits in common. "c909e0c7030ef98a6c130c17e6f8edaa09d3ca24" and "75c50b63c12576283976f755e591e9e48c1b2452" have entirely different histories.
c909e0c703 ... 75c50b63c1

2 changed files with 77 additions and 88 deletions
Show Stats Expand all files Collapse all files

19
bench/test.vhd
View File

@ -15,25 +15,23 @@ architecture bench of test is
signal mdio : std_logic; signal mdio : std_logic;
signal led : std_logic_vector(1 downto 0); signal led : std_logic_vector(1 downto 0);
signal ws : std_logic; signal ws : std_logic;
signal rst_hw : std_logic;
signal dat_cnt : std_logic_vector(3 downto 0);
begin -- architecture bench begin -- architecture bench
top_1 : entity work.top top_1 : entity work.top
port map ( port map (
clk => clk, clk => clk,
rst_hw => rst_hw, rst => rst,
mdio => mdio, mdio => mdio,
mdc => mdc, mdc => mdc,
rx => rx, rx => rx,
dv => dv, dv => dv,
led1 => led(0), led1 => led(0),
led2 => led(1), led2 => led(1),
dat_cnt => dat_cnt,
ws_out => ws); ws_out => ws);
clkgen : process is clkgen : process is
begin begin
clk <= '0'; clk <= '0';
@ -43,7 +41,7 @@ begin -- architecture bench
end process clkgen; end process clkgen;
rst_hw <= not rst;
sendphy : process is sendphy : process is
@ -67,7 +65,7 @@ begin -- architecture bench
rst <= '0'; rst <= '0';
dv <= '0'; dv <= '0';
rx <= "00"; rx <= "00";
wait for 350 us; wait for 100 us;
sendRMII(x"55"); sendRMII(x"55");
sendRMII(x"55"); sendRMII(x"55");
sendRMII(x"55"); sendRMII(x"55");
@ -96,6 +94,7 @@ begin -- architecture bench
sendRMII(x"02"); sendRMII(x"02");
sendRMII(x"AA"); sendRMII(x"AA");
sendRMII(x"01"); sendRMII(x"01");
sendRMII(x"02"); sendRMII(x"02");
@ -104,10 +103,10 @@ begin -- architecture bench
sendRMII(x"AA"); sendRMII(x"AA");
sendRMII(x"55"); sendRMII(x"55");
-- Send FCS -- Send FCS
sendRMII(x"3A"); sendRMII(x"BD");
sendRMII(x"97"); sendRMII(x"9B");
sendRMII(x"D9"); sendRMII(x"AC");
sendRMII(x"7A"); sendRMII(x"54");
-- sendRMII(x"AB"); -- sendRMII(x"AB");

22
top.vhd
View File

@ -6,7 +6,7 @@
-- Author : Mario Hüttel <mario.huettel@gmx.net> -- Author : Mario Hüttel <mario.huettel@gmx.net>
-- Company : -- Company :
-- Created : 2018-04-05 -- Created : 2018-04-05
-- Last update: 2018-04-07 -- Last update: 2018-04-06
-- Platform : -- Platform :
-- Standard : VHDL'93/02 -- Standard : VHDL'93/02
------------------------------------------------------------------------------- -------------------------------------------------------------------------------
@ -36,12 +36,11 @@ entity top is
end entity top; end entity top;
architecture RTL of top is architecture RTL of top is
constant DELAYCNTVAL : integer := 100000; -- set to low value for constant DELAYCNTVAL : integer := 100000;
-- simulation
constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00"; constant DEFMAC : std_logic_vector(47 downto 0) := x"00DEADBEEF00";
type smi_state_t is (IDLE, STROBE); type smi_state_t is (IDLE, STROBE);
type smi_init_state_t is (SMI_POR, RESET, INIT, DELAY, INIT_COMPLETE); type smi_init_state_t is (RESET, INIT, DELAY, INIT_COMPLETE);
type ws_send_t is (WS_READY, WS_SYNC, WS_RED, WS_GREEN, WS_BLUE, WS_PIPE, WS_POST); type ws_send_t is (WS_READY, WS_SYNC, WS_RED, WS_GREEN, WS_BLUE, WS_PIPE, WS_POST);
type receive_t is (PRE, DESTMAC, HEADER, RECV, WAITFORACK); type receive_t is (PRE, DESTMAC, HEADER, RECV, WAITFORACK);
@ -49,8 +48,7 @@ architecture RTL of top is
signal dat_cnt_s : unsigned(3 downto 0); signal dat_cnt_s : unsigned(3 downto 0);
signal sendstate : smi_state_t; signal sendstate : smi_state_t;
signal initstate : smi_init_state_t := SMI_POR; signal initstate : smi_init_state_t := RESET;
signal after_delay_state : smi_init_state_t := RESET;
signal rst_rxtx : std_logic; signal rst_rxtx : std_logic;
signal delaycounter : unsigned(19 downto 0); signal delaycounter : unsigned(19 downto 0);
signal smi_reg : std_logic_vector(4 downto 0); signal smi_reg : std_logic_vector(4 downto 0);
@ -188,27 +186,19 @@ begin -- architecture RTL
smi_dat <= (others => '0'); smi_dat <= (others => '0');
smi_strb <= '0'; smi_strb <= '0';
rst_rxtx <= '1'; rst_rxtx <= '1';
initstate <= SMI_POR; initstate <= RESET;
sendstate <= IDLE; sendstate <= IDLE;
after_delay_state <= RESET;
delaycounter <= (others => '0'); delaycounter <= (others => '0');
elsif rising_edge(clk) then elsif rising_edge(clk) then
smi_strb <= '0'; smi_strb <= '0';
rst_rxtx <= '1'; rst_rxtx <= '1';
case initstate is case initstate is
when SMI_POR =>
after_delay_state <= RESET;
delaycounter <= (others => '0');
initstate <= DELAY;
when RESET => when RESET =>
after_delay_state <= INIT;
delaycounter <= (others => '0');
sendsmi((others => '0'), x"8000", DELAY); sendsmi((others => '0'), x"8000", DELAY);
when DELAY => when DELAY =>
delaycounter <= delaycounter + 1; delaycounter <= delaycounter + 1;
if delaycounter = DELAYCNTVAL then -- Set to 100000 if delaycounter = DELAYCNTVAL then -- Set to 100000
initstate <= after_delay_state; initstate <= INIT;
end if; end if;
when INIT => when INIT =>
sendsmi((others => '0'), "00" & '1' & '1' & "000" & '1' & "00000000", INIT_COMPLETE); sendsmi((others => '0'), "00" & '1' & '1' & "000" & '1' & "00000000", INIT_COMPLETE);