implemented first draft
This commit is contained in:
commit
660765e332
3
.gitignore
vendored
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3
.gitignore
vendored
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*.o
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*~
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187
bench.vhd
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187
bench.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity bench is
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end entity bench;
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architecture sim of bench is
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signal clk : std_logic;
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signal rst_hw : std_logic;
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signal sck : std_logic;
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signal mosi : std_logic;
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signal cs : std_logic;
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signal ready : std_logic;
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signal ws_out : std_logic;
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begin -- architecture sim
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top_1 : entity work.top
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port map (
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clk => clk,
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rst_hw => rst_hw,
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sck => sck,
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mosi => mosi,
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cs => cs,
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ready => ready,
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ws_out => ws_out);
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clk_gen : process is
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begin
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clk <= '0';
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wait for 10 ns;
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clk <= '1';
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wait for 10 ns;
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end process clk_gen;
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rst_gen : process is
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begin
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rst_hw <= '1';
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wait for 15 ns;
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rst_hw <= '0';
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wait;
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end process rst_gen;
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sck_gen : process is
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begin
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sck <= '0';
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wait for 40 ns;
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sck <= '1';
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wait for 40 ns;
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end process sck_gen;
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send_spi : process is
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procedure send24(dat : in std_logic_vector(23 downto 0)) is
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variable data : std_logic_vector(dat'range);
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begin
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cs <= '1';
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if ready /= '1' then
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wait until ready = '1';
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end if;
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wait for 30 ns;
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data := dat;
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '1';
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end send24;
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begin
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cs <= '1';
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wait for 50 ns;
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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wait;
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end process send_spi;
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end architecture sim;
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96
fifo.vhd
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96
fifo.vhd
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@ -0,0 +1,96 @@
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-- Thanks to: http://www.deathbylogic.com/2013/07/vhdl-standard-fifo/
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library IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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entity STD_FIFO is
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Generic (
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DATA_WIDTH : positive := 8;
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FIFO_DEPTH : positive := 256
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);
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Port (
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CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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WriteEn : in STD_LOGIC;
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DataIn : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
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ReadEn : in STD_LOGIC;
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DataOut : out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
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Empty : out STD_LOGIC;
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Full : out STD_LOGIC
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);
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end STD_FIFO;
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architecture Behavioral of STD_FIFO is
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begin
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-- Memory Pointer Process
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fifo_proc : process (CLK)
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type FIFO_Memory is array (0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
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variable Memory : FIFO_Memory;
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variable Head : natural range 0 to FIFO_DEPTH - 1;
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variable Tail : natural range 0 to FIFO_DEPTH - 1;
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variable Looped : boolean;
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begin
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if rising_edge(CLK) then
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if RST = '1' then
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Head := 0;
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Tail := 0;
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Looped := false;
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Full <= '0';
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Empty <= '1';
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else
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if (ReadEn = '1') then
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if ((Looped = true) or (Head /= Tail)) then
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-- Update data output
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DataOut <= Memory(Tail);
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-- Update Tail pointer as needed
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if (Tail = FIFO_DEPTH - 1) then
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Tail := 0;
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Looped := false;
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else
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Tail := Tail + 1;
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end if;
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end if;
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end if;
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if (WriteEn = '1') then
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if ((Looped = false) or (Head /= Tail)) then
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-- Write Data to Memory
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Memory(Head) := DataIn;
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-- Increment Head pointer as needed
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if (Head = FIFO_DEPTH - 1) then
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Head := 0;
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Looped := true;
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else
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Head := Head + 1;
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end if;
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end if;
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end if;
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-- Update Empty and Full flags
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if (Head = Tail) then
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if Looped then
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Full <= '1';
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else
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Empty <= '1';
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end if;
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else
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Empty <= '0';
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Full <= '0';
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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113
spi_slave.vhd
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113
spi_slave.vhd
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@ -0,0 +1,113 @@
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-------------------------------------------------------------------------------
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-- Title : simple SPI slave
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-- Project :
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-------------------------------------------------------------------------------
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-- File : spi_slave.vhd
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-- Author : Mario Hüttel <mario.huettel@gmx.net>
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-- Company :
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-- Created : 2018-04-15
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-- Last update: 2018-04-15
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: This SPI slaves samples the SPI's sck line
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-- Therefore freq(clk) > 2.5 * freq(sck)
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-------------------------------------------------------------------------------
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-- Copyright (c) 2018
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity spi_slave is
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generic (
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DAT_WIDTH : natural := 8);
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port (
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clk : in std_logic;
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rst : in std_logic;
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cs : in std_logic;
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sck : in std_logic;
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miso : out std_logic;
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mosi : in std_logic;
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dat_o : out std_logic_vector(DAT_WIDTH - 1 downto 0);
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dat_i : in std_logic_vector(DAT_WIDTH - 1 downto 0);
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dat_o_strb : out std_logic;
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dat_i_ack : out std_logic);
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end entity spi_slave;
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architecture RTL of spi_slave is
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signal sck_old : std_logic;
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signal sck_sync : std_logic;
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signal mosi_sync : std_logic;
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signal cs_sync : std_logic;
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signal pos_edge : std_logic;
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signal neg_edge : std_logic;
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signal miso_int : std_logic;
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signal cnt : integer range 0 to DAT_WIDTH-1;
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signal shift_reg : std_logic_vector(DAT_WIDTH -1 downto 0);
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begin -- architecture RTL
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sync : process (clk, rst) is
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begin -- process sck_sync
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if rst = '1' then -- asynchronous reset (active high)
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sck_sync <= '0';
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mosi_sync <= '0';
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cs_sync <= '0';
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elsif rising_edge(clk) then -- rising clock edge
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cs_sync <= cs;
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mosi_sync <= mosi;
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sck_sync <= sck;
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end if;
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end process sync;
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edge_detector : process (clk, rst) is
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begin -- process edge_detector
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if rst = '1' then -- asynchronous reset (active high)
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pos_edge <= '0';
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neg_edge <= '0';
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elsif rising_edge(clk) then -- rising clock edge
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neg_edge <= '0';
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pos_edge <= '0';
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sck_old <= sck_sync;
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if sck_old = '1' and sck_sync = '0' then
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neg_edge <= '1';
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elsif sck_old = '0' and sck_sync = '1' then
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pos_edge <= '1';
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end if;
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end if;
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end process edge_detector;
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shifter : process (clk, rst) is
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begin -- process shifter
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if rst = '1' then -- asynchronous reset (active high)
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shift_reg <= (others => '0');
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dat_i_ack <= '0';
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dat_o <= (others => '0');
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miso_int <= '0';
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cnt <= 0;
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elsif rising_edge(clk) then -- rising clock edge
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dat_i_ack <= '0';
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dat_o_strb <= '0';
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if pos_edge = '1' and cs_sync = '0' then
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shift_reg <= shift_reg(DAT_WIDTH-2 downto 0) & mosi_sync;
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miso_int <= shift_reg(7);
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if cnt < DAT_WIDTH-1 then
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cnt <= cnt + 1;
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else
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cnt <= 0;
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end if;
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if cnt = DAT_WIDTH - 1 then
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dat_o <= shift_reg(DAT_WIDTH -2 downto 0) & mosi_sync;
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dat_o_strb <= '1';
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shift_reg <= dat_i;
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dat_i_ack <= '1';
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end if;
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end if;
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end if;
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end process shifter;
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miso <= miso_int when cs = '0' else 'Z';
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end architecture RTL;
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184
top.vhd
Normal file
184
top.vhd
Normal file
@ -0,0 +1,184 @@
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-------------------------------------------------------------------------------
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-- Title : Top Level of SPI => WS2812b
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-- Project :
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-------------------------------------------------------------------------------
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-- File : top.vhd
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-- Author : Mario Hüttel <mario.huettel@gmx.net>
|
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-- Company :
|
||||
-- Created : 2018-04-15
|
||||
-- Last update: 2018-04-15
|
||||
-- Platform :
|
||||
-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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||||
-- Description:
|
||||
-------------------------------------------------------------------------------
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||||
-- Copyright (c) 2018 GPLv2
|
||||
-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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||||
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entity top is
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port (
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clk : in std_logic;
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rst_hw : in std_logic;
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sck : in std_logic;
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mosi : in std_logic;
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cs : in std_logic;
|
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ready : out std_logic; -- goes high when at least 10 LEDs can
|
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-- be accepted
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ws_out : out std_logic);
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end entity top;
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architecture RTL of top is
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constant FIFO_DEPTH : positive := 20;
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signal rst : std_logic;
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signal fifo_empty : std_logic;
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signal fifo_full : std_logic;
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||||
signal fifo_wr : std_logic;
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signal fifo_rd : std_logic;
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||||
signal fifo_i : std_logic_vector(23 downto 0);
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signal fifo_o : std_logic_vector(23 downto 0);
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signal spi_dat_o : std_logic_vector(23 downto 0);
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signal spi_dat_o_strb : std_logic;
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signal fifo_fill_cnt : integer range 0 to FIFO_DEPTH;
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signal ws_strb : std_logic;
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signal red : unsigned(7 downto 0);
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signal green : unsigned(7 downto 0);
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signal blue : unsigned(7 downto 0);
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signal ws_busy : std_logic;
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signal fifo_inc : std_logic;
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||||
signal fifo_dec : std_logic;
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signal fifo_data_req : std_logic;
|
||||
signal fifo_data_avail : std_logic;
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||||
begin -- architecture RTL
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||||
|
||||
reset_sync : process (clk, rst_hw) is
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||||
begin -- process reset_sync
|
||||
if rst_hw = '1' then -- asynchronous reset (active high)
|
||||
rst <= '1';
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
rst <= rst_hw;
|
||||
end if;
|
||||
end process reset_sync;
|
||||
|
||||
STD_FIFO_1 : entity work.STD_FIFO
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||||
generic map (
|
||||
DATA_WIDTH => 24,
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||||
FIFO_DEPTH => FIFO_DEPTH) -- 20 LEDs FIFO depth
|
||||
port map (
|
||||
CLK => clk,
|
||||
RST => rst,
|
||||
WriteEn => fifo_wr,
|
||||
DataIn => fifo_i,
|
||||
ReadEn => fifo_rd,
|
||||
DataOut => fifo_o,
|
||||
Empty => fifo_empty,
|
||||
Full => fifo_full);
|
||||
|
||||
spi_slave_1 : entity work.spi_slave
|
||||
generic map (
|
||||
DAT_WIDTH => 24)
|
||||
port map (
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
cs => cs,
|
||||
sck => sck,
|
||||
miso => open,
|
||||
mosi => mosi,
|
||||
dat_o => spi_dat_o,
|
||||
dat_i => (others => '0'),
|
||||
dat_o_strb => spi_dat_o_strb,
|
||||
dat_i_ack => open);
|
||||
|
||||
ws2812bphy_1 : entity work.ws2812bphy
|
||||
generic map (
|
||||
HIGH1 => 40,
|
||||
LOW1 => 23,
|
||||
HIGH0 => 20,
|
||||
LOW0 => 43)
|
||||
port map (
|
||||
clk => clk,
|
||||
rst => rst,
|
||||
busy => ws_busy,
|
||||
ws_out => ws_out,
|
||||
strb => ws_strb,
|
||||
red => red,
|
||||
green => green,
|
||||
blue => blue);
|
||||
|
||||
fill_cnt_proc : process (clk, rst) is
|
||||
variable inc_dec : std_logic_vector(1 downto 0);
|
||||
begin -- process fill_cnt_proc
|
||||
if rst = '1' then -- asynchronous reset (active high)
|
||||
fifo_fill_cnt <= 0;
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
inc_dec := fifo_inc & fifo_dec;
|
||||
if inc_dec = "10" then
|
||||
fifo_fill_cnt <= fifo_fill_cnt + 1;
|
||||
elsif inc_dec = "01" then
|
||||
fifo_fill_cnt <= fifo_fill_cnt -1;
|
||||
end if;
|
||||
end if;
|
||||
end process fill_cnt_proc;
|
||||
|
||||
ready <= '1' when fifo_fill_cnt <= 10 else '0';
|
||||
|
||||
spi2fifo_proc : process (clk, rst) is
|
||||
begin -- process spi2fifo_proc
|
||||
if rst = '1' then -- asynchronous reset (active high)
|
||||
fifo_inc <= '0';
|
||||
fifo_wr <= '0';
|
||||
fifo_i <= (others => '0');
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
fifo_wr <= '0';
|
||||
fifo_inc <= '0';
|
||||
if spi_dat_o_strb = '1' and fifo_full /= '1' then
|
||||
fifo_wr <= '1';
|
||||
fifo_i <= spi_dat_o;
|
||||
fifo_inc <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end process spi2fifo_proc;
|
||||
|
||||
fifo2ws_proc : process (clk, rst) is
|
||||
begin -- process fifo2ws_proc
|
||||
if rst = '1' then -- asynchronous reset (active high)
|
||||
fifo_rd <= '0';
|
||||
fifo_dec <= '0';
|
||||
ws_strb <= '0';
|
||||
red <= x"00";
|
||||
blue <= x"00";
|
||||
green <= x"00";
|
||||
fifo_data_req <= '0';
|
||||
fifo_data_avail <= '0';
|
||||
elsif rising_edge(clk) then -- rising clock edge
|
||||
fifo_rd <= '0';
|
||||
ws_strb <= '0';
|
||||
fifo_dec <= '0';
|
||||
-- TODO: Write following lines as statemachine
|
||||
if fifo_empty = '0' and fifo_data_req = '0' and fifo_data_avail = '0' then
|
||||
fifo_data_req <= '1';
|
||||
fifo_rd <= '1';
|
||||
fifo_dec <= '1';
|
||||
end if;
|
||||
if fifo_data_req = '1' then
|
||||
fifo_data_avail <= '1';
|
||||
fifo_data_req <= '0';
|
||||
end if;
|
||||
if ws_busy = '0' and ws_strb = '0' and fifo_data_avail = '1' then
|
||||
red <= unsigned(fifo_o(23 downto 16));
|
||||
green <= unsigned(fifo_o(15 downto 8));
|
||||
blue <= unsigned(fifo_o(7 downto 0));
|
||||
ws_strb <= '1';
|
||||
fifo_data_avail <= '0';
|
||||
end if;
|
||||
end if;
|
||||
end process fifo2ws_proc;
|
||||
|
||||
end architecture RTL;
|
||||
|
||||
|
||||
121
ws2812/ws2812bphy.vhd
Normal file
121
ws2812/ws2812bphy.vhd
Normal file
@ -0,0 +1,121 @@
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use ieee.numeric_std.all;
|
||||
|
||||
entity ws2812bphy is
|
||||
generic(
|
||||
HIGH1 : integer := 40;
|
||||
LOW1 : integer := 23;
|
||||
HIGH0 : integer := 20;
|
||||
LOW0 : integer := 43);
|
||||
port(
|
||||
clk : in std_logic;
|
||||
rst : in std_logic;
|
||||
busy : out std_logic;
|
||||
ws_out : out std_logic;
|
||||
strb : in std_logic;
|
||||
red : in unsigned(7 downto 0);
|
||||
green : in unsigned(7 downto 0);
|
||||
blue : in unsigned(7 downto 0));
|
||||
end entity ws2812bphy;
|
||||
|
||||
architecture RTL of ws2812bphy is
|
||||
|
||||
type ws_output_state_t is (IDLE, TRANSMITTING, INTERLEDDELAY);
|
||||
signal ws_output_state : ws_output_state_t;
|
||||
|
||||
type bitstate_t is (LOW, HIGH);
|
||||
signal bitstate : bitstate_t;
|
||||
|
||||
begin
|
||||
ws_output : process(clk, rst) is
|
||||
variable counter : integer range 0 to 255 := 0;
|
||||
|
||||
variable color_vector : std_logic_vector(23 downto 0);
|
||||
variable bitnum : integer range 0 to 23;
|
||||
begin
|
||||
if rst = '1' then
|
||||
ws_output_state <= IDLE;
|
||||
color_vector := (others => '0');
|
||||
counter := 0;
|
||||
bitstate <= LOW;
|
||||
bitnum := 0;
|
||||
elsif rising_edge(clk) then
|
||||
case ws_output_state is
|
||||
when IDLE =>
|
||||
bitstate <= LOW;
|
||||
if strb = '1' then
|
||||
ws_output_state <= TRANSMITTING;
|
||||
bitnum := 23;
|
||||
color_vector := std_logic_vector(green) & std_logic_vector(red) & std_logic_vector(blue);
|
||||
counter := 0;
|
||||
bitstate <= HIGH;
|
||||
end if;
|
||||
when TRANSMITTING =>
|
||||
case bitstate is
|
||||
when HIGH =>
|
||||
if color_vector(bitnum) = '1' then
|
||||
if counter < HIGH1 - 1 then
|
||||
counter := counter + 1;
|
||||
else
|
||||
bitstate <= LOW;
|
||||
counter := 0;
|
||||
end if;
|
||||
else
|
||||
if counter < HIGH0 -1 then
|
||||
counter := counter + 1;
|
||||
else
|
||||
bitstate <= LOW;
|
||||
counter := 0;
|
||||
end if;
|
||||
end if;
|
||||
when LOW =>
|
||||
if color_vector(bitnum) = '1' then
|
||||
if counter < LOW1 -1 then
|
||||
counter := counter + 1;
|
||||
else
|
||||
bitstate <= HIGH;
|
||||
counter := 0;
|
||||
if bitnum = 0 then
|
||||
ws_output_state <= INTERLEDDELAY;
|
||||
counter := 0;
|
||||
bitstate <= LOW;
|
||||
else
|
||||
bitnum := bitnum - 1;
|
||||
end if;
|
||||
end if;
|
||||
else
|
||||
if counter < LOW0 - 1 then
|
||||
counter := counter + 1;
|
||||
else
|
||||
bitstate <= HIGH;
|
||||
counter := 0;
|
||||
|
||||
if bitnum = 0 then
|
||||
ws_output_state <= INTERLEDDELAY;
|
||||
counter := 0;
|
||||
bitstate <= LOW;
|
||||
else
|
||||
bitnum := bitnum - 1;
|
||||
end if;
|
||||
|
||||
end if;
|
||||
end if;
|
||||
|
||||
end case;
|
||||
|
||||
when INTERLEDDELAY =>
|
||||
if counter < HIGH1+LOW1+LOW1 then
|
||||
counter := counter + 1;
|
||||
else
|
||||
counter := 0;
|
||||
ws_output_state <= IDLE;
|
||||
end if;
|
||||
|
||||
end case;
|
||||
end if;
|
||||
end process ws_output;
|
||||
busy <= '0' when ws_output_state = IDLE else '1';
|
||||
ws_out <= '1' when bitstate = HIGH else '0';
|
||||
|
||||
end architecture RTL;
|
||||
Loading…
Reference in New Issue
Block a user