implemented first draft

2018-04-15 20:33:13 +02:00
commit 660765e332
6 changed files with 704 additions and 0 deletions
--- a/ws2812/ws2812bphy.vhd
+++ b/ws2812/ws2812bphy.vhd
@@ -0,0 +1,121 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ws2812bphy is
+	generic(
+		HIGH1 : integer := 40;
+		LOW1  : integer := 23;
+		HIGH0 : integer := 20;
+		LOW0  : integer := 43);
+	port(
+		clk    : in  std_logic;
+		rst    : in  std_logic;
+		busy   : out std_logic;
+		ws_out : out std_logic;
+		strb   : in  std_logic;
+		red    : in  unsigned(7 downto 0);
+		green  : in  unsigned(7 downto 0);
+		blue   : in  unsigned(7 downto 0));
+end entity ws2812bphy;
+
+architecture RTL of ws2812bphy is
+
+	type ws_output_state_t is (IDLE, TRANSMITTING, INTERLEDDELAY);
+	signal ws_output_state : ws_output_state_t;
+
+	type bitstate_t is (LOW, HIGH);
+	signal bitstate : bitstate_t;
+
+begin
+	ws_output : process(clk, rst) is
+		variable counter : integer range 0 to 255 := 0;
+
+		variable color_vector : std_logic_vector(23 downto 0);
+		variable bitnum	      : integer range 0 to 23;
+	begin
+		if rst = '1' then
+			ws_output_state <= IDLE;
+			color_vector	:= (others => '0');
+			counter		:= 0;
+			bitstate	<= LOW;
+			bitnum		:= 0;
+		elsif rising_edge(clk) then
+			case ws_output_state is
+				when IDLE =>
+					bitstate <= LOW;
+					if strb = '1' then
+						ws_output_state <= TRANSMITTING;
+						bitnum		:= 23;
+						color_vector	:= std_logic_vector(green) & std_logic_vector(red) & std_logic_vector(blue);
+						counter		:= 0;
+						bitstate	<= HIGH;
+					end if;
+				when TRANSMITTING =>
+					case bitstate is
+						when HIGH =>
+							if color_vector(bitnum) = '1' then
+								if counter < HIGH1 - 1 then
+									counter := counter + 1;
+								else
+									bitstate <= LOW;
+									counter	 := 0;
+								end if;
+							else
+								if counter < HIGH0 -1 then
+									counter := counter + 1;
+								else
+									bitstate <= LOW;
+									counter	 := 0;
+								end if;
+							end if;
+						when LOW =>
+							if color_vector(bitnum) = '1' then
+								if counter < LOW1 -1 then
+									counter := counter + 1;
+								else
+									bitstate <= HIGH;
+									counter	 := 0;
+									if bitnum = 0 then
+										ws_output_state <= INTERLEDDELAY;
+										counter		:= 0;
+										bitstate	<= LOW;
+									else
+										bitnum := bitnum - 1;
+									end if;
+								end if;
+							else
+								if counter < LOW0 - 1 then
+									counter := counter + 1;
+								else
+									bitstate <= HIGH;
+									counter	 := 0;
+
+									if bitnum = 0 then
+										ws_output_state <= INTERLEDDELAY;
+										counter		:= 0;
+										bitstate	<= LOW;
+									else
+										bitnum := bitnum - 1;
+									end if;
+
+								end if;
+							end if;
+
+					end case;
+
+				when INTERLEDDELAY =>
+					if counter < HIGH1+LOW1+LOW1 then
+						counter := counter + 1;
+					else
+						counter		:= 0;
+						ws_output_state <= IDLE;
+					end if;
+
+			end case;
+		end if;
+	end process ws_output;
+	busy   <= '0' when ws_output_state = IDLE else '1';
+	ws_out <= '1' when bitstate = HIGH	  else '0';
+
+end architecture RTL;