188 lines
4.1 KiB
VHDL
188 lines
4.1 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity bench is
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end entity bench;
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architecture sim of bench is
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signal clk : std_logic;
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signal rst_hw : std_logic;
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signal sck : std_logic;
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signal mosi : std_logic;
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signal cs : std_logic;
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signal ready : std_logic;
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signal ws_out : std_logic;
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begin -- architecture sim
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top_1 : entity work.top
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port map (
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clk => clk,
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rst_hw => rst_hw,
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sck => sck,
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mosi => mosi,
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cs => cs,
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ready => ready,
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ws_out => ws_out);
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clk_gen : process is
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begin
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clk <= '0';
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wait for 10 ns;
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clk <= '1';
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wait for 10 ns;
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end process clk_gen;
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rst_gen : process is
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begin
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rst_hw <= '1';
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wait for 15 ns;
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rst_hw <= '0';
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wait;
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end process rst_gen;
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sck_gen : process is
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begin
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sck <= '0';
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wait for 40 ns;
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sck <= '1';
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wait for 40 ns;
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end process sck_gen;
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send_spi : process is
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procedure send24(dat : in std_logic_vector(23 downto 0)) is
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variable data : std_logic_vector(dat'range);
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begin
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cs <= '1';
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if ready /= '1' then
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wait until ready = '1';
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end if;
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wait for 30 ns;
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data := dat;
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '0';
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mosi <= data(23);
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data := data(22 downto 0) & '0';
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wait until falling_edge(sck);
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cs <= '1';
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end send24;
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begin
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cs <= '1';
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wait for 50 ns;
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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send24(x"FF0055");
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send24(x"CCFFAA");
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wait;
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end process send_spi;
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end architecture sim;
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