97 lines
2.0 KiB
VHDL
97 lines
2.0 KiB
VHDL
-- Thanks to: http://www.deathbylogic.com/2013/07/vhdl-standard-fifo/
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library IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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entity STD_FIFO is
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Generic (
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DATA_WIDTH : positive := 8;
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FIFO_DEPTH : positive := 256
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);
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Port (
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CLK : in STD_LOGIC;
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RST : in STD_LOGIC;
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WriteEn : in STD_LOGIC;
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DataIn : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
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ReadEn : in STD_LOGIC;
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DataOut : out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
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Empty : out STD_LOGIC;
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Full : out STD_LOGIC
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);
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end STD_FIFO;
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architecture Behavioral of STD_FIFO is
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begin
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-- Memory Pointer Process
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fifo_proc : process (CLK)
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type FIFO_Memory is array (0 to FIFO_DEPTH - 1) of STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0);
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variable Memory : FIFO_Memory;
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variable Head : natural range 0 to FIFO_DEPTH - 1;
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variable Tail : natural range 0 to FIFO_DEPTH - 1;
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variable Looped : boolean;
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begin
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if rising_edge(CLK) then
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if RST = '1' then
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Head := 0;
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Tail := 0;
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Looped := false;
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Full <= '0';
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Empty <= '1';
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else
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if (ReadEn = '1') then
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if ((Looped = true) or (Head /= Tail)) then
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-- Update data output
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DataOut <= Memory(Tail);
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-- Update Tail pointer as needed
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if (Tail = FIFO_DEPTH - 1) then
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Tail := 0;
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Looped := false;
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else
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Tail := Tail + 1;
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end if;
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end if;
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end if;
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if (WriteEn = '1') then
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if ((Looped = false) or (Head /= Tail)) then
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-- Write Data to Memory
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Memory(Head) := DataIn;
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-- Increment Head pointer as needed
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if (Head = FIFO_DEPTH - 1) then
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Head := 0;
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Looped := true;
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else
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Head := Head + 1;
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end if;
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end if;
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end if;
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-- Update Empty and Full flags
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if (Head = Tail) then
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if Looped then
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Full <= '1';
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else
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Empty <= '1';
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end if;
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else
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Empty <= '0';
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Full <= '0';
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end if;
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end if;
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end if;
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end process;
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end Behavioral;
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