can: m_can: Updated register defines to newest version
* Updated register defines to newest M_CAN version (v3.2.1). * Changed defines in the whole code. Signed-off-by: Mario Huettel <mario.huettel@gmx.net>
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@ -37,17 +37,19 @@ enum m_can_reg {
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M_CAN_CREL = 0x0,
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M_CAN_ENDN = 0x4,
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M_CAN_CUST = 0x8,
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M_CAN_FBTP = 0xc,
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M_CAN_DBTP = 0xc,
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M_CAN_TEST = 0x10,
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M_CAN_RWD = 0x14,
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M_CAN_CCCR = 0x18,
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M_CAN_BTP = 0x1c,
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M_CAN_NBTP = 0x1c,
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M_CAN_TSCC = 0x20,
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M_CAN_TSCV = 0x24,
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M_CAN_TOCC = 0x28,
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M_CAN_TOCV = 0x2c,
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M_CAN_ECR = 0x40,
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M_CAN_PSR = 0x44,
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/* TDCR Register only available for version >=3.1.x */
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M_CAN_TDCR = 0x48,
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M_CAN_IR = 0x50,
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M_CAN_IE = 0x54,
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M_CAN_ILS = 0x58,
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@ -105,21 +107,21 @@ enum m_can_mram_cfg {
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MRAM_CFG_NUM,
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};
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/* Fast Bit Timing & Prescaler Register (FBTP) */
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#define FBTR_FBRP_MASK 0x1f
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#define FBTR_FBRP_SHIFT 16
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#define FBTR_FTSEG1_SHIFT 8
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#define FBTR_FTSEG1_MASK (0xf << FBTR_FTSEG1_SHIFT)
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#define FBTR_FTSEG2_SHIFT 4
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#define FBTR_FTSEG2_MASK (0x7 << FBTR_FTSEG2_SHIFT)
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#define FBTR_FSJW_SHIFT 0
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#define FBTR_FSJW_MASK 0x3
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/* Data Bit Timing & Prescaler Register (DBTP) */
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#define DBTP_TDC BIT(23)
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#define DBTP_DBRP_SHIFT 16
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#define DBTP_DBRP_MASK (0x1f << DBTP_DBRP_SHIFT)
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#define DBTP_DTSEG1_SHIFT 8
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#define DBTP_DTSEG1_MASK (0x1f << DBTP_DTSEG1_SHIFT)
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#define DBTP_DTSEG2_SHIFT 4
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#define DBTP_DTSEG2_MASK (0xf << DBTP_DTSEG2_SHIFT)
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#define DBTP_DSJW_SHIFT 0
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#define DBTP_DSJW_MASK (0xf << DBTP_DSJW_SHIFT)
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/* Test Register (TEST) */
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#define TEST_LBCK BIT(4)
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#define TEST_LBCK BIT(4)
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/* CC Control Register(CCCR) */
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#define CCCR_TEST BIT(7)
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#define CCCR_CMR_MASK 0x3
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#define CCCR_CMR_SHIFT 10
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#define CCCR_CMR_CANFD 0x1
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@ -130,21 +132,32 @@ enum m_can_mram_cfg {
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#define CCCR_CME_CAN 0
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#define CCCR_CME_CANFD 0x1
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#define CCCR_CME_CANFD_BRS 0x2
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#define CCCR_TXP BIT(14)
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#define CCCR_TEST BIT(7)
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#define CCCR_MON BIT(5)
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#define CCCR_CSR BIT(4)
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#define CCCR_CSA BIT(3)
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#define CCCR_ASM BIT(2)
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#define CCCR_CCE BIT(1)
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#define CCCR_INIT BIT(0)
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#define CCCR_CANFD 0x10
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/* for version >=3.1.x */
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#define CCCR_EFBI BIT(13)
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#define CCCR_PXHD BIT(12)
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#define CCCR_BRSE BIT(9)
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#define CCCR_FDOE BIT(8)
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/* only for version >=3.2.x */
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#define CCCR_NISO BIT(15)
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/* Bit Timing & Prescaler Register (BTP) */
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#define BTR_BRP_MASK 0x3ff
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#define BTR_BRP_SHIFT 16
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#define BTR_TSEG1_SHIFT 8
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#define BTR_TSEG1_MASK (0x3f << BTR_TSEG1_SHIFT)
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#define BTR_TSEG2_SHIFT 4
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#define BTR_TSEG2_MASK (0xf << BTR_TSEG2_SHIFT)
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#define BTR_SJW_SHIFT 0
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#define BTR_SJW_MASK 0xf
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/* Nominal Bit Timing & Prescaler Register (NBTP) */
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#define NBTP_NSJW_SHIFT 25
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#define NBTP_NSJW_MASK (0x7f << NBTP_NSJW_SHIFT)
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#define NBTP_NBRP_SHIFT 16
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#define NBTP_NBRP_MASK (0x1ff << NBTP_NBRP_SHIFT)
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#define NBTP_NTSEG1_SHIFT 8
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#define NBTP_NTSEG1_MASK (0xff << NBTP_NTSEG1_SHIFT)
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#define NBTP_NTSEG2_SHIFT 0
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#define NBTP_NTSEG2_MASK (0x7f << NBTP_NTSEG2_SHIFT)
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/* Error Counter Register(ECR) */
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#define ECR_RP BIT(15)
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@ -161,6 +174,13 @@ enum m_can_mram_cfg {
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/* Interrupt Register(IR) */
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#define IR_ALL_INT 0xffffffff
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/* Renamed bits for versions > 3.1.x */
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#define IR_ARA BIT(29)
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#define IR_PED BIT(28)
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#define IR_PEA BIT(27)
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/* Bits for version 3.0.x */
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#define IR_STE BIT(31)
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#define IR_FOE BIT(30)
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#define IR_ACKE BIT(29)
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@ -194,33 +214,40 @@ enum m_can_mram_cfg {
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#define IR_RF0W BIT(1)
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#define IR_RF0N BIT(0)
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#define IR_ERR_STATE (IR_BO | IR_EW | IR_EP)
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#define IR_ERR_LEC (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
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#define IR_ERR_BUS (IR_ERR_LEC | IR_WDI | IR_ELO | IR_BEU | \
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/* Interrupts for version 3.0.x */
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#define IR_ERR_LEC_30X (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
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#define IR_ERR_BUS_30X (IR_ERR_LEC_30X | IR_WDI | IR_ELO | IR_BEU | \
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IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
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IR_RF1L | IR_RF0L)
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#define IR_ERR_ALL (IR_ERR_STATE | IR_ERR_BUS)
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#define IR_ERR_ALL_30X (IR_ERR_STATE | IR_ERR_BUS_30X)
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/* Interrupts for version >= 3.1.x */
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#define IR_ERR_LEC_31X (IR_PED | IR_PEA)
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#define IR_ERR_BUS_31X (IR_ERR_LEC_31X | IR_WDI | IR_ELO | IR_BEU | \
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IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
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IR_RF1L | IR_RF0L)
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#define IR_ERR_ALL_31X (IR_ERR_STATE | IR_ERR_BUS_31X)
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/* Interrupt Line Select (ILS) */
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#define ILS_ALL_INT0 0x0
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#define ILS_ALL_INT1 0xFFFFFFFF
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/* Interrupt Line Enable (ILE) */
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#define ILE_EINT0 BIT(0)
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#define ILE_EINT1 BIT(1)
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#define ILE_EINT0 BIT(0)
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/* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
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#define RXFC_FWM_OFF 24
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#define RXFC_FWM_MASK 0x7f
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#define RXFC_FWM_1 (1 << RXFC_FWM_OFF)
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#define RXFC_FS_OFF 16
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#define RXFC_FS_MASK 0x7f
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#define RXFC_FWM_SHIFT 24
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#define RXFC_FWM_MASK (0x7f < RXFC_FWM_SHIFT)
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#define RXFC_FS_SHIFT 16
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#define RXFC_FS_MASK (0x7f << RXFC_FS_SHIFT)
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/* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
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#define RXFS_RFL BIT(25)
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#define RXFS_FF BIT(24)
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#define RXFS_FPI_OFF 16
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#define RXFS_FPI_SHIFT 16
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#define RXFS_FPI_MASK 0x3f0000
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#define RXFS_FGI_OFF 8
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#define RXFS_FGI_SHIFT 8
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#define RXFS_FGI_MASK 0x3f00
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#define RXFS_FFL_MASK 0x7f
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@ -229,23 +256,46 @@ enum m_can_mram_cfg {
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#define M_CAN_RXESC_64BYTES 0x777
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/* Tx Buffer Configuration(TXBC) */
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#define TXBC_NDTB_OFF 16
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#define TXBC_NDTB_MASK 0x3f
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#define TXBC_NDTB_SHIFT 16
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#define TXBC_NDTB_MASK (0x3f << TXBC_NDTB_SHIFT)
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#define TXBC_TFQS_SHIFT 24
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#define TXBC_TFQS_MASK (0x3f << TXBC_TFQS_SHIFT)
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/* Tx FIFO/Queue Status (TXFQS) */
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#define TXFQS_TFQF BIT(21)
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#define TXFQS_TFQPI_SHIFT 16
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#define TXFQS_TFQPI_MASK (0x1f << TXFQS_TFQPI_SHIFT)
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#define TXFQS_TFGI_SHIFT 8
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#define TXFQS_TFGI_MASK (0x1f << TXFQS_TFGI_SHIFT)
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#define TXFQS_TFFL_SHIFT 0
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#define TXFQS_TFFL_MASK (0x3f << TXFQS_TFFL_SHIFT)
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/* Tx Buffer Element Size Configuration(TXESC) */
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#define TXESC_TBDS_8BYTES 0x0
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#define TXESC_TBDS_64BYTES 0x7
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/* Tx Event FIFO Con.guration (TXEFC) */
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#define TXEFC_EFS_OFF 16
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#define TXEFC_EFS_MASK 0x3f
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/* Tx Event FIFO Configuration (TXEFC) */
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#define TXEFC_EFS_SHIFT 16
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#define TXEFC_EFS_MASK (0x3f << TXEFC_EFS_SHIFT)
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/* Tx Event FIFO Status (TXEFS) */
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#define TXEFS_TEFL BIT(25)
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#define TXEFS_EFF BIT(24)
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#define TXEFS_EFGI_SHIFT 8
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#define TXEFS_EFGI_MASK (0x1f << TXEFS_EFGI_SHIFT)
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#define TXEFS_EFFL_SHIFT 0
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#define TXEFS_EFFL_MASK (0x3f << TXEFS_EFFL_SHIFT)
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/* Tx Event FIFO Acknowledge (TXEFA) */
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#define TXEFA_EFAI_SHIFT 0
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#define TXEFA_EFAI_MASK (0x1f << TXEFA_EFAI_SHIFT)
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/* Message RAM Configuration (in bytes) */
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#define SIDF_ELEMENT_SIZE 4
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#define XIDF_ELEMENT_SIZE 8
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#define RXF0_ELEMENT_SIZE 72
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#define RXF1_ELEMENT_SIZE 72
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#define RXB_ELEMENT_SIZE 16
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#define RXB_ELEMENT_SIZE 72
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#define TXE_ELEMENT_SIZE 8
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#define TXB_ELEMENT_SIZE 72
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@ -261,13 +311,20 @@ enum m_can_mram_cfg {
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#define RX_BUF_RTR BIT(29)
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/* R1 */
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#define RX_BUF_ANMF BIT(31)
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#define RX_BUF_EDL BIT(21)
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#define RX_BUF_FDF BIT(21)
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#define RX_BUF_BRS BIT(20)
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/* Tx Buffer Element */
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/* R0 */
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/* T0 */
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#define TX_BUF_ESI BIT(31)
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#define TX_BUF_XTD BIT(30)
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#define TX_BUF_RTR BIT(29)
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/* T1 */
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#define TX_BUF_EFC BIT(23)
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#define TX_BUF_FDF BIT(21)
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#define TX_BUF_BRS BIT(20)
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#define TX_BUF_MM_SHIFT 24
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#define TX_BUF_MM_MASK (0xff << TX_BUF_MM_SHIFT)
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/* address offset and element number for each FIFO/Buffer in the Message RAM */
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struct mram_cfg {
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@ -368,9 +425,9 @@ static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
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int i;
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/* calculate the fifo get index for where to read data */
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fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_OFF;
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fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_SHIFT;
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dlc = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC);
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if (dlc & RX_BUF_EDL)
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if (dlc & RX_BUF_FDF)
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skb = alloc_canfd_skb(dev, &cf);
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else
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skb = alloc_can_skb(dev, (struct can_frame **)&cf);
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@ -379,7 +436,7 @@ static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
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return;
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}
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if (dlc & RX_BUF_EDL)
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if (dlc & RX_BUF_FDF)
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cf->len = can_dlc2len((dlc >> 16) & 0x0F);
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else
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cf->len = get_can_dlc((dlc >> 16) & 0x0F);
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@ -395,7 +452,7 @@ static void m_can_read_fifo(struct net_device *dev, u32 rxfs)
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netdev_dbg(dev, "ESI Error\n");
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}
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if (!(dlc & RX_BUF_EDL) && (id & RX_BUF_RTR)) {
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if (!(dlc & RX_BUF_FDF) && (id & RX_BUF_RTR)) {
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cf->can_id |= CAN_RTR_FLAG;
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} else {
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if (dlc & RX_BUF_BRS)
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@ -533,7 +590,7 @@ static int __m_can_get_berr_counter(const struct net_device *dev,
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ecr = m_can_read(priv, M_CAN_ECR);
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bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
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bec->txerr = ecr & ECR_TEC_MASK;
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bec->txerr = (ecr & ECR_TEC_MASK) >> ECR_TEC_SHIFT;
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return 0;
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}
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@ -724,7 +781,7 @@ static int m_can_poll(struct napi_struct *napi, int quota)
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if (irqstatus & IR_ERR_STATE)
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work_done += m_can_handle_state_errors(dev, psr);
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if (irqstatus & IR_ERR_BUS)
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if (irqstatus & IR_ERR_BUS_30X)
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work_done += m_can_handle_bus_errors(dev, irqstatus, psr);
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if (irqstatus & IR_RF0N)
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@ -759,7 +816,7 @@ static irqreturn_t m_can_isr(int irq, void *dev_id)
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* - state change IRQ
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* - bus error IRQ and bus error reporting
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*/
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if ((ir & IR_RF0N) || (ir & IR_ERR_ALL)) {
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if ((ir & IR_RF0N) || (ir & IR_ERR_ALL_30X)) {
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priv->irqstatus = ir;
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m_can_disable_all_interrupts(priv);
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napi_schedule(&priv->napi);
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@ -812,19 +869,19 @@ static int m_can_set_bittiming(struct net_device *dev)
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sjw = bt->sjw - 1;
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tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
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tseg2 = bt->phase_seg2 - 1;
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reg_btp = (brp << BTR_BRP_SHIFT) | (sjw << BTR_SJW_SHIFT) |
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(tseg1 << BTR_TSEG1_SHIFT) | (tseg2 << BTR_TSEG2_SHIFT);
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m_can_write(priv, M_CAN_BTP, reg_btp);
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reg_btp = (brp << NBTP_NBRP_SHIFT) | (sjw << NBTP_NSJW_SHIFT) |
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(tseg1 << NBTP_NTSEG1_SHIFT) | (tseg2 << NBTP_NTSEG2_SHIFT);
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m_can_write(priv, M_CAN_NBTP, reg_btp);
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if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
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brp = dbt->brp - 1;
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sjw = dbt->sjw - 1;
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tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
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tseg2 = dbt->phase_seg2 - 1;
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reg_btp = (brp << FBTR_FBRP_SHIFT) | (sjw << FBTR_FSJW_SHIFT) |
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(tseg1 << FBTR_FTSEG1_SHIFT) |
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(tseg2 << FBTR_FTSEG2_SHIFT);
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m_can_write(priv, M_CAN_FBTP, reg_btp);
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reg_btp = (brp << DBTP_DBRP_SHIFT) | (sjw << DBTP_DSJW_SHIFT) |
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(tseg1 << DBTP_DTSEG1_SHIFT) |
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(tseg2 << DBTP_DTSEG2_SHIFT);
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m_can_write(priv, M_CAN_DBTP, reg_btp);
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}
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return 0;
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@ -852,22 +909,22 @@ static void m_can_chip_config(struct net_device *dev)
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m_can_write(priv, M_CAN_GFC, 0x0);
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/* only support one Tx Buffer currently */
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m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_OFF) |
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m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_SHIFT) |
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priv->mcfg[MRAM_TXB].off);
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/* support 64 bytes payload */
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m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_64BYTES);
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m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_OFF) |
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m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_SHIFT) |
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priv->mcfg[MRAM_TXE].off);
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/* rx fifo configuration, blocking mode, fifo size 1 */
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m_can_write(priv, M_CAN_RXF0C,
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(priv->mcfg[MRAM_RXF0].num << RXFC_FS_OFF) |
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(priv->mcfg[MRAM_RXF0].num << RXFC_FS_SHIFT) |
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priv->mcfg[MRAM_RXF0].off);
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m_can_write(priv, M_CAN_RXF1C,
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(priv->mcfg[MRAM_RXF1].num << RXFC_FS_OFF) |
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(priv->mcfg[MRAM_RXF1].num << RXFC_FS_SHIFT) |
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priv->mcfg[MRAM_RXF1].off);
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cccr = m_can_read(priv, M_CAN_CCCR);
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@ -893,7 +950,7 @@ static void m_can_chip_config(struct net_device *dev)
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/* enable interrupts */
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m_can_write(priv, M_CAN_IR, IR_ALL_INT);
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if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
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m_can_write(priv, M_CAN_IE, IR_ALL_INT & ~IR_ERR_LEC);
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m_can_write(priv, M_CAN_IE, IR_ALL_INT & ~IR_ERR_LEC_30X);
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else
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||||
m_can_write(priv, M_CAN_IE, IR_ALL_INT);
|
||||
|
||||
|
|
@ -1144,10 +1201,12 @@ static int m_can_of_parse_mram(struct platform_device *pdev,
|
|||
priv->mcfg[MRAM_XIDF].num = out_val[2];
|
||||
priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off +
|
||||
priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
|
||||
priv->mcfg[MRAM_RXF0].num = out_val[3] & RXFC_FS_MASK;
|
||||
priv->mcfg[MRAM_RXF0].num = out_val[3] &
|
||||
(RXFC_FS_MASK >> RXFC_FS_SHIFT);
|
||||
priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off +
|
||||
priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
|
||||
priv->mcfg[MRAM_RXF1].num = out_val[4] & RXFC_FS_MASK;
|
||||
priv->mcfg[MRAM_RXF1].num = out_val[4] &
|
||||
(RXFC_FS_MASK >> RXFC_FS_SHIFT);
|
||||
priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off +
|
||||
priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
|
||||
priv->mcfg[MRAM_RXB].num = out_val[5];
|
||||
|
|
@ -1156,7 +1215,8 @@ static int m_can_of_parse_mram(struct platform_device *pdev,
|
|||
priv->mcfg[MRAM_TXE].num = out_val[6];
|
||||
priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off +
|
||||
priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
|
||||
priv->mcfg[MRAM_TXB].num = out_val[7] & TXBC_NDTB_MASK;
|
||||
priv->mcfg[MRAM_TXB].num = out_val[7] &
|
||||
(TXBC_NDTB_MASK >> TXBC_NDTB_SHIFT);
|
||||
|
||||
dev_dbg(&pdev->dev, "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
|
||||
priv->mram_base,
|
||||
|
|
@ -1192,7 +1252,7 @@ static int m_can_plat_probe(struct platform_device *pdev)
|
|||
hclk = devm_clk_get(&pdev->dev, "hclk");
|
||||
cclk = devm_clk_get(&pdev->dev, "cclk");
|
||||
if (IS_ERR(hclk) || IS_ERR(cclk)) {
|
||||
dev_err(&pdev->dev, "no clock find\n");
|
||||
dev_err(&pdev->dev, "no clock found\n");
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue