Implement test RX for DMX. Still no functionality
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@ -1,21 +1,34 @@
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#include <ring-light/dmx.h>
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#include <stm32f0xx.h>
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static volatile bool dmx_new_data_avail = false;
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static uint32_t dmx_base_channel;
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static uint8_t dmx_channel_data[DMX_USED_CHANNEL_COUNT];
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enum dmx_rx_state_enum {
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DMX_RX_WAIT_FOR_BREAK = 0,
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DMX_RX_DATA,
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};
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/**
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* @brief DMX data received. Contains the whole DMX universe including the first 0 byte.
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* The controller does check the first byte to be zero.
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*/
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static volatile uint8_t dmx_channel_data[DMX_UNIVERSE_SIZE + 1];
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static volatile enum dmx_rx_state_enum dmx_rx_state;
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static volatile uint32_t dmx_write_pointer;
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void dmx_init(uint32_t base_channel)
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{
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int i;
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uint8_t *ptr;
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volatile uint8_t *ptr;
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dmx_new_data_avail = false;
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for (i = 0, ptr = dmx_channel_data; i < DMX_USED_CHANNEL_COUNT; i++, ptr++) {
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*ptr = 0u;
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}
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dmx_base_channel = base_channel;
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dmx_write_pointer = 0u;
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dmx_rx_state = DMX_RX_WAIT_FOR_BREAK;
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/* Enable GPIOA and USART1 clock */
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RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
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@ -35,31 +48,52 @@ void dmx_init(uint32_t base_channel)
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USART1->CR2 = USART_CR2_STOP_1;
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USART1->CR1 = USART_CR1_RXNEIE | USART_CR1_RE | USART_CR1_UE;
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/* Map USART1 RX to DMA Channel 3 */
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SYSCFG->CFGR1 &= ~SYSCFG_CFGR1_USART1RX_DMA_RMP;
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NVIC_EnableIRQ(USART1_IRQn);
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}
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bool dmx_new_data_available()
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{
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return dmx_new_data_avail;
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}
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const uint8_t *dmx_get_data()
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{
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return dmx_channel_data;
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return (const uint8_t *)&dmx_channel_data[1];
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}
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void USART1_IRQHandler(void)
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{
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uint32_t isr;
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volatile uint8_t dreg;
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uint8_t dreg;
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isr = USART1->ISR;
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USART1->ICR = USART_ICR_ORECF | USART_ICR_NCF | USART_ICR_FECF;
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if (isr & USART_ISR_RXNE) {
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if (isr & USART_ISR_FE) {
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/* Frame error received. Start of DMX frame */
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dmx_write_pointer = 0u;
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dmx_rx_state = DMX_RX_DATA;
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/* Flush RX data */
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USART1->RQR = USART_RQR_RXFRQ;
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} else if (isr & USART_ISR_RXNE) {
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/* Received valid symbol */
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dreg = (uint8_t)USART1->RDR;
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dmx_channel_data[0] = dreg;
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if (dmx_rx_state == DMX_RX_DATA) {
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/* Ready to recieve data */
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if (dmx_write_pointer < (DMX_UNIVERSE_SIZE + 1)) {
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dmx_channel_data[dmx_write_pointer] = dreg;
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dmx_write_pointer++;
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} else {
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dmx_rx_state = DMX_RX_WAIT_FOR_BREAK;
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}
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}
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}
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__DSB();
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}
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void DMA_CH2_3_DMA2_CH1_2_IRQHandler()
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{
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}
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@ -28,12 +28,6 @@
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*/
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void dmx_init(uint32_t base_channel);
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/**
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* @brief Has new DMX data been received?
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* @return true if new data is available
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*/
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bool dmx_new_data_available(void);
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/**
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* @brief Returns the array of the 129 DMX channels
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* @return
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@ -96,7 +96,7 @@ void DMA_CH1_IRQHandler(void)
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uint32_t isr;
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isr = DMA1->ISR;
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DMA1->IFCR = isr;
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DMA1->IFCR = isr & 0xF;
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if (isr & DMA_ISR_TCIF1) {
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process_adc_samples();
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