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Issue #9: Increase SDIO clock speed to 4.2 MHz

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Mario Hüttel
2020-08-18 19:30:51 +02:00
parent 637ac77a09
commit 64ef7b4a3c
1 changed files with 2 additions and 2 deletions
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4
stm-firmware/fatfs/shimatta_sdio_driver/shimatta_sdio_config.h
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@@ -14,9 +14,9 @@
//Initial Transfer CLK (ca. 400kHz) //Initial Transfer CLK (ca. 400kHz)
#define INITCLK 140 //120 #define INITCLK 140 //120
//Working CLK (Maximum) //Working CLK (Maximum)
#define WORKCLK 50 //0 #define WORKCLK 8 //0
//Data Timeout in CLK Cycles //Data Timeout in CLK Cycles
#define DTIMEOUT 0x3000 //150 #define DTIMEOUT 0x6000 //150
//DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible //DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible
// Currently not used due to possible misalignment of the data buffer. // Currently not used due to possible misalignment of the data buffer.
//#define DMASTREAM DMA2_Stream6 //#define DMASTREAM DMA2_Stream6