Issue #9: Increase SDIO clock speed to 4.2 MHz

stm-firmware/fatfs/shimatta_sdio_driver/shimatta_sdio_config.h

@@ -14,9 +14,9 @@
 //Initial Transfer CLK (ca. 400kHz)
 #define INITCLK   140   //120
 //Working CLK (Maximum)
-#define WORKCLK   50   //0
+#define WORKCLK   8   //0
 //Data Timeout in CLK Cycles
-#define DTIMEOUT  0x3000   //150
+#define DTIMEOUT  0x6000   //150
 //DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible
 // Currently not used due to possible misalignment of the data buffer.
 //#define DMASTREAM DMA2_Stream6