Add generic function to detzermine reset cuase to rcc manager
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@ -40,11 +40,4 @@ int watchdog_setup(uint8_t prescaler);
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*/
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*/
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int watchdog_ack(uint32_t magic);
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int watchdog_ack(uint32_t magic);
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/**
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* @brief Check if reset was generated by the watchdog.
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* @note This also clears the relevant flag, so the function will return false when called a second time
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* @return true, if reset was generated by the watchdog
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*/
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bool watchdog_check_reset_source(void);
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#endif /* __WATCHDOG_H__ */
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#endif /* __WATCHDOG_H__ */
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@ -23,6 +23,7 @@
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#include <stdint.h>
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#include <stdint.h>
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#include <stm-periph/stm32-gpio-macros.h>
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#include <stm-periph/stm32-gpio-macros.h>
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#include <stdbool.h>
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/**
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/**
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* @brief The RCC Enable Manager uses static memory with a fixed maximum
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* @brief The RCC Enable Manager uses static memory with a fixed maximum
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@ -35,6 +36,19 @@
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#error "RCC Enable Manager not yet implemented with dynamic memory"
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#error "RCC Enable Manager not yet implemented with dynamic memory"
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#endif
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#endif
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/**
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* @brief The source/cause of a system reset. The values can be or'ed together as multiple flags may be possible at the same time.
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*/
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enum rcc_reset_source {
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RCC_RESET_SOURCE_LOW_POWER = (1<<0), /**< @brief System reset caused by low power reset */
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RCC_RESET_SOURCE_SOFTWARE = (1<<1), /**< @brief System reset caused by software */
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RCC_RESET_SOURCE_WWD = (1<<2), /**< @brief System reset caused by window watchdog */
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RCC_RESET_SOURCE_IWDG = (1<<3), /**< @brief System reset caused by independent watchdog */
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RCC_RESET_SOURCE_POWER_ON = (1<<4), /**< @brief System reset caused by power on reset (POR) */
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RCC_RESET_SOURCE_PIN = (1<<5), /**< @brief System reset caused by NRST pin */
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RCC_RESET_BOR_POR = (1<<6), /**< @brief System reset caused by eitehr brown out or POR */
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};
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/**
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/**
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* @brief Enable Clock for peripheral by setting the corresponding bit (@p bit_no) to one
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* @brief Enable Clock for peripheral by setting the corresponding bit (@p bit_no) to one
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*
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*
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@ -64,4 +78,11 @@ int rcc_manager_enable_clock(volatile uint32_t *rcc_enable_register, uint8_t bit
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*/
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*/
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int rcc_manager_disable_clock(volatile uint32_t *rcc_enable_register, uint8_t bit_no);
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int rcc_manager_disable_clock(volatile uint32_t *rcc_enable_register, uint8_t bit_no);
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/**
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* @brief Get the causes of the last system reset.
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* @param clear_flags Clear the reset cause
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* @return Reset cause
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*/
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enum rcc_reset_source rcc_manager_get_reset_cause(bool clear_flags);
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#endif /* __RCC_MANAGER_H__ */
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#endif /* __RCC_MANAGER_H__ */
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@ -39,6 +39,7 @@
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#include <reflow-controller/safety/safety-memory.h>
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#include <reflow-controller/safety/safety-memory.h>
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#include <reflow-controller/oven-driver.h>
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#include <reflow-controller/oven-driver.h>
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#include <helper-macros/helper-macros.h>
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#include <helper-macros/helper-macros.h>
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#include <stm-periph/rcc-manager.h>
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#define check_flag_persistent(flag) ((flag)->persistency && (flag)->persistency->persistency)
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#define check_flag_persistent(flag) ((flag)->persistency && (flag)->persistency->persistency)
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#define get_flag_weight(flag) ((flag)->weight ? (flag->weight->weight) : SAFETY_FLAG_CONFIG_WEIGHT_NONE)
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#define get_flag_weight(flag) ((flag)->weight ? (flag->weight->weight) : SAFETY_FLAG_CONFIG_WEIGHT_NONE)
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@ -513,7 +514,7 @@ void safety_controller_init()
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safety_adc_init();
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safety_adc_init();
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watchdog_setup(WATCHDOG_PRESCALER);
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watchdog_setup(WATCHDOG_PRESCALER);
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if (watchdog_check_reset_source())
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if (rcc_manager_get_reset_cause(false) & RCC_RESET_SOURCE_IWDG)
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safety_controller_report_error(ERR_FLAG_WTCHDG_FIRED);
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safety_controller_report_error(ERR_FLAG_WTCHDG_FIRED);
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#ifdef DEBUGBUILD
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#ifdef DEBUGBUILD
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@ -105,16 +105,4 @@ int watchdog_ack(uint32_t magic)
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return ret;
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return ret;
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}
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}
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bool watchdog_check_reset_source(void)
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{
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bool ret;
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ret = !!(RCC->CSR & RCC_CSR_WDGRSTF);
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if (ret)
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RCC->CSR |= RCC_CSR_RMVF;
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return ret;
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}
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/** @} */
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/** @} */
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@ -21,6 +21,7 @@
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#include <stm-periph/rcc-manager.h>
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#include <stm-periph/rcc-manager.h>
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#include <helper-macros/helper-macros.h>
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#include <helper-macros/helper-macros.h>
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#include <stdlib.h>
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#include <stdlib.h>
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#include <stm32/stm32f4xx.h>
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struct rcc_enable_count {
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struct rcc_enable_count {
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volatile uint32_t *rcc_reg_addr;
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volatile uint32_t *rcc_reg_addr;
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@ -153,3 +154,30 @@ int rcc_manager_disable_clock(volatile uint32_t *rcc_enable_register, uint8_t bi
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return ret_val;
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return ret_val;
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}
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}
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enum rcc_reset_source rcc_manager_get_reset_cause(bool clear_flags)
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{
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enum rcc_reset_source ret = 0;
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uint32_t rcc_csr;
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rcc_csr = RCC->CSR;
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if (rcc_csr & RCC_CSR_LPWRRSTF)
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ret |= RCC_RESET_SOURCE_LOW_POWER;
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if (rcc_csr & RCC_CSR_WWDGRSTF)
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ret |= RCC_RESET_SOURCE_WWD;
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if (rcc_csr & RCC_CSR_WDGRSTF)
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ret |= RCC_RESET_SOURCE_IWDG;
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if (rcc_csr & RCC_CSR_SFTRSTF)
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ret |= RCC_RESET_SOURCE_SOFTWARE;
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if (rcc_csr & RCC_CSR_PORRSTF)
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ret |= RCC_RESET_SOURCE_POWER_ON;
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if (rcc_csr & RCC_CSR_PADRSTF)
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ret |= RCC_RESET_SOURCE_PIN;
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if (rcc_csr & RCC_CSR_BORRSTF)
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ret |= RCC_RESET_BOR_POR;
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if (clear_flags)
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RCC->CSR |= RCC_CSR_RMVF;
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return ret;
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}
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