improve SDIO driver
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09ea84beaf
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e37001e3c4
@ -185,12 +185,13 @@ static int sdio_send_csd_cmd9(uint16_t rca, uint32_t *response_buffer) {
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* @param blklen Log2 of block length (9 in case of 512 byte block)
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* @param blklen Log2 of block length (9 in case of 512 byte block)
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* @param buff Buffer to send
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* @param buff Buffer to send
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*/
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*/
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static void sdio_write_buffer(uint32_t dlen, uint32_t log_blklen, const unsigned char *buff)
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static int sdio_write_buffer(uint32_t dlen, uint32_t log_blklen, const unsigned char *buff)
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{
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{
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uint32_t count;
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uint32_t count;
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int byte_count;
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int byte_count;
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int byte_max;
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int byte_max;
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uint32_t fifo;
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uint32_t fifo;
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uint32_t status_reg;
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SDIO->DLEN = dlen;
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SDIO->DLEN = dlen;
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@ -213,6 +214,8 @@ static void sdio_write_buffer(uint32_t dlen, uint32_t log_blklen, const unsigned
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fifo |= (((uint32_t)*(buff++)) << 24) & 0xFF000000;
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fifo |= (((uint32_t)*(buff++)) << 24) & 0xFF000000;
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}
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}
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/* Wait as long as FIFO is full */
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/* Wait as long as FIFO is full */
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while (SDIO->STA & SDIO_STA_TXFIFOF);
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while (SDIO->STA & SDIO_STA_TXFIFOF);
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@ -222,6 +225,14 @@ static void sdio_write_buffer(uint32_t dlen, uint32_t log_blklen, const unsigned
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/* Wait for TX to complete */
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/* Wait for TX to complete */
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while (SDIO->STA & SDIO_STA_TXACT);
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while (SDIO->STA & SDIO_STA_TXACT);
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status_reg = SDIO->STA;
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if (status_reg & (SDIO_STA_DTIMEOUT | SDIO_STA_TXUNDERR | SDIO_STA_DCRCFAIL)) {
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SDIO->DCTRL = 0UL;
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return -1;
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}
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return 0;
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}
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}
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static int sdio_send_write_block_cmd24(uint32_t addr)
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static int sdio_send_write_block_cmd24(uint32_t addr)
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@ -779,17 +790,11 @@ DRESULT sdio_disk_write(const BYTE *buff, DWORD sector, UINT count)
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if (ret)
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if (ret)
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return RES_ERROR;
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return RES_ERROR;
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while (count) {
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ret = 0;
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ret = sdio_write_buffer((count * 512UL), 9, &buff[buff_offset]);
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sdio_write_buffer(512, 9, &buff[buff_offset]);
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buff_offset += 512;
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addr += (card_info.type == SD_V2_HC ? 1 : 512);
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count--;
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}
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if (count_backup > 1)
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if (count_backup > 1)
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(void)sdio_send_stop_transmission_cmd12();
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(void)sdio_send_stop_transmission_cmd12();
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return RES_OK;
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return (ret ? RES_ERROR : RES_OK);
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}
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}
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@ -3,6 +3,8 @@
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#include <stm32/stm32f4xx.h>
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#include <stm32/stm32f4xx.h>
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#define SDIO_CLOCK_FREQ 42000000UL
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//General Definitions
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//General Definitions
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//Blocksize: 512 = 2^9 => 9
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//Blocksize: 512 = 2^9 => 9
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#define BLOCKSIZE 9 //9
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#define BLOCKSIZE 9 //9
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@ -12,11 +14,14 @@
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//4 bit: 4
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//4 bit: 4
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#define BUSWIDTH 4 //4
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#define BUSWIDTH 4 //4
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//Initial Transfer CLK (ca. 400kHz)
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//Initial Transfer CLK (ca. 400kHz)
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#define INITCLK 140 //120
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#define INITCLK 140UL //120
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//Working CLK (Maximum)
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//Working CLK (Maximum)
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#define WORKCLK 8 //0
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#define WORKCLK 30UL //0
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//Data Timeout in CLK Cycles
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//Data Timeout in CLK Cycles
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#define DTIMEOUT 0x6000 //150
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#define DATA_TIMEOUT_MS 250UL // 250
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#define DTIMEOUT (((SDIO_CLOCK_FREQ / (WORKCLK+2))) * DATA_TIMEOUT_MS / 1000UL)
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//DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible
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//DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible
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// Currently not used due to possible misalignment of the data buffer.
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// Currently not used due to possible misalignment of the data buffer.
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//#define DMASTREAM DMA2_Stream6
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//#define DMASTREAM DMA2_Stream6
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