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improve SDIO driver

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This commit is contained in:
Mario Hüttel 2020-11-02 18:19:42 +01:00
parent 09ea84beaf
commit e37001e3c4
2 changed files with 23 additions and 13 deletions
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25
stm-firmware/fatfs/shimatta_sdio_driver/shimatta_sdio.c
View File

@ -185,12 +185,13 @@ static int sdio_send_csd_cmd9(uint16_t rca, uint32_t *response_buffer) {
* @param blklen Log2 of block length (9 in case of 512 byte block)
* @param buff Buffer to send
*/
static void sdio_write_buffer(uint32_t dlen, uint32_t log_blklen, const unsigned char *buff)
static int sdio_write_buffer(uint32_t dlen, uint32_t log_blklen, const unsigned char *buff)
{
uint32_t count;
int byte_count;
int byte_max;
uint32_t fifo;
uint32_t status_reg;
SDIO->DLEN = dlen;
@ -213,6 +214,8 @@ static void sdio_write_buffer(uint32_t dlen, uint32_t log_blklen, const unsigned
fifo |= (((uint32_t)*(buff++)) << 24) & 0xFF000000;
}
/* Wait as long as FIFO is full */
while (SDIO->STA & SDIO_STA_TXFIFOF);
@ -222,6 +225,14 @@ static void sdio_write_buffer(uint32_t dlen, uint32_t log_blklen, const unsigned
/* Wait for TX to complete */
while (SDIO->STA & SDIO_STA_TXACT);
status_reg = SDIO->STA;
if (status_reg & (SDIO_STA_DTIMEOUT | SDIO_STA_TXUNDERR | SDIO_STA_DCRCFAIL)) {
SDIO->DCTRL = 0UL;
return -1;
}
return 0;
}
static int sdio_send_write_block_cmd24(uint32_t addr)
@ -779,17 +790,11 @@ DRESULT sdio_disk_write(const BYTE *buff, DWORD sector, UINT count)
if (ret)
return RES_ERROR;
while (count) {
sdio_write_buffer(512, 9, &buff[buff_offset]);
buff_offset += 512;
addr += (card_info.type == SD_V2_HC ? 1 : 512);
count--;
}
ret = 0;
ret = sdio_write_buffer((count * 512UL), 9, &buff[buff_offset]);
if (count_backup > 1)
(void)sdio_send_stop_transmission_cmd12();
return RES_OK;
return (ret ? RES_ERROR : RES_OK);
}

11
stm-firmware/fatfs/shimatta_sdio_driver/shimatta_sdio_config.h
View File

@ -3,6 +3,8 @@
#include <stm32/stm32f4xx.h>
#define SDIO_CLOCK_FREQ 42000000UL
//General Definitions
//Blocksize: 512 = 2^9 => 9
#define BLOCKSIZE 9 //9
@ -12,11 +14,14 @@
//4 bit: 4
#define BUSWIDTH 4 //4
//Initial Transfer CLK (ca. 400kHz)
#define INITCLK 140 //120
#define INITCLK 140UL //120
//Working CLK (Maximum)
#define WORKCLK 8 //0
#define WORKCLK 30UL //0
//Data Timeout in CLK Cycles
#define DTIMEOUT 0x6000 //150
#define DATA_TIMEOUT_MS 250UL // 250
#define DTIMEOUT (((SDIO_CLOCK_FREQ / (WORKCLK+2))) * DATA_TIMEOUT_MS / 1000UL)
//DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible
// Currently not used due to possible misalignment of the data buffer.
//#define DMASTREAM DMA2_Stream6