Mario Hüttel
8bbc2e60f8
* Shellmatta implemented using UART * Version string implemented * Increased heap size * Add shellmatta printf support
94 lines
2.2 KiB
C
94 lines
2.2 KiB
C
#include <uart/dma-ring-buffer.h>
|
|
#include <clock-enable-manager.h>
|
|
|
|
int dma_ring_buffer_initialize(struct dma_ring_buffer *dma_buffer, uint8_t base_dma_id, DMA_Stream_TypeDef *dma_stream, size_t buffer_element_count, char *data_buffer, void* src_reg, uint8_t dma_trigger_channel)
|
|
{
|
|
if (!dma_buffer || !dma_stream || !data_buffer || !src_reg)
|
|
return -1;
|
|
|
|
if (dma_trigger_channel > 7)
|
|
return -3;
|
|
|
|
dma_buffer->base_dma_id = base_dma_id;
|
|
|
|
switch (base_dma_id) {
|
|
case 1:
|
|
rcc_manager_enable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(RCC_AHB1ENR_DMA1EN));
|
|
break;
|
|
case 2:
|
|
rcc_manager_enable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(RCC_AHB1ENR_DMA2EN));
|
|
break;
|
|
default:
|
|
return -2;
|
|
break;
|
|
}
|
|
|
|
dma_buffer->dma = dma_stream;
|
|
dma_buffer->get_idx = 0;
|
|
dma_buffer->buffer_count = buffer_element_count;
|
|
|
|
dma_buffer->data_ptr = data_buffer;
|
|
|
|
dma_stream->PAR = (uint32_t)src_reg;
|
|
dma_stream->M0AR = (uint32_t)data_buffer;
|
|
dma_stream->NDTR = buffer_element_count;
|
|
dma_stream->NDTR = buffer_element_count;
|
|
|
|
dma_stream->CR |= (dma_trigger_channel<<25) | DMA_SxCR_MINC | DMA_SxCR_CIRC | DMA_SxCR_EN;
|
|
|
|
return 0;
|
|
}
|
|
|
|
int dma_ring_buffer_get_data(struct dma_ring_buffer *buff, const char **data_buff, size_t *len)
|
|
{
|
|
int ret_code = 0;
|
|
uint32_t ndtr;
|
|
size_t put_idx;
|
|
|
|
if (!buff || !data_buff || !len)
|
|
return -1;
|
|
|
|
|
|
ndtr = buff->dma->NDTR;
|
|
put_idx = buff->buffer_count - ndtr;
|
|
|
|
/* Check if wrap around */
|
|
if (put_idx < buff->get_idx) {
|
|
*data_buff = &(buff->data_ptr[buff->get_idx]);
|
|
*len = buff->buffer_count - buff->get_idx;
|
|
buff->get_idx = 0;
|
|
ret_code = 1;
|
|
} else if (put_idx > buff->get_idx) {
|
|
*data_buff = &(buff->data_ptr[buff->get_idx]);
|
|
*len = put_idx - buff->get_idx;
|
|
buff->get_idx += *len;
|
|
} else {
|
|
/* No new data */
|
|
*len = 0;
|
|
}
|
|
|
|
return ret_code;
|
|
}
|
|
|
|
void dma_ring_buffer_stop(struct dma_ring_buffer *buff)
|
|
{
|
|
if (!buff || !buff->dma)
|
|
return;
|
|
|
|
buff->dma->CR = 0;
|
|
buff->dma->NDTR = 0;
|
|
buff->dma->M1AR = 0;
|
|
buff->dma->FCR = 0;
|
|
|
|
switch (buff->base_dma_id) {
|
|
case 1:
|
|
rcc_manager_disable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(RCC_AHB1ENR_DMA1EN));
|
|
break;
|
|
case 2:
|
|
rcc_manager_disable_clock(&RCC->AHB1ENR, BITMASK_TO_BITNO(RCC_AHB1ENR_DMA2EN));
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|