mhu/stm32f4-sdio
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STM32F407VE adaptations, tried to find initialization bug

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This commit is contained in:
Mario Hüttel
2017-04-15 19:50:17 +02:00
parent 6d5b9578b9
commit 79d476e1eb
8 changed files with 113 additions and 56 deletions
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76
fatfs/shimatta_sdio_driver/shimatta_sdio.c
View File

@@ -8,6 +8,8 @@
#include "shimatta_sdio.h"
#include "shimatta_sdio_config.h"
#include <cmsis/core_cm4.h>
#include <stm32f4xx.h>
extern void SDIO_wait_ms(unsigned int i);
#define SETAF(PORT,PIN,AF) PORT->AFR[(PIN < 8 ? 0 : 1)] |= AF << ((PIN < 8 ? PIN : (PIN - 8)) * 4)
@@ -74,6 +76,7 @@ DSTATUS SDIO_status(){
}
uint32_t debug;
uint32_t debug_timeout;
int debug_acmd = 0;
DSTATUS SDIO_initialize(){
int timeout = 0x3000;
int i;
@@ -85,6 +88,7 @@ DSTATUS SDIO_initialize(){
card_type_t detected_card = CARD_NONE;
SDIO_init_hw();
SDIO_wait_ms(2);
SDIO_init_detect_pins();
if (checkNotInserted()) {
return STA_NOINIT | STA_NODISK;
@@ -92,6 +96,7 @@ DSTATUS SDIO_initialize(){
debug=0;
SDIO_send_go_idle_CMD0();
SDIO_wait_ms(2);
res8 = SDIO_send_iface_condition_CMD8();
switch (res8) {
case CMD8_VOLTAGE_ACCEPTED: // SDV2 Card
@@ -112,7 +117,9 @@ DSTATUS SDIO_initialize(){
do {
resa41 = SDIO_init_card_ACMD41(hcs_flag);
} while((resa41 == ACMD41_RESP_INIT) && (--timeout > 0));
debug++;
debug_acmd = resa41;
debug_timeout= timeout;
switch (resa41) {
case ACMD41_RESP_SDSC:
@@ -153,7 +160,7 @@ DSTATUS SDIO_initialize(){
}
uint32_t debug_addr, debug_count;
uint32_t __attribute__ ((aligned (16))) buffer_sdio[512/4];
//uint32_t __attribute__ ((aligned (16))) buffer_sdio[512/4];
DRESULT SDIO_disk_read(BYTE *buff, DWORD sector, UINT count){
uint32_t addr;
@@ -166,14 +173,14 @@ DRESULT SDIO_disk_read(BYTE *buff, DWORD sector, UINT count){
for (; count > 0; count--) {
/* configure read DMA */
DMA2->LIFCR = 0xffffffff;
DMA2->HIFCR = 0xffffffff;
DMASTREAM->NDTR = 0;
DMASTREAM->FCR |= 0x21 | 0x3 | (1<<DMA_SxFCR_DMDIS);
DMASTREAM->M0AR = (uint32_t)(&buffer_sdio);
DMASTREAM->PAR = (uint32_t)&(SDIO->FIFO);
DMASTREAM->CR = DMAP2M | DMA_SxCR_PL_1 | DMA_SxCR_PL_1;
DMASTREAM->CR |= DMA_SxCR_EN;
// DMA2->LIFCR = 0xffffffff;
// DMA2->HIFCR = 0xffffffff;
// DMASTREAM->NDTR = 0;
// DMASTREAM->FCR = DMA_SxFCR_FTH_0 | DMA_SxFCR_FTH_1 | DMA_SxFCR_DMDIS;
// DMASTREAM->M0AR = (uint32_t)(buff);
// DMASTREAM->PAR = (uint32_t)&(SDIO->FIFO);
// DMASTREAM->CR = DMAP2M | DMA_SxCR_PL_1 | DMA_SxCR_PL_1;
// DMASTREAM->CR |= DMA_SxCR_EN;
SDIO->DLEN = (1 << BLOCKSIZE);
@@ -187,29 +194,29 @@ DRESULT SDIO_disk_read(BYTE *buff, DWORD sector, UINT count){
SDIO->DCTRL = (BLOCKSIZE<<4) | SDIO_DCTRL_DTDIR | SDIO_DCTRL_DMAEN | SDIO_DCTRL_DTEN;
debug=0;
// counter = 0;
// while (counter < (1<<(BLOCKSIZE-2)) || !(SDIO->STA & (SDIO_STA_DBCKEND | SDIO_STA_DATAEND))) { // TODO: Handle errors
// if (SDIO->STA & (SDIO_STA_DCRCFAIL | SDIO_STA_DTIMEOUT | SDIO_STA_STBITERR))
// {
// return RES_ERROR;
// }
//
// if (SDIO->STA & SDIO_STA_RXDAVL) {
// counter++;
// fifo = SDIO->FIFO;
// *(buff++) = (BYTE)(fifo & 0xFF);
// fifo >>= 8;
// *(buff++) = (BYTE)(fifo & 0xFF);
// fifo >>= 8;
// *(buff++) = (BYTE)(fifo & 0xFF);
// fifo >>= 8;
// *(buff++) = (BYTE)(fifo & 0xFF);
// }
//
// }
// if (SDIO->STA & SDIO_STA_DCRCFAIL) return RES_ERROR;
counter = 0;
while (counter < (1<<(BLOCKSIZE-2)) || !(SDIO->STA & (SDIO_STA_DBCKEND | SDIO_STA_DATAEND))) { // TODO: Handle errors
if (SDIO->STA & (SDIO_STA_DCRCFAIL | SDIO_STA_DTIMEOUT | SDIO_STA_STBITERR))
{
return RES_ERROR;
}
while(DMASTREAM->CR & DMA_SxCR_EN);
if (SDIO->STA & SDIO_STA_RXDAVL) {
counter++;
fifo = SDIO->FIFO;
*(buff++) = (BYTE)(fifo & 0xFF);
fifo >>= 8;
*(buff++) = (BYTE)(fifo & 0xFF);
fifo >>= 8;
*(buff++) = (BYTE)(fifo & 0xFF);
fifo >>= 8;
*(buff++) = (BYTE)(fifo & 0xFF);
}
}
if (SDIO->STA & SDIO_STA_DCRCFAIL) return RES_ERROR;
//while(DMASTREAM->CR & DMA_SxCR_EN);
while(1) {
__DSB();
__DMB();
@@ -230,10 +237,6 @@ DRESULT SDIO_disk_read(BYTE *buff, DWORD sector, UINT count){
}
DMASTREAM->CR = 0x0;
while (DMASTREAM->CR);
__asm("dsb");
if (card_info.type == SD_V2_HC) {
addr++;
} else {
@@ -398,7 +401,7 @@ int SDIO_get_response(uint8_t expectedCMD, uint8_t typeOfAns, uint32_t *response
return -CTIMEOUT;
}
//Valid Respone Received
if (((SDIO->RESPCMD & SDIO_RESPCMD_RESPCMD) != expectedCMD) && expectedCMD != 0xff)
if (((SDIO->RESPCMD & SDIO_RESPCMD_RESPCMD) != expectedCMD) && (expectedCMD != 0xff))
return -1; //Not the expected respose
//If case of a correct Response
@@ -438,7 +441,6 @@ ACMD41_RESP_t SDIO_init_card_ACMD41(uint8_t HCS){
uint32_t response;
int retry = 0x20;
if (SDIO_switch_appmode_CMD55()) return ACMD41_RESP_ERR;
do {
SDIO_send_cmd(41, (HCS ? (1<<30) : 0) | (1<<28) | (1<<20) |(1<<21)|(1<<22) |(1<<23)|(1<<19), SHORT_ANS);
if (!SDIO_get_response(0xFF, SHORT_ANS, &response)) {

5
fatfs/shimatta_sdio_driver/shimatta_sdio_config.h
View File

@@ -12,13 +12,14 @@
//4 bit: 4
#define BUSWIDTH 4 //4
//Initial Transfer CLK (ca. 400kHz)
#define INITCLK 120 //120
#define INITCLK 130 //120
//Working CLK (Maximum)
#define WORKCLK 255 //0
//Data Timeout in CLK Cycles
#define DTIMEOUT 0x3000 //150
//DMA Stream used for TX and RX DMA2 Stream 3 or 6 possible
#define DMASTREAM DMA2_Stream6
// Currently not used due to possible misalignment of the data buffer.
//#define DMASTREAM DMA2_Stream6
/* Port Definitions */