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firmware/setup/system_init.c

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+/*
+* STM32L052x8 System Setup Code
+*
+* This file is part of 'STM32L052' code template'.
+*
+* It is free software: you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation, version 2 of the License.
+*
+* This code is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this template.  If not, see <http://www.gnu.org/licenses/>.
+* ------------------------------------------------------------------------
+*/
+
+#include <stm32l0xx.h>
+#include <stdint.h>
+
+/**
+ * @brief Init for 32 MHz clock
+ */
+static void __init_default_clocks(void)
+{
+	uint32_t tmp;
+
+	RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+
+	/* Set Flash Waitstate */
+	FLASH->ACR |= FLASH_ACR_LATENCY;
+
+	/* Configure interal voltage regualtor to range 1 (1.8V) */
+	PWR->CR = PWR_CR_VOS_0;
+
+	/* Enable MSI osc as main source for now to ensure we're running stable */
+	tmp = RCC->CFGR;
+	tmp &= ~0x3;
+	RCC->CFGR = tmp;
+
+	/* Enable HSI */
+	RCC->CR |= RCC_CR_HSION;
+
+	/* Wait for HSI to be ready */
+	while (!(RCC->CR & RCC_CR_HSIRDY));
+
+	/* Disable PLL */
+	RCC->CR &= ~RCC_CR_PLLON;
+	while (RCC->CR & RCC_CR_PLLRDY);
+
+	/* Reset PLL and clock div config etc. */
+	RCC->CFGR = 0;
+
+	/* Configure PLL for HSI input and 32 MHz output
+	 * PLLDIV = 2
+	 * PLLMUL = x4
+	 */
+	RCC->CFGR |= RCC_CFGR_PLLDIV_0 | RCC_CFGR_PLLMUL_0;
+
+	/* Startup PLL */
+	RCC->CR |= RCC_CR_PLLON;
+	while (!(RCC->CR & RCC_CR_PLLRDY));
+
+	/* Switch over to PLL clock. Prescalers for buses are finde with div by 1 for 32 MHz */
+	RCC->CFGR |= RCC_CFGR_SW_0 | RCC_CFGR_SW_1;
+}
+
+
+void __system_init(void)
+{
+	__init_default_clocks();
+}