Add input FIFO with TB
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58
rtl/mem/flacdec_64x08_memory.vhd
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58
rtl/mem/flacdec_64x08_memory.vhd
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-------------------------------------------------------------------------------
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-- Title : 64x08 byte single port memory
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-- Project : Shimatta VHDL FLAC Decoder
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-------------------------------------------------------------------------------
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-- File : flacdec_64x08_memory.vhd
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-- Author : Mario Huettel <mario.huettel@linux.com>
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-- Company : Shimatta
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-- Created : 2023-10-06
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-- Last update: 2023-10-06
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: This is a 64 byte single ported RAM implementation. This file
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-- should be able to infer a BRAM on FPGA targets.
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-- Swap this implementation on an ASIC flow in order to instantiate a fitting
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-- memory instance.
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-- Two instances of this memory are used in the input FIFO of the Flac decoder
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-------------------------------------------------------------------------------
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-- Copyright (c) 2023
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity flacdec_64x08_memory is
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port (
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clk : in std_logic; -- Clock
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address : in std_logic_vector(5 downto 0); -- RAM data address
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write_enable : in std_logic; -- Write enable
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read_enable : in std_logic; -- Enable readout
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write_data : in std_logic_vector(7 downto 0); -- Write data
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read_data : out std_logic_vector(7 downto 0)); -- Read data
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end entity flacdec_64x08_memory;
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architecture RTL of flacdec_64x08_memory is
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type memory_arr_t is array(natural range <>) of std_logic_vector(7 downto 0);
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signal mem : memory_arr_t(0 to 63); -- Memory array
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signal addr_s : integer range 0 to 63; -- Memory access address
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begin -- architecture RTL
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addr_s <= to_integer(unsigned(address));
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memory_proc : process is
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begin
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wait until rising_edge(clk);
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if write_enable = '1' then
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mem(addr_s) <= write_data;
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end if;
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if read_enable = '1' then
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read_data <= mem(addr_s);
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end if;
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end process memory_proc;
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end architecture RTL;
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@@ -1,143 +0,0 @@
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-------------------------------------------------------------------------------
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-- Title : FIFO for 8 bit data
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-- Project : VHDL FLAC Decoder
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-------------------------------------------------------------------------------
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-- File : flacdec_byte_fifo.vhd
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-- Author : Mario Huettel <mario.huettel@linux.com>
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-- Company :
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-- Created : 2023-10-05
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-- Last update: 2023-10-05
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: This is a generic FIFO implementation for 8 bit Data. This
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-- implementation should be able to map to a dual ported BRAM in an FPGA. If an
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-- ASIC Design is used, decide weather to use a RAM instance or let the
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-- synthesis generate a FIFO out of Flip Flops.
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-- The FIFO is 64 bytes large.
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-------------------------------------------------------------------------------
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-- Copyright (c) 2023 Mario Huettel
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity flacdec_byte_fifo is
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port (
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clk : in std_logic; -- Clock
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rst_n : in std_logic; -- async. low-active reset
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data_in : in std_logic_vector(7 downto 0);
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data_in_wstrb : in std_logic; -- Write strobe to push data into the FIFO
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data_out : out std_logic_vector(7 downto 0); -- Output data. 1 cycle delayed after read strobe.
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data_rstrb : in std_logic;
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fifo_full : out std_logic; -- FIFO is full
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fifo_empty : out std_logic; -- FIFO is empty
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fifo_32_free : out std_logic); -- FIFO has at least 32 bytes free
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end entity flacdec_byte_fifo;
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architecture RTL of flacdec_byte_fifo is
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type fifo_mem_t is array(natural range <>) of std_logic_vector(data_in'range);
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signal mem : fifo_mem_t(0 to 63);
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signal read_ptr : unsigned(6 downto 0);
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signal write_ptr : unsigned(6 downto 0);
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signal write_strb_s : std_logic;
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signal read_strb_s : std_logic;
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signal write_addr : unsigned(5 downto 0);
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signal read_addr : unsigned(5 downto 0);
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signal fifo_fill_level : integer range 0 to 64;
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signal wrapped_around : std_logic;
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signal fifo_full_s : std_logic;
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signal fifo_empty_s : std_logic;
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begin -- architecture RTL
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fifo_full <= fifo_full_s;
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fifo_empty <= fifo_empty_s;
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--------------------------------------------------------------------------
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-- FIFO memory implementation
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--------------------------------------------------------------------------
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-- FIFO memory process. Should allow BRAM infer.
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fifo_mem_proc : process is
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begin
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wait until rising_edge(clk);
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if write_strb_s = '1' then
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mem(to_integer(write_addr)) <= data_in;
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end if;
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if read_strb_s = '1' then
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data_out <= mem(to_integer(read_addr));
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end if;
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end process fifo_mem_proc;
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--------------------------------------------------------------------------
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-- FIFO fill level and address logic
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--------------------------------------------------------------------------
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-- Addresses to memory are the pointers except for the MSB, which is used
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-- for wrap around detection
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read_addr <= read_ptr(read_ptr'high - 1 downto read_ptr'low);
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write_addr <= write_ptr(write_ptr'high - 1 downto write_ptr'low);
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wrapped_around <= '1' when read_ptr(read_ptr'high) /= write_ptr(write_ptr'high) else '0';
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fill_level_proc : process(wrapped_around, read_addr, write_addr) is
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begin
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fifo_fill_level <= 0;
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if wrapped_around = '0' then
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fifo_fill_level <= to_integer(write_addr - read_addr);
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else
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fifo_fill_level <= to_integer(64 - read_addr + write_addr);
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end if;
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end process fill_level_proc;
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fifo_full_s <= '1' when read_addr = write_addr and wrapped_around = '1' else '0';
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fifo_empty_s <= '1' when read_addr = write_addr and wrapped_around = '0' else '0';
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fifo_32_free <= '1' when fifo_fill_level >= 32 else '0';
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---------------------------------------------------------------------------
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-- FIFO write pointer
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---------------------------------------------------------------------------
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write_strb_s <= data_in_wstrb and (not fifo_full_s);
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write_ptr_proc : process(clk, rst_n) is
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begin
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if rst_n = '0' then
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write_ptr <= (others => '0');
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elsif rising_edge(clk) then
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if write_strb_s = '1' then
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-- Wrap around expected
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write_ptr <= write_ptr + 1;
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end if;
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end if;
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end process write_ptr_proc;
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---------------------------------------------------------------------------
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-- FIFO read pointer
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---------------------------------------------------------------------------
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read_strb_s <= data_rstrb and (not fifo_empty_s);
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read_ptr_proc : process(clk, rst_n) is
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begin
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if rst_n = '0' then
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read_ptr <= (others => '0');
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elsif rising_edge(clk) then
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if read_strb_s = '1' then
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-- Wrap around expected
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read_ptr <= read_ptr + 1;
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end if;
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end if;
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end process read_ptr_proc;
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end architecture RTL;
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