324 lines
14 KiB
VHDL
324 lines
14 KiB
VHDL
-------------------------------------------------------------------------------
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-- Title : FIFO based on two single ported memory instances
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-- Project : Shimatta VHDL FLAC decoder
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-------------------------------------------------------------------------------
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-- File : flacdec_double_mem_fifo.vhd
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-- Author : Mario Huettel <mario.huettel@linux.com>
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-- Company :
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-- Created : 2023-10-06
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-- Last update: 2023-10-07
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-- Platform :
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: This is a FIFO implementation based on two single ported memory
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-- instances, which will allow continuous read/write with minimal arbitration
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-- overhead. The memory instances have to be connected externally.
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-------------------------------------------------------------------------------
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-- Copyright (c) 2023
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity flacdec_double_mem_fifo is
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generic (
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ADDRESS_WIDTH : natural range 2 to 32 := 7; -- Adress width of the whole FIFO memory. Defining the FIFO size
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DATA_WIDTH : positive := 8); -- Data width in bits
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port (
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clk : in std_logic; -- Clock
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rst_n : in std_logic; -- Async. low-active reset
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----------------------------------------------------------------------
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-- MEMORY 0 Connections
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----------------------------------------------------------------------
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mem0_address : out std_logic_vector(ADDRESS_WIDTH - 2 downto 0);
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mem0_write_enable : out std_logic;
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mem0_read_enable : out std_logic;
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mem0_write_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
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mem0_read_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
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----------------------------------------------------------------------
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-- MEMORY 1 Connections
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----------------------------------------------------------------------
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mem1_address : out std_logic_vector(ADDRESS_WIDTH - 2 downto 0);
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mem1_write_enable : out std_logic;
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mem1_read_enable : out std_logic;
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mem1_write_data : out std_logic_vector(DATA_WIDTH - 1 downto 0);
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mem1_read_data : in std_logic_vector(DATA_WIDTH - 1 downto 0);
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----------------------------------------------------------------------
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-- Input AXI Stream
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----------------------------------------------------------------------
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in_tdata : in std_logic_vector(DATA_WIDTH - 1 downto 0);
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in_tvalid : in std_logic;
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in_tready : out std_logic;
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----------------------------------------------------------------------
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-- Output AXI stream
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----------------------------------------------------------------------
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out_tdata : out std_logic_vector(DATA_WIDTH -1 downto 0);
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out_tvalid : out std_logic;
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out_tready : in std_logic;
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----------------------------------------------------------------------
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-- Control and status
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----------------------------------------------------------------------
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clear : in std_logic;
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flush_output : in std_logic;
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fill_level : out std_logic_vector(ADDRESS_WIDTH downto 0);
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empty : out std_logic;
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full : out std_logic;
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half_empty : out std_logic);
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end entity flacdec_double_mem_fifo;
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architecture RTL of flacdec_double_mem_fifo is
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constant FIFO_SIZE : natural := 2**ADDRESS_WIDTH;
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signal accepted_input_reg : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal accepted_input_valid_reg : std_logic;
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signal in_tready_s : std_logic;
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signal out_tvalid_reg : std_logic;
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signal out_tdata_buffer_reg : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal out_tdata_buffer_valid_reg : std_logic;
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signal fifo_read_out_data_s : std_logic_vector(DATA_WIDTH - 1 downto 0);
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signal out_ready_for_data_s : std_logic;
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signal write_pointer_reg : unsigned(ADDRESS_WIDTH downto 0);
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signal read_pointer_reg : unsigned(ADDRESS_WIDTH downto 0);
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signal write_address_s : std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
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signal read_address_s : std_logic_vector(ADDRESS_WIDTH - 1 downto 0);
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signal write_enable : std_logic;
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signal read_enable : std_logic;
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signal mem0_read_enable_s : std_logic;
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signal mem1_read_enable_s : std_logic;
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signal write_dest_mem : std_logic;
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signal read_source_mem : std_logic;
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signal read_data_valid_reg : std_logic_vector(1 downto 0);
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signal fifo_full_s : std_logic;
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signal fifo_empty_s : std_logic;
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signal fifo_half_empty_s : std_logic;
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signal fifo_fill_level_s : integer range 0 to FIFO_SIZE;
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begin -- architecture RTL
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full <= fifo_full_s;
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empty <= fifo_empty_s;
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half_empty <= fifo_half_empty_s;
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fill_level <= std_logic_vector(to_unsigned(fifo_fill_level_s, fill_level'length));
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in_tready <= in_tready_s;
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out_tvalid <= out_tvalid_reg;
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mem0_read_enable <= mem0_read_enable_s;
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mem1_read_enable <= mem1_read_enable_s;
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mem0_address <= write_address_s(write_address_s'high downto 1) when mem0_read_enable_s = '0' else read_address_s(read_address_s'high downto 1);
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mem1_address <= write_address_s(write_address_s'high downto 1) when mem1_read_enable_s = '0' else read_address_s(read_address_s'high downto 1);
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-------------------------------------------------------------------------------------------------------------------------------------------------
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-- Writing end implementation
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-------------------------------------------------------------------------------------------------------------------------------------------------
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write_address_s <= std_logic_vector(write_pointer_reg(write_pointer_reg'high - 1 downto 0));
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-- Let LSB decide which memory to write to
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write_dest_mem <= write_pointer_reg(0);
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mem0_write_enable <= write_enable when write_dest_mem = '0' else '0';
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mem1_write_enable <= write_enable when write_dest_mem = '1' else '0';
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mem0_write_data <= accepted_input_reg;
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mem1_write_data <= accepted_input_reg;
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write_enable_proc : process(accepted_input_valid_reg, write_dest_mem, mem0_read_enable_s, mem1_read_enable_s, fifo_full_s) is
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begin
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write_enable <= '0';
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-- Perform write if write destination does not collide with current
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-- read (This basically implements the arbitration between read and
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-- write, giving priority to the read path).
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if (write_dest_mem = '0' and mem0_read_enable_s = '0') or (write_dest_mem = '1' and mem1_read_enable_s = '0') then
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-- Write if data is available and the FIFO may take new data
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if accepted_input_valid_reg = '1' and fifo_full_s = '0' then
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write_enable <= '1';
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end if;
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end if;
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end process write_enable_proc;
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-- Write pointer increment upon write action
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write_pointer_proc : process(clk, rst_n) is
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begin
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if rst_n = '0' then
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write_pointer_reg <= (others => '0');
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elsif rising_edge(clk) then
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if clear = '1' then
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write_pointer_reg <= (others => '0');
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elsif write_enable = '1' then
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-- Overflow expected
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write_pointer_reg <= write_pointer_reg + 1;
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end if;
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end if;
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end process write_pointer_proc;
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-----------------------------------------------------------------
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-- AXI input
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----------------------------------------------------------------
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-- Generate the ready signal for the input stream
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axi_input_ready_proc : process(accepted_input_valid_reg, write_enable, clear) is
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begin
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in_tready_s <= '0';
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if accepted_input_valid_reg = '0' then
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in_tready_s <= '1';
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end if;
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if write_enable = '1' then
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in_tready_s <= '1';
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end if;
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if clear = '1' then
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in_tready_s <= '0';
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end if;
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end process axi_input_ready_proc;
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-- Accept the input datum into a FF buffer
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axi_input_proc : process(clk, rst_n) is
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begin
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if rst_n = '0' then
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accepted_input_reg <= (others => '0');
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accepted_input_valid_reg <= '0';
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elsif rising_edge(clk) then
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if write_enable = '1' or clear = '1' then
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-- Reset input buffer once datum is written to memory
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accepted_input_valid_reg <= '0';
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end if;
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if in_tvalid = '1' and in_tready_s = '1' then
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-- Accept datum in buffer
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accepted_input_valid_reg <= '1';
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accepted_input_reg <= in_tdata;
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end if;
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end if;
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end process axi_input_proc;
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------------------------------------------------------------------------
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-- FIFO status calculations
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------------------------------------------------------------------------
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fill_level_proc : process(read_pointer_reg, write_pointer_reg) is
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variable wrapped_around : boolean;
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variable read_addr : integer range 0 to FIFO_SIZE - 1;
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variable write_addr : integer range 0 to FIFO_SIZE - 1;
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begin
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wrapped_around := (read_pointer_reg(read_pointer_reg'high) /= write_pointer_reg(write_pointer_reg'high));
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write_addr := to_integer(write_pointer_reg(write_pointer_reg'high - 1 downto 0));
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read_addr := to_integer(read_pointer_reg(read_pointer_reg'high -1 downto 0));
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if not wrapped_around then
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fifo_fill_level_s <= write_addr - read_addr;
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else
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fifo_fill_level_s <= FIFO_SIZE - read_addr + write_addr;
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end if;
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end process fill_level_proc;
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fifo_full_s <= '1' when write_address_s = read_address_s and read_pointer_reg(read_pointer_reg'high) /= write_pointer_reg(write_pointer_reg'high) else '0';
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fifo_empty_s <= '1' when write_pointer_reg = read_pointer_reg else '0';
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fifo_half_empty_s <= '1' when fifo_fill_level_s <= FIFO_SIZE / 2 else '0';
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-----------------------------------------------------------------------------------------------------------------------------------------------
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-- READ end implementation
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-----------------------------------------------------------------------------------------------------------------------------------------------
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read_address_s <= std_logic_vector(read_pointer_reg(read_pointer_reg'high - 1 downto 0));
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read_source_mem <= read_address_s(0);
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mem0_read_enable_s <= read_enable when read_source_mem = '0' else '0';
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mem1_read_enable_s <= read_enable when read_source_mem = '1' else '0';
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read_data_valid_proc : process(clk, rst_n) is
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begin
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if rst_n = '0' then
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read_data_valid_reg <= (others => '0');
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elsif rising_edge(clk) then
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-- Delay read enables by one cycle, generating a valid signal
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read_data_valid_reg <= mem1_read_enable_s & mem0_read_enable_s;
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end if;
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end process read_data_valid_proc;
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-- Generate the read_enable signal
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-- Read from fifo if it is not empty and the output is able to accept a new
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-- datum. If clear is set, no read is requested.
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read_enable_proc : process(fifo_empty_s, out_ready_for_data_s, clear) is
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begin
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read_enable <= '0';
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if fifo_empty_s = '0' and clear = '0' then
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if out_ready_for_data_s = '1' then
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read_enable <= '1';
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end if;
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end if;
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end process read_enable_proc;
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read_pointer_proc : process(clk, rst_n) is
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begin
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if rst_n = '0' then
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read_pointer_reg <= (others => '0');
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elsif rising_edge(clk) then
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if clear = '1' then
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read_pointer_reg <= (others => '0');
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elsif read_enable = '1' then
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-- Overflow expected
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read_pointer_reg <= read_pointer_reg + 1;
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end if;
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end if;
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end process read_pointer_proc;
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--------------------
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-- Output AXI stream
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---------------------
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-- Read data mux
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fifo_read_out_data_s <= mem0_read_data when read_data_valid_reg(0) = '1' else mem1_read_data;
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-- Determine if output flops can be loaded with new data
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out_ready_for_data_s <= (not out_tvalid_reg) or out_tready;
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axi_output_proc : process(clk, rst_n) is
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begin
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if rst_n = '0' then
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out_tvalid_reg <= '0';
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out_tdata <= (others => '0');
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out_tdata_buffer_valid_reg <= '0';
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out_tdata_buffer_reg <= (others => '0');
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elsif rising_edge(clk) then
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if out_tready = '1' then
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out_tvalid_reg <= '0';
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end if;
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if flush_output = '1' then
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-- Flush the output. This breaks the stream protocol!
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out_tvalid_reg <= '0';
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out_tdata_buffer_valid_reg <= '0';
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else -- Output is not flushed
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if out_ready_for_data_s = '1' then
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if out_tdata_buffer_valid_reg = '1' then
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out_tdata <= out_tdata_buffer_reg;
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out_tvalid_reg <= '1';
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out_tdata_buffer_valid_reg <= '0';
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elsif read_data_valid_reg /= "00" then
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out_tdata <= fifo_read_out_data_s;
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out_tvalid_reg <= '1';
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end if;
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end if;
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-- Fill buffer register, if output is not ready for data or
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-- filled with old buffer data
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if read_data_valid_reg /= "00" and ((out_ready_for_data_s = '1' and out_tdata_buffer_valid_reg = '1') or out_ready_for_data_s = '0') then
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out_tdata_buffer_reg <= fifo_read_out_data_s;
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out_tdata_buffer_valid_reg <= '1';
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end if;
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end if;
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end if;
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end process axi_output_proc;
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end architecture RTL;
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