2016-11-24 22:23:33 +01:00
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EESchema Schematic File Version 2
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LIBS:power
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LIBS:device
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LIBS:transistors
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LIBS:conn
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LIBS:linear
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LIBS:regul
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LIBS:74xx
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LIBS:cmos4000
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LIBS:adc-dac
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LIBS:memory
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LIBS:xilinx
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LIBS:microcontrollers
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LIBS:dsp
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LIBS:microchip
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LIBS:analog_switches
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LIBS:motorola
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LIBS:texas
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LIBS:intel
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LIBS:audio
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LIBS:interface
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LIBS:digital-audio
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LIBS:philips
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LIBS:display
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LIBS:cypress
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LIBS:siliconi
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LIBS:opto
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LIBS:atmel
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LIBS:contrib
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LIBS:valves
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LIBS:ti
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2016-11-26 00:51:02 +01:00
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LIBS:altera
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2016-11-26 17:17:19 +01:00
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LIBS:regulators
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LIBS:pmic
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2016-11-27 13:43:11 +01:00
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LIBS:powersym
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2016-11-27 15:53:52 +01:00
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LIBS:osc
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LIBS:con-molex
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2016-11-26 00:51:02 +01:00
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LIBS:dvi-sniffer-cache
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2016-11-24 22:23:33 +01:00
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EELAYER 26 0
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EELAYER END
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2016-11-26 17:17:19 +01:00
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$Descr A3 16535 11693
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2016-11-24 22:23:33 +01:00
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encoding utf-8
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2016-11-27 18:09:10 +01:00
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Sheet 1 5
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2016-11-26 17:17:19 +01:00
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Title "DVI-Sniffer -- Top"
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2016-11-24 22:23:33 +01:00
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Date ""
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2016-11-26 17:17:19 +01:00
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Rev "0.1"
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2016-11-24 22:23:33 +01:00
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Comp ""
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Comment1 ""
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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2016-11-26 17:17:19 +01:00
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$Sheet
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S 1850 1450 1050 1250
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U 5839A46D
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F0 "power" 60
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F1 "power.sch" 60
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F2 "VIN" I L 1850 1550 60
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$EndSheet
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2016-11-24 22:23:33 +01:00
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$Comp
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2016-11-26 17:17:19 +01:00
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L BARREL_JACK CON?
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U 1 1 583A22E7
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P 1050 1650
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F 0 "CON?" H 1031 1975 50 0000 C CNN
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F 1 "BARREL_JACK" H 1031 1884 50 0000 C CNN
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F 2 "" H 1050 1650 50 0000 C CNN
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F 3 "" H 1050 1650 50 0000 C CNN
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1 1050 1650
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2016-11-24 22:23:33 +01:00
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1 0 0 -1
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$EndComp
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$Comp
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2016-11-27 15:53:52 +01:00
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L GND #PWR01
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2016-11-26 17:17:19 +01:00
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U 1 1 583A2391
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P 1450 1850
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2016-11-27 15:53:52 +01:00
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F 0 "#PWR01" H 1450 1600 50 0001 C CNN
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2016-11-26 17:17:19 +01:00
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F 1 "GND" H 1455 1677 50 0000 C CNN
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F 2 "" H 1450 1850 50 0000 C CNN
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F 3 "" H 1450 1850 50 0000 C CNN
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1 1450 1850
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2016-11-26 00:51:02 +01:00
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1 0 0 -1
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$EndComp
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2016-11-26 17:17:19 +01:00
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$Sheet
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2016-11-27 15:53:52 +01:00
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S 6600 3300 2000 2300
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2016-11-26 17:17:19 +01:00
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U 583A26B6
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F0 "fpga" 60
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F1 "fpga.sch" 60
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2016-11-27 15:53:52 +01:00
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F2 "DATI[0..23]" I L 6600 3500 60
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F3 "CLKIN" I L 6600 3700 60
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F4 "HSYNC_IN" I L 6600 3800 60
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F5 "VSYNC_IN" I L 6600 3900 60
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F6 "DE_IN" I L 6600 4000 60
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F7 "LINK_ACT_IN" I L 6600 4100 60
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F8 "TXCLK-" O R 8600 3800 60
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F9 "DATO[0..23]" O R 8600 3500 60
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F10 "HSYNC_OUT" O R 8600 3900 60
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F11 "VSYNC_OUT" O R 8600 4000 60
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F12 "DE_OUT" O R 8600 4100 60
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F13 "TXCLK+" O R 8600 3700 60
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2016-11-27 18:09:10 +01:00
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F14 "DDCDAT_IN" B L 6600 4650 60
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F15 "DDCCLK_IN" I L 6600 4550 60
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F16 "DDCDAT_OUT" B R 8600 4650 60
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F17 "DDCCLK_OUT" O R 8600 4550 60
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F18 "HOTPLUG_OUT" O L 6600 4350 60
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F19 "HOTPLUG_IN" I R 8600 4350 60
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F20 "CTL_IN[1..3]" I L 6600 3400 60
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F21 "CTL_OUT[1..3]" O R 8600 3400 60
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2016-11-26 17:17:19 +01:00
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$EndSheet
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2016-11-27 15:53:52 +01:00
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$Sheet
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S 3900 3300 1550 2300
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U 583B5F85
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F0 "dvi_in" 60
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F1 "dvi_in.sch" 60
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F2 "DATI[0..23]" O R 5450 3500 60
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2016-11-27 18:09:10 +01:00
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F3 "HOTPLUG" I R 5450 4350 60
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F4 "DDCCLK_IN" O R 5450 4550 60
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F5 "DDCDAT_IN" B R 5450 4650 60
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F6 "LINK_ACT" O R 5450 4100 60
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F7 "CTL[1..3]" O R 5450 3400 60
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F8 "DE" O R 5450 4000 60
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F9 "OCLK" O R 5450 3700 60
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F10 "HSYNC" O R 5450 3800 60
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F11 "VSYNC" O R 5450 3900 60
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2016-11-27 15:53:52 +01:00
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$EndSheet
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Text Label 5800 3500 0 60 ~ 0
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DATI[0..23]
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2016-11-27 18:09:10 +01:00
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Wire Wire Line
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1350 1650 1450 1650
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Wire Wire Line
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1450 1650 1450 1850
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Wire Wire Line
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1450 1750 1350 1750
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Connection ~ 1450 1750
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Wire Wire Line
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1350 1550 1850 1550
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Wire Bus Line
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5450 3500 6600 3500
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Wire Wire Line
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5450 3700 6600 3700
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Wire Wire Line
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5450 3800 6600 3800
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Wire Wire Line
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5450 3900 6600 3900
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Wire Wire Line
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5450 4000 6600 4000
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Wire Wire Line
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5450 4100 6600 4100
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Wire Bus Line
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5450 3400 6600 3400
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Text Label 5800 3400 0 60 ~ 0
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CTL_IN[1..3]
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Wire Wire Line
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6600 4350 5450 4350
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Wire Wire Line
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6600 4550 5450 4550
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Wire Wire Line
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5450 4650 6600 4650
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$Sheet
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S 10200 3300 1250 2300
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U 583BE4A7
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F0 "dvi_out" 60
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F1 "dvi_out.sch" 60
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$EndSheet
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2016-11-24 22:23:33 +01:00
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$EndSCHEMATC
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