Everything connected, ready for improving layout
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07f4bc1c3c
commit
e4bc30bf46
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dvi-sniffer.net
890
dvi-sniffer.net
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24
dvi_out.sch
24
dvi_out.sch
@ -613,32 +613,8 @@ Wire Wire Line
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4750 4000 5200 4000
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Wire Wire Line
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4750 4100 5200 4100
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$Comp
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L R R502
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U 1 1 5848825D
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P 4850 4300
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F 0 "R502" H 4920 4346 50 0000 L CNN
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F 1 "5k" H 4920 4255 50 0000 L CNN
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F 2 "Resistors_SMD:R_0603_HandSoldering" V 4780 4300 50 0001 C CNN
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F 3 "" H 4850 4300 50 0000 C CNN
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1 4850 4300
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0 -1 -1 0
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$EndComp
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Wire Wire Line
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5000 4300 5200 4300
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Wire Wire Line
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4650 4300 4700 4300
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$Comp
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L +3V3 #PWR083
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U 1 1 584885B1
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P 4650 4300
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F 0 "#PWR083" H 4650 4150 50 0001 C CNN
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F 1 "+3V3" H 4665 4473 50 0000 C CNN
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F 2 "" H 4650 4300 50 0000 C CNN
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F 3 "" H 4650 4300 50 0000 C CNN
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1 4650 4300
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0 -1 -1 0
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$EndComp
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Text Label 5000 4300 0 60 ~ 0
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MSEN
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Text Label 1350 1200 0 60 ~ 0
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2
fpga.sch
2
fpga.sch
@ -190,7 +190,7 @@ U 1 1 583A4F22
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P 1400 3900
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F 0 "P301" H 1400 4315 50 0000 C CNN
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F 1 "CONN_02X05" H 1400 4224 50 0000 C CNN
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F 2 "Connectors:IDC_Header_Straight_10pins" H 1400 2700 50 0001 C CNN
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F 2 "Connectors_Multicomp:Multicomp_MC9A12-1034_2x05x2.54mm_Straight" H 1400 2700 50 0001 C CNN
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F 3 "" H 1400 2700 50 0000 C CNN
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1 1400 3900
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1 0 0 -1
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