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Everything connected, ready for improving layout

This commit is contained in:
Mario Hüttel 2017-01-21 17:44:52 +01:00
parent 07f4bc1c3c
commit e4bc30bf46
4 changed files with 6543 additions and 4239 deletions
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9866
dvi-sniffer.kicad_pcb
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dvi-sniffer.net
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dvi_out.sch
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@ -613,32 +613,8 @@ Wire Wire Line
4750 4000 5200 4000
Wire Wire Line
4750 4100 5200 4100
$Comp
L R R502
U 1 1 5848825D
P 4850 4300
F 0 "R502" H 4920 4346 50 0000 L CNN
F 1 "5k" H 4920 4255 50 0000 L CNN
F 2 "Resistors_SMD:R_0603_HandSoldering" V 4780 4300 50 0001 C CNN
F 3 "" H 4850 4300 50 0000 C CNN
1 4850 4300
0 -1 -1 0
$EndComp
Wire Wire Line
5000 4300 5200 4300
Wire Wire Line
4650 4300 4700 4300
$Comp
L +3V3 #PWR083
U 1 1 584885B1
P 4650 4300
F 0 "#PWR083" H 4650 4150 50 0001 C CNN
F 1 "+3V3" H 4665 4473 50 0000 C CNN
F 2 "" H 4650 4300 50 0000 C CNN
F 3 "" H 4650 4300 50 0000 C CNN
1 4650 4300
0 -1 -1 0
$EndComp
Text Label 5000 4300 0 60 ~ 0
MSEN
Text Label 1350 1200 0 60 ~ 0

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fpga.sch
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@ -190,7 +190,7 @@ U 1 1 583A4F22
P 1400 3900
F 0 "P301" H 1400 4315 50 0000 C CNN
F 1 "CONN_02X05" H 1400 4224 50 0000 C CNN
F 2 "Connectors:IDC_Header_Straight_10pins" H 1400 2700 50 0001 C CNN
F 2 "Connectors_Multicomp:Multicomp_MC9A12-1034_2x05x2.54mm_Straight" H 1400 2700 50 0001 C CNN
F 3 "" H 1400 2700 50 0000 C CNN
1 1400 3900
1 0 0 -1