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headphone-amp/headphone-amp.kicad_pcb

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redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(kicad_pcb (version 20170922) (host pcbnew "(2017-10-03 revision 3d1569081)-master")
Layouted first draft
2017-06-09 00:41:36 +02:00
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(general
(thickness 1.6)
(drawings 5)
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(tracks 933)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(zones 0)
(modules 104)
(nets 70)
)
Layouted first draft
2017-06-09 00:41:36 +02:00
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user hide)
(49 F.Fab user hide)
)
Layouted first draft
2017-06-09 00:41:36 +02:00
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(general
(thickness 1.6)
(drawings 5)
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(tracks 933)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(zones 0)
(modules 104)
(nets 70)
)
Layouted first draft
2017-06-09 00:41:36 +02:00
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user hide)
(49 F.Fab user hide)
)
(setup
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(last_trace_width 0.4)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(user_trace_width 0.2)
(user_trace_width 0.25)
(user_trace_width 0.6)
(user_trace_width 0.8)
(user_trace_width 1.5)
(trace_clearance 0.2)
(zone_clearance 0.3)
(zone_45_only yes)
(trace_min 0.2)
(segment_width 0.2)
(edge_width 0.15)
(via_size 0.6)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(user_via 0.5 0.3)
(user_via 1.3 1)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(pad_size 3 4)
(pad_drill 0)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(pad_to_mask_clearance 0.2)
(aux_axis_origin 0 0)
(visible_elements FFFFFFFF)
(pcbplotparams
(layerselection 0x010f0_80000001)
(usegerberextensions true)
(usegerberattributes true)
(usegerberadvancedattributes true)
(creategerberjobfile true)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue false)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 0)
(scaleselection 1)
(outputdirectory gerber/))
)
(net 0 "")
(net 1 Earth)
(net 2 "Net-(C1-Pad1)")
(net 3 +5V)
(net 4 "Net-(C4-Pad2)")
(net 5 "Net-(C5-Pad1)")
(net 6 +3V3)
(net 7 /LUSB)
(net 8 "Net-(C12-Pad1)")
(net 9 "Net-(C13-Pad2)")
(net 10 "Net-(C14-Pad1)")
(net 11 /RUSB)
(net 12 "Net-(C15-Pad1)")
(net 13 GNDPWR)
(net 14 "Net-(C16-Pad1)")
(net 15 "Net-(C17-Pad2)")
(net 16 "Net-(C18-Pad2)")
(net 17 "Net-(C21-Pad1)")
(net 18 "Net-(C22-Pad2)")
(net 19 +12V)
(net 20 -12V)
(net 21 "Net-(C27-Pad1)")
(net 22 "Net-(C29-Pad1)")
(net 23 "Net-(C30-Pad1)")
(net 24 "Net-(C31-Pad1)")
(net 25 "Net-(C33-Pad2)")
(net 26 "Net-(C35-Pad2)")
(net 27 "Net-(D1-Pad1)")
(net 28 "Net-(J1-Pad4)")
(net 29 /D+)
(net 30 /D-)
(net 31 GNDA)
(net 32 "Net-(J4-Pad4)")
(net 33 "Net-(J4-Pad6)")
(net 34 "Net-(J4-Pad5)")
(net 35 "Net-(J4-Pad2)")
(net 36 "Net-(J4-Pad3)")
(net 37 "Net-(K1-Pad6)")
(net 38 "Net-(K1-Pad3)")
(net 39 "Net-(R2-Pad2)")
(net 40 "Net-(R3-Pad1)")
(net 41 "Net-(R7-Pad2)")
(net 42 "Net-(R11-Pad2)")
(net 43 "Net-(R10-Pad2)")
(net 44 "Net-(R12-Pad2)")
(net 45 "Net-(R13-Pad2)")
(net 46 "Net-(R14-Pad1)")
(net 47 "Net-(R15-Pad2)")
(net 48 "Net-(R16-Pad1)")
(net 49 "Net-(TP1-Pad1)")
(net 50 "Net-(TP2-Pad1)")
(net 51 "Net-(TP3-Pad1)")
(net 52 "Net-(U1-Pad5)")
(net 53 "Net-(U1-Pad2)")
(net 54 "Net-(C37-Pad1)")
(net 55 "Net-(C38-Pad1)")
(net 56 "Net-(R23-Pad2)")
(net 57 "Net-(R23-Pad1)")
(net 58 "Net-(R24-Pad2)")
(net 59 "Net-(R24-Pad1)")
(net 60 "Net-(C45-Pad2)")
(net 61 "Net-(C45-Pad1)")
(net 62 "Net-(C46-Pad2)")
(net 63 "Net-(C46-Pad1)")
(net 64 "Net-(C47-Pad1)")
(net 65 "Net-(D2-Pad2)")
(net 66 "Net-(K1-Pad8)")
(net 67 "Net-(K2-Pad8)")
(net 68 "Net-(R25-Pad1)")
(net 69 /SSPND)
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 0.4)
(via_dia 0.6)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net +12V)
(add_net +3V3)
(add_net +5V)
(add_net -12V)
(add_net /D+)
(add_net /D-)
(add_net /LUSB)
(add_net /RUSB)
(add_net /SSPND)
(add_net Earth)
(add_net GNDA)
(add_net GNDPWR)
(add_net "Net-(C1-Pad1)")
(add_net "Net-(C12-Pad1)")
(add_net "Net-(C13-Pad2)")
(add_net "Net-(C14-Pad1)")
(add_net "Net-(C15-Pad1)")
(add_net "Net-(C16-Pad1)")
(add_net "Net-(C17-Pad2)")
(add_net "Net-(C18-Pad2)")
(add_net "Net-(C21-Pad1)")
(add_net "Net-(C22-Pad2)")
(add_net "Net-(C27-Pad1)")
(add_net "Net-(C29-Pad1)")
(add_net "Net-(C30-Pad1)")
(add_net "Net-(C31-Pad1)")
(add_net "Net-(C33-Pad2)")
(add_net "Net-(C35-Pad2)")
(add_net "Net-(C37-Pad1)")
(add_net "Net-(C38-Pad1)")
(add_net "Net-(C4-Pad2)")
(add_net "Net-(C45-Pad1)")
(add_net "Net-(C45-Pad2)")
(add_net "Net-(C46-Pad1)")
(add_net "Net-(C46-Pad2)")
(add_net "Net-(C47-Pad1)")
(add_net "Net-(C5-Pad1)")
(add_net "Net-(D1-Pad1)")
(add_net "Net-(D2-Pad2)")
(add_net "Net-(J1-Pad4)")
(add_net "Net-(J4-Pad2)")
(add_net "Net-(J4-Pad3)")
(add_net "Net-(J4-Pad4)")
(add_net "Net-(J4-Pad5)")
(add_net "Net-(J4-Pad6)")
(add_net "Net-(K1-Pad3)")
(add_net "Net-(K1-Pad6)")
(add_net "Net-(K1-Pad8)")
(add_net "Net-(K2-Pad8)")
(add_net "Net-(R10-Pad2)")
(add_net "Net-(R11-Pad2)")
(add_net "Net-(R12-Pad2)")
(add_net "Net-(R13-Pad2)")
(add_net "Net-(R14-Pad1)")
(add_net "Net-(R15-Pad2)")
(add_net "Net-(R16-Pad1)")
(add_net "Net-(R2-Pad2)")
(add_net "Net-(R23-Pad1)")
(add_net "Net-(R23-Pad2)")
(add_net "Net-(R24-Pad1)")
(add_net "Net-(R24-Pad2)")
(add_net "Net-(R25-Pad1)")
(add_net "Net-(R3-Pad1)")
(add_net "Net-(R7-Pad2)")
(add_net "Net-(TP1-Pad1)")
(add_net "Net-(TP2-Pad1)")
(add_net "Net-(TP3-Pad1)")
(add_net "Net-(U1-Pad2)")
(add_net "Net-(U1-Pad5)")
)
Layouted first draft
2017-06-09 00:41:36 +02:00
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(module Capacitors_THT:C_Radial_D8_L11.5_P3.5 (layer F.Cu) (tedit 0) (tstamp 5978A803)
(at 83 22.5 270)
(descr "Radial Electrolytic Capacitor Diameter 8mm x Length 11.5mm, Pitch 3.5mm")
(tags "Electrolytic Capacitor")
(path /593064DB)
Layout: Silkscreen Fix
2017-09-10 20:10:51 +02:00
(fp_text reference C25 (at -2.25 -4 270) (layer F.SilkS)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100u (at 1.75 5.3 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.75 0) (end 1.75 -4.3) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1.75 0) (end 1.75 -4.0375) (layer F.SilkS) (width 0.15))
(fp_circle (center 3.5 0) (end 3.5 -1) (layer F.SilkS) (width 0.15))
(fp_line (start 5.745 -0.2) (end 5.745 0.2) (layer F.SilkS) (width 0.15))
(fp_line (start 5.605 -1.067) (end 5.605 1.067) (layer F.SilkS) (width 0.15))
(fp_line (start 5.465 -1.483) (end 5.465 1.483) (layer F.SilkS) (width 0.15))
(fp_line (start 5.325 -1.794) (end 5.325 1.794) (layer F.SilkS) (width 0.15))
(fp_line (start 5.185 -2.05) (end 5.185 2.05) (layer F.SilkS) (width 0.15))
(fp_line (start 5.045 -2.268) (end 5.045 2.268) (layer F.SilkS) (width 0.15))
(fp_line (start 4.905 -2.459) (end 4.905 2.459) (layer F.SilkS) (width 0.15))
(fp_line (start 4.765 -2.629) (end 4.765 2.629) (layer F.SilkS) (width 0.15))
(fp_line (start 4.625 -2.781) (end 4.625 2.781) (layer F.SilkS) (width 0.15))
(fp_line (start 4.485 0.173) (end 4.485 2.919) (layer F.SilkS) (width 0.15))
(fp_line (start 4.485 -2.919) (end 4.485 -0.173) (layer F.SilkS) (width 0.15))
(fp_line (start 4.345 0.535) (end 4.345 3.044) (layer F.SilkS) (width 0.15))
(fp_line (start 4.345 -3.044) (end 4.345 -0.535) (layer F.SilkS) (width 0.15))
(fp_line (start 4.205 0.709) (end 4.205 3.158) (layer F.SilkS) (width 0.15))
(fp_line (start 4.205 -3.158) (end 4.205 -0.709) (layer F.SilkS) (width 0.15))
(fp_line (start 4.065 0.825) (end 4.065 3.262) (layer F.SilkS) (width 0.15))
(fp_line (start 4.065 -3.262) (end 4.065 -0.825) (layer F.SilkS) (width 0.15))
(fp_line (start 3.925 0.905) (end 3.925 3.357) (layer F.SilkS) (width 0.15))
(fp_line (start 3.925 -3.357) (end 3.925 -0.905) (layer F.SilkS) (width 0.15))
(fp_line (start 3.785 0.959) (end 3.785 3.444) (layer F.SilkS) (width 0.15))
(fp_line (start 3.785 -3.444) (end 3.785 -0.959) (layer F.SilkS) (width 0.15))
(fp_line (start 3.645 0.989) (end 3.645 3.523) (layer F.SilkS) (width 0.15))
(fp_line (start 3.645 -3.523) (end 3.645 -0.989) (layer F.SilkS) (width 0.15))
(fp_line (start 3.505 1) (end 3.505 3.594) (layer F.SilkS) (width 0.15))
(fp_line (start 3.505 -3.594) (end 3.505 -1) (layer F.SilkS) (width 0.15))
(fp_line (start 3.365 0.991) (end 3.365 3.659) (layer F.SilkS) (width 0.15))
(fp_line (start 3.365 -3.659) (end 3.365 -0.991) (layer F.SilkS) (width 0.15))
(fp_line (start 3.225 0.961) (end 3.225 3.718) (layer F.SilkS) (width 0.15))
(fp_line (start 3.225 -3.718) (end 3.225 -0.961) (layer F.SilkS) (width 0.15))
(fp_line (start 3.085 0.91) (end 3.085 3.771) (layer F.SilkS) (width 0.15))
(fp_line (start 3.085 -3.771) (end 3.085 -0.91) (layer F.SilkS) (width 0.15))
(fp_line (start 2.945 0.832) (end 2.945 3.817) (layer F.SilkS) (width 0.15))
(fp_line (start 2.945 -3.817) (end 2.945 -0.832) (layer F.SilkS) (width 0.15))
(fp_line (start 2.805 0.719) (end 2.805 3.858) (layer F.SilkS) (width 0.15))
(fp_line (start 2.805 -3.858) (end 2.805 -0.719) (layer F.SilkS) (width 0.15))
(fp_line (start 2.665 0.55) (end 2.665 3.894) (layer F.SilkS) (width 0.15))
(fp_line (start 2.665 -3.894) (end 2.665 -0.55) (layer F.SilkS) (width 0.15))
(fp_line (start 2.525 0.222) (end 2.525 3.924) (layer F.SilkS) (width 0.15))
(fp_line (start 2.525 -3.924) (end 2.525 -0.222) (layer F.SilkS) (width 0.15))
(fp_line (start 2.385 -3.949) (end 2.385 3.949) (layer F.SilkS) (width 0.15))
(fp_line (start 2.245 -3.969) (end 2.245 3.969) (layer F.SilkS) (width 0.15))
(fp_line (start 2.105 -3.984) (end 2.105 3.984) (layer F.SilkS) (width 0.15))
(fp_line (start 1.965 -3.994) (end 1.965 3.994) (layer F.SilkS) (width 0.15))
(fp_line (start 1.825 -3.999) (end 1.825 3.999) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole rect (at 0 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 19 +12V))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(pad 2 thru_hole circle (at 3.5 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(model Capacitors_ThroughHole.3dshapes/C_Radial_D8_L11.5_P3.5.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(module Connectors:USB_Mini-B (layer F.Cu) (tedit 5543E571) (tstamp 5978A85A)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(at 16 28.5)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(descr "USB Mini-B 5-pin SMD connector")
(tags "USB USB_B USB_Mini connector")
(path /5976A1B4)
(attr smd)
(fp_text reference J1 (at -1.85 6.61) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value USB_OTG (at 0 -7.0993) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 4.59994 -3.85064) (end -4.59994 -3.85064) (layer F.SilkS) (width 0.15))
(fp_line (start 4.59994 3.85064) (end 4.59994 -3.85064) (layer F.SilkS) (width 0.15))
(fp_line (start -4.59994 3.85064) (end 4.59994 3.85064) (layer F.SilkS) (width 0.15))
(fp_line (start -4.59994 -3.85064) (end -4.59994 3.85064) (layer F.SilkS) (width 0.15))
(fp_line (start -3.59918 -3.85064) (end -3.59918 3.85064) (layer F.SilkS) (width 0.15))
(fp_line (start -4.85 5.7) (end -4.85 -5.7) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.85 5.7) (end -4.85 5.7) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.85 -5.7) (end 4.85 5.7) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.85 -5.7) (end 4.85 -5.7) (layer F.CrtYd) (width 0.05))
(pad "" np_thru_hole circle (at 0.8509 2.19964) (size 0.89916 0.89916) (drill 0.89916) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 0.8509 -2.19964) (size 0.89916 0.89916) (drill 0.89916) (layers *.Cu *.Mask))
(pad 6 smd rect (at -2.14884 4.45008) (size 2.49936 1.99898) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 6 smd rect (at 3.35026 4.45008) (size 2.49936 1.99898) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 6 smd rect (at -2.14884 -4.45008) (size 2.49936 1.99898) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 6 smd rect (at 3.35026 -4.45008) (size 2.49936 1.99898) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 5 smd rect (at 3.44932 1.6002) (size 2.30124 0.50038) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 4 smd rect (at 3.44932 0.8001) (size 2.30124 0.50038) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 28 "Net-(J1-Pad4)"))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(pad 3 smd rect (at 3.44932 0) (size 2.30124 0.50038) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 29 /D+))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(pad 2 smd rect (at 3.44932 -0.8001) (size 2.30124 0.50038) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 30 /D-))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(pad 1 smd rect (at 3.44932 -1.6002) (size 2.30124 0.50038) (layers F.Cu F.Paste F.Mask)
(net 3 +5V))
)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(module Capacitors_THT:C_Radial_D5_L11_P2 (layer F.Cu) (tedit 0) (tstamp 5978A773)
(at 31.98 36.22 270)
(descr "Radial Electrolytic Capacitor 5mm x Length 11mm, Pitch 2mm")
(tags "Electrolytic Capacitor")
(path /5934B839)
(fp_text reference C1 (at 1 -3.8 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10u (at 1 3.8 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1 0) (end 1 -2.8) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1 0) (end 1 -2.5375) (layer F.SilkS) (width 0.15))
(fp_circle (center 2 0) (end 2 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 3.455 -0.472) (end 3.455 0.472) (layer F.SilkS) (width 0.15))
(fp_line (start 3.315 -0.944) (end 3.315 0.944) (layer F.SilkS) (width 0.15))
(fp_line (start 3.175 -1.233) (end 3.175 1.233) (layer F.SilkS) (width 0.15))
(fp_line (start 3.035 -1.452) (end 3.035 1.452) (layer F.SilkS) (width 0.15))
(fp_line (start 2.895 -1.631) (end 2.895 1.631) (layer F.SilkS) (width 0.15))
(fp_line (start 2.755 0.265) (end 2.755 1.78) (layer F.SilkS) (width 0.15))
(fp_line (start 2.755 -1.78) (end 2.755 -0.265) (layer F.SilkS) (width 0.15))
(fp_line (start 2.615 0.512) (end 2.615 1.908) (layer F.SilkS) (width 0.15))
(fp_line (start 2.615 -1.908) (end 2.615 -0.512) (layer F.SilkS) (width 0.15))
(fp_line (start 2.475 0.644) (end 2.475 2.019) (layer F.SilkS) (width 0.15))
(fp_line (start 2.475 -2.019) (end 2.475 -0.644) (layer F.SilkS) (width 0.15))
(fp_line (start 2.335 0.726) (end 2.335 2.114) (layer F.SilkS) (width 0.15))
(fp_line (start 2.335 -2.114) (end 2.335 -0.726) (layer F.SilkS) (width 0.15))
(fp_line (start 2.195 0.776) (end 2.195 2.196) (layer F.SilkS) (width 0.15))
(fp_line (start 2.195 -2.196) (end 2.195 -0.776) (layer F.SilkS) (width 0.15))
(fp_line (start 2.055 0.798) (end 2.055 2.266) (layer F.SilkS) (width 0.15))
(fp_line (start 2.055 -2.266) (end 2.055 -0.798) (layer F.SilkS) (width 0.15))
(fp_line (start 1.915 0.795) (end 1.915 2.327) (layer F.SilkS) (width 0.15))
(fp_line (start 1.915 -2.327) (end 1.915 -0.795) (layer F.SilkS) (width 0.15))
(fp_line (start 1.775 0.768) (end 1.775 2.377) (layer F.SilkS) (width 0.15))
(fp_line (start 1.775 -2.377) (end 1.775 -0.768) (layer F.SilkS) (width 0.15))
(fp_line (start 1.635 0.712) (end 1.635 2.418) (layer F.SilkS) (width 0.15))
(fp_line (start 1.635 -2.418) (end 1.635 -0.712) (layer F.SilkS) (width 0.15))
(fp_line (start 1.495 0.62) (end 1.495 2.451) (layer F.SilkS) (width 0.15))
(fp_line (start 1.495 -2.451) (end 1.495 -0.62) (layer F.SilkS) (width 0.15))
(fp_line (start 1.355 0.473) (end 1.355 2.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1.355 -2.475) (end 1.355 -0.473) (layer F.SilkS) (width 0.15))
(fp_line (start 1.215 0.154) (end 1.215 2.491) (layer F.SilkS) (width 0.15))
(fp_line (start 1.215 -2.491) (end 1.215 -0.154) (layer F.SilkS) (width 0.15))
(fp_line (start 1.075 -2.499) (end 1.075 2.499) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole circle (at 2 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
(net 1 Earth))
(pad 1 thru_hole rect (at 0 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
(net 2 "Net-(C1-Pad1)"))
(model Capacitors_ThroughHole.3dshapes/C_Radial_D5_L11_P2.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A779)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(at 25.5 35.5)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5934BF3E)
(attr smd)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference C2 (at 0.51 -2.14) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 2 "Net-(C1-Pad1)"))
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A77F)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(at 21.5 35.5)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59305590)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C3 (at -3.5 0) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 200n (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 3 +5V))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A785)
(at 35.75 33.59 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5934A4BD)
(attr smd)
(fp_text reference C4 (at 0 1.9 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1u (at 0 -1.9 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 4 "Net-(C4-Pad2)"))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 1 Earth))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A78B)
(at 37.5 17.5)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59348C90)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C5 (at 0 -1.5) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 27p (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 5 "Net-(C5-Pad1)"))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A791)
(at 32.5 28.5 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5934D473)
(attr smd)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(fp_text reference C6 (at -0.25 -2 270) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 200n (at 0 1.9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 6 +3V3))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A797)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(at 28 44 180)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5935AC3B)
(attr smd)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(fp_text reference C7 (at -3 0 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 60 "Net-(C45-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 61 "Net-(C45-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A79D)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(at 20.06 48.2 90)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5935A9B7)
(attr smd)
(fp_text reference C8 (at 0 1.9 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1u (at 0 -1.9 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 62 "Net-(C46-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 63 "Net-(C46-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A7A3)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(at 34 41.5 90)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /593501B5)
(attr smd)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(fp_text reference C9 (at 0 1.75 90) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(fp_text value 1u (at 0 1.9 90) (layer F.Fab)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 64 "Net-(C47-Pad1)"))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 7 /LUSB))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_Tantalum_SMD:Tantalum_Case-D_EIA-7343-31_Hand (layer F.Cu) (tedit 57B6E980) (tstamp 5978A7A9)
(at 58 50)
(descr "Tantalum capacitor, Case D, EIA 7343-31, 7.3x4.3x2.8mm, Hand soldering footprint")
(tags "capacitor tantalum smd")
(path /593055F7)
(attr smd)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(fp_text reference C10 (at -0.08 0.01) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100u (at 0 3.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -5.95 -2.4) (end -5.95 2.4) (layer F.SilkS) (width 0.15))
(fp_line (start -5.95 2.4) (end 3.65 2.4) (layer F.SilkS) (width 0.15))
(fp_line (start -5.95 -2.4) (end 3.65 -2.4) (layer F.SilkS) (width 0.15))
(fp_line (start -2.555 -2.15) (end -2.555 2.15) (layer F.Fab) (width 0.15))
(fp_line (start -2.92 -2.15) (end -2.92 2.15) (layer F.Fab) (width 0.15))
(fp_line (start 3.65 -2.15) (end -3.65 -2.15) (layer F.Fab) (width 0.15))
(fp_line (start 3.65 2.15) (end 3.65 -2.15) (layer F.Fab) (width 0.15))
(fp_line (start -3.65 2.15) (end 3.65 2.15) (layer F.Fab) (width 0.15))
(fp_line (start -3.65 -2.15) (end -3.65 2.15) (layer F.Fab) (width 0.15))
(fp_line (start 6.05 -2.5) (end -6.05 -2.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.05 2.5) (end 6.05 -2.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.05 2.5) (end 6.05 2.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.05 -2.5) (end -6.05 2.5) (layer F.CrtYd) (width 0.05))
(pad 2 smd rect (at 3.775 0) (size 3.75 2.7) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 1 smd rect (at -3.775 0) (size 3.75 2.7) (layers F.Cu F.Paste F.Mask)
(net 3 +5V))
(model Capacitors_Tantalum_SMD.3dshapes/Tantalum_Case-D_EIA-7343-31.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A7AF)
(at 56.5 43.05 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5930565F)
(attr smd)
(fp_text reference C11 (at 0 1.9 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.9 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 1 Earth))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 3 +5V))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A7B5)
(at 38.5 41.5 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5934FA03)
(attr smd)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(fp_text reference C12 (at 2.75 0.5 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 22n (at 0 1.9 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 8 "Net-(C12-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A7BB)
(at 41 41.5 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5934F029)
(attr smd)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(fp_text reference C13 (at -2.75 0.25) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 22n (at 0 1.9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 9 "Net-(C13-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A7C1)
(at 41.5 17.5 180)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59348F37)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C14 (at 0 1.5 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 27p (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 10 "Net-(C14-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A7C7)
(at 43 41.5 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5934F52B)
(attr smd)
(fp_text reference C15 (at 0 -1.9 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 1.9 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 11 /RUSB))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 12 "Net-(C15-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_THT:C_Radial_D5_L11_P2 (layer F.Cu) (tedit 0) (tstamp 5978A7CD)
(at 64.36 22.92 270)
(descr "Radial Electrolytic Capacitor 5mm x Length 11mm, Pitch 2mm")
(tags "Electrolytic Capacitor")
(path /59305A96)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(fp_text reference C16 (at -2.72 -0.04) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10u (at 1 3.8 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1 0) (end 1 -2.8) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1 0) (end 1 -2.5375) (layer F.SilkS) (width 0.15))
(fp_circle (center 2 0) (end 2 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 3.455 -0.472) (end 3.455 0.472) (layer F.SilkS) (width 0.15))
(fp_line (start 3.315 -0.944) (end 3.315 0.944) (layer F.SilkS) (width 0.15))
(fp_line (start 3.175 -1.233) (end 3.175 1.233) (layer F.SilkS) (width 0.15))
(fp_line (start 3.035 -1.452) (end 3.035 1.452) (layer F.SilkS) (width 0.15))
(fp_line (start 2.895 -1.631) (end 2.895 1.631) (layer F.SilkS) (width 0.15))
(fp_line (start 2.755 0.265) (end 2.755 1.78) (layer F.SilkS) (width 0.15))
(fp_line (start 2.755 -1.78) (end 2.755 -0.265) (layer F.SilkS) (width 0.15))
(fp_line (start 2.615 0.512) (end 2.615 1.908) (layer F.SilkS) (width 0.15))
(fp_line (start 2.615 -1.908) (end 2.615 -0.512) (layer F.SilkS) (width 0.15))
(fp_line (start 2.475 0.644) (end 2.475 2.019) (layer F.SilkS) (width 0.15))
(fp_line (start 2.475 -2.019) (end 2.475 -0.644) (layer F.SilkS) (width 0.15))
(fp_line (start 2.335 0.726) (end 2.335 2.114) (layer F.SilkS) (width 0.15))
(fp_line (start 2.335 -2.114) (end 2.335 -0.726) (layer F.SilkS) (width 0.15))
(fp_line (start 2.195 0.776) (end 2.195 2.196) (layer F.SilkS) (width 0.15))
(fp_line (start 2.195 -2.196) (end 2.195 -0.776) (layer F.SilkS) (width 0.15))
(fp_line (start 2.055 0.798) (end 2.055 2.266) (layer F.SilkS) (width 0.15))
(fp_line (start 2.055 -2.266) (end 2.055 -0.798) (layer F.SilkS) (width 0.15))
(fp_line (start 1.915 0.795) (end 1.915 2.327) (layer F.SilkS) (width 0.15))
(fp_line (start 1.915 -2.327) (end 1.915 -0.795) (layer F.SilkS) (width 0.15))
(fp_line (start 1.775 0.768) (end 1.775 2.377) (layer F.SilkS) (width 0.15))
(fp_line (start 1.775 -2.377) (end 1.775 -0.768) (layer F.SilkS) (width 0.15))
(fp_line (start 1.635 0.712) (end 1.635 2.418) (layer F.SilkS) (width 0.15))
(fp_line (start 1.635 -2.418) (end 1.635 -0.712) (layer F.SilkS) (width 0.15))
(fp_line (start 1.495 0.62) (end 1.495 2.451) (layer F.SilkS) (width 0.15))
(fp_line (start 1.495 -2.451) (end 1.495 -0.62) (layer F.SilkS) (width 0.15))
(fp_line (start 1.355 0.473) (end 1.355 2.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1.355 -2.475) (end 1.355 -0.473) (layer F.SilkS) (width 0.15))
(fp_line (start 1.215 0.154) (end 1.215 2.491) (layer F.SilkS) (width 0.15))
(fp_line (start 1.215 -2.491) (end 1.215 -0.154) (layer F.SilkS) (width 0.15))
(fp_line (start 1.075 -2.499) (end 1.075 2.499) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole circle (at 2 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 thru_hole rect (at 0 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 14 "Net-(C16-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_ThroughHole.3dshapes/C_Radial_D5_L11_P2.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_THT:C_Radial_D5_L11_P2 (layer F.Cu) (tedit 0) (tstamp 5978A7D3)
(at 64.5 29 270)
(descr "Radial Electrolytic Capacitor 5mm x Length 11mm, Pitch 2mm")
(tags "Electrolytic Capacitor")
(path /59305B29)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C17 (at 0 3.5 270) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10u (at 1 3.8 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1 0) (end 1 -2.8) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1 0) (end 1 -2.5375) (layer F.SilkS) (width 0.15))
(fp_circle (center 2 0) (end 2 -0.8) (layer F.SilkS) (width 0.15))
(fp_line (start 3.455 -0.472) (end 3.455 0.472) (layer F.SilkS) (width 0.15))
(fp_line (start 3.315 -0.944) (end 3.315 0.944) (layer F.SilkS) (width 0.15))
(fp_line (start 3.175 -1.233) (end 3.175 1.233) (layer F.SilkS) (width 0.15))
(fp_line (start 3.035 -1.452) (end 3.035 1.452) (layer F.SilkS) (width 0.15))
(fp_line (start 2.895 -1.631) (end 2.895 1.631) (layer F.SilkS) (width 0.15))
(fp_line (start 2.755 0.265) (end 2.755 1.78) (layer F.SilkS) (width 0.15))
(fp_line (start 2.755 -1.78) (end 2.755 -0.265) (layer F.SilkS) (width 0.15))
(fp_line (start 2.615 0.512) (end 2.615 1.908) (layer F.SilkS) (width 0.15))
(fp_line (start 2.615 -1.908) (end 2.615 -0.512) (layer F.SilkS) (width 0.15))
(fp_line (start 2.475 0.644) (end 2.475 2.019) (layer F.SilkS) (width 0.15))
(fp_line (start 2.475 -2.019) (end 2.475 -0.644) (layer F.SilkS) (width 0.15))
(fp_line (start 2.335 0.726) (end 2.335 2.114) (layer F.SilkS) (width 0.15))
(fp_line (start 2.335 -2.114) (end 2.335 -0.726) (layer F.SilkS) (width 0.15))
(fp_line (start 2.195 0.776) (end 2.195 2.196) (layer F.SilkS) (width 0.15))
(fp_line (start 2.195 -2.196) (end 2.195 -0.776) (layer F.SilkS) (width 0.15))
(fp_line (start 2.055 0.798) (end 2.055 2.266) (layer F.SilkS) (width 0.15))
(fp_line (start 2.055 -2.266) (end 2.055 -0.798) (layer F.SilkS) (width 0.15))
(fp_line (start 1.915 0.795) (end 1.915 2.327) (layer F.SilkS) (width 0.15))
(fp_line (start 1.915 -2.327) (end 1.915 -0.795) (layer F.SilkS) (width 0.15))
(fp_line (start 1.775 0.768) (end 1.775 2.377) (layer F.SilkS) (width 0.15))
(fp_line (start 1.775 -2.377) (end 1.775 -0.768) (layer F.SilkS) (width 0.15))
(fp_line (start 1.635 0.712) (end 1.635 2.418) (layer F.SilkS) (width 0.15))
(fp_line (start 1.635 -2.418) (end 1.635 -0.712) (layer F.SilkS) (width 0.15))
(fp_line (start 1.495 0.62) (end 1.495 2.451) (layer F.SilkS) (width 0.15))
(fp_line (start 1.495 -2.451) (end 1.495 -0.62) (layer F.SilkS) (width 0.15))
(fp_line (start 1.355 0.473) (end 1.355 2.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1.355 -2.475) (end 1.355 -0.473) (layer F.SilkS) (width 0.15))
(fp_line (start 1.215 0.154) (end 1.215 2.491) (layer F.SilkS) (width 0.15))
(fp_line (start 1.215 -2.491) (end 1.215 -0.154) (layer F.SilkS) (width 0.15))
(fp_line (start 1.075 -2.499) (end 1.075 2.499) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole circle (at 2 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 15 "Net-(C17-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 thru_hole rect (at 0 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_ThroughHole.3dshapes/C_Radial_D5_L11_P2.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A7D9)
(at 39.5 34.5)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5934A59B)
(attr smd)
(fp_text reference C18 (at 0 1.9) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1u (at 0 -1.9) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 16 "Net-(C18-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 1 Earth))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A7DF)
(at 56 32 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59305CF8)
(attr smd)
(fp_text reference C19 (at 0 1.9 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.9 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 14 "Net-(C16-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A7E5)
(at 56 36.5 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59305D6F)
(attr smd)
(fp_text reference C20 (at 0 1.9 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.9 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 15 "Net-(C17-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A7EB)
(at 46 34 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5934A14D)
(attr smd)
(fp_text reference C21 (at 0 -1.9 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 1.9 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 17 "Net-(C21-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A7F1)
(at 42.5 32.5 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59349E35)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C22 (at 1.25 -1.75 90) (layer B.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1u (at 0 -1.9 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 18 "Net-(C22-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 1 Earth))
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A7F7)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(at 73 28 180)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59306354)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C23 (at -3.5 0.75 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 19 +12V))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A7FD)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(at 73 35.25 270)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59306303)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C24 (at 3.25 -0.25 270) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(fp_text value 100n (at 0 1.9 270) (layer F.Fab)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 20 -12V))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_THT:C_Radial_D8_L11.5_P3.5 (layer F.Cu) (tedit 0) (tstamp 5978A809)
(at 78.5 31 270)
(descr "Radial Electrolytic Capacitor Diameter 8mm x Length 11.5mm, Pitch 3.5mm")
(tags "Electrolytic Capacitor")
(path /59306550)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C26 (at 4.75 -4.5 270) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100u (at 1.75 5.3 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.75 0) (end 1.75 -4.3) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1.75 0) (end 1.75 -4.0375) (layer F.SilkS) (width 0.15))
(fp_circle (center 3.5 0) (end 3.5 -1) (layer F.SilkS) (width 0.15))
(fp_line (start 5.745 -0.2) (end 5.745 0.2) (layer F.SilkS) (width 0.15))
(fp_line (start 5.605 -1.067) (end 5.605 1.067) (layer F.SilkS) (width 0.15))
(fp_line (start 5.465 -1.483) (end 5.465 1.483) (layer F.SilkS) (width 0.15))
(fp_line (start 5.325 -1.794) (end 5.325 1.794) (layer F.SilkS) (width 0.15))
(fp_line (start 5.185 -2.05) (end 5.185 2.05) (layer F.SilkS) (width 0.15))
(fp_line (start 5.045 -2.268) (end 5.045 2.268) (layer F.SilkS) (width 0.15))
(fp_line (start 4.905 -2.459) (end 4.905 2.459) (layer F.SilkS) (width 0.15))
(fp_line (start 4.765 -2.629) (end 4.765 2.629) (layer F.SilkS) (width 0.15))
(fp_line (start 4.625 -2.781) (end 4.625 2.781) (layer F.SilkS) (width 0.15))
(fp_line (start 4.485 0.173) (end 4.485 2.919) (layer F.SilkS) (width 0.15))
(fp_line (start 4.485 -2.919) (end 4.485 -0.173) (layer F.SilkS) (width 0.15))
(fp_line (start 4.345 0.535) (end 4.345 3.044) (layer F.SilkS) (width 0.15))
(fp_line (start 4.345 -3.044) (end 4.345 -0.535) (layer F.SilkS) (width 0.15))
(fp_line (start 4.205 0.709) (end 4.205 3.158) (layer F.SilkS) (width 0.15))
(fp_line (start 4.205 -3.158) (end 4.205 -0.709) (layer F.SilkS) (width 0.15))
(fp_line (start 4.065 0.825) (end 4.065 3.262) (layer F.SilkS) (width 0.15))
(fp_line (start 4.065 -3.262) (end 4.065 -0.825) (layer F.SilkS) (width 0.15))
(fp_line (start 3.925 0.905) (end 3.925 3.357) (layer F.SilkS) (width 0.15))
(fp_line (start 3.925 -3.357) (end 3.925 -0.905) (layer F.SilkS) (width 0.15))
(fp_line (start 3.785 0.959) (end 3.785 3.444) (layer F.SilkS) (width 0.15))
(fp_line (start 3.785 -3.444) (end 3.785 -0.959) (layer F.SilkS) (width 0.15))
(fp_line (start 3.645 0.989) (end 3.645 3.523) (layer F.SilkS) (width 0.15))
(fp_line (start 3.645 -3.523) (end 3.645 -0.989) (layer F.SilkS) (width 0.15))
(fp_line (start 3.505 1) (end 3.505 3.594) (layer F.SilkS) (width 0.15))
(fp_line (start 3.505 -3.594) (end 3.505 -1) (layer F.SilkS) (width 0.15))
(fp_line (start 3.365 0.991) (end 3.365 3.659) (layer F.SilkS) (width 0.15))
(fp_line (start 3.365 -3.659) (end 3.365 -0.991) (layer F.SilkS) (width 0.15))
(fp_line (start 3.225 0.961) (end 3.225 3.718) (layer F.SilkS) (width 0.15))
(fp_line (start 3.225 -3.718) (end 3.225 -0.961) (layer F.SilkS) (width 0.15))
(fp_line (start 3.085 0.91) (end 3.085 3.771) (layer F.SilkS) (width 0.15))
(fp_line (start 3.085 -3.771) (end 3.085 -0.91) (layer F.SilkS) (width 0.15))
(fp_line (start 2.945 0.832) (end 2.945 3.817) (layer F.SilkS) (width 0.15))
(fp_line (start 2.945 -3.817) (end 2.945 -0.832) (layer F.SilkS) (width 0.15))
(fp_line (start 2.805 0.719) (end 2.805 3.858) (layer F.SilkS) (width 0.15))
(fp_line (start 2.805 -3.858) (end 2.805 -0.719) (layer F.SilkS) (width 0.15))
(fp_line (start 2.665 0.55) (end 2.665 3.894) (layer F.SilkS) (width 0.15))
(fp_line (start 2.665 -3.894) (end 2.665 -0.55) (layer F.SilkS) (width 0.15))
(fp_line (start 2.525 0.222) (end 2.525 3.924) (layer F.SilkS) (width 0.15))
(fp_line (start 2.525 -3.924) (end 2.525 -0.222) (layer F.SilkS) (width 0.15))
(fp_line (start 2.385 -3.949) (end 2.385 3.949) (layer F.SilkS) (width 0.15))
(fp_line (start 2.245 -3.969) (end 2.245 3.969) (layer F.SilkS) (width 0.15))
(fp_line (start 2.105 -3.984) (end 2.105 3.984) (layer F.SilkS) (width 0.15))
(fp_line (start 1.965 -3.994) (end 1.965 3.994) (layer F.SilkS) (width 0.15))
(fp_line (start 1.825 -3.999) (end 1.825 3.999) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole rect (at 0 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 2 thru_hole circle (at 3.5 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 20 -12V))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_ThroughHole.3dshapes/C_Radial_D8_L11.5_P3.5.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A80F)
(at 94 48.5)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59361C5D)
(attr smd)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference C27 (at 0 -1.5) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 21 "Net-(C27-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A815)
(at 92 51.5 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59361F8D)
(attr smd)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(fp_text reference C28 (at -3.47 0.45 90) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 1.9 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 21 "Net-(C27-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A81B)
(at 75.5 55 90)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /593775B9)
(attr smd)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(fp_text reference C29 (at 0 -1.9 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(fp_text value 10n (at 0 1.9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 22 "Net-(C29-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A821)
(at 85.95 56.5)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /593773D6)
(attr smd)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference C30 (at -3.5 0) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10n (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 23 "Net-(C30-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_THT:C_Radial_D5_L11_P2.5 (layer F.Cu) (tedit 0) (tstamp 5978A827)
(at 96 42.5 270)
(descr "Radial Electrolytic Capacitor Diameter 5mm x Length 11mm, Pitch 2.5mm")
(tags "Electrolytic Capacitor")
(path /5936D506)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(fp_text reference C31 (at 1 -4.25 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 22u (at 1.25 3.8 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.25 0) (end 1.25 -2.8) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1.25 0) (end 1.25 -2.5375) (layer F.SilkS) (width 0.15))
(fp_circle (center 2.5 0) (end 2.5 -0.9) (layer F.SilkS) (width 0.15))
(fp_line (start 3.705 -0.472) (end 3.705 0.472) (layer F.SilkS) (width 0.15))
(fp_line (start 3.565 -0.944) (end 3.565 0.944) (layer F.SilkS) (width 0.15))
(fp_line (start 3.425 -1.233) (end 3.425 1.233) (layer F.SilkS) (width 0.15))
(fp_line (start 3.285 0.44) (end 3.285 1.452) (layer F.SilkS) (width 0.15))
(fp_line (start 3.285 -1.452) (end 3.285 -0.44) (layer F.SilkS) (width 0.15))
(fp_line (start 3.145 0.628) (end 3.145 1.631) (layer F.SilkS) (width 0.15))
(fp_line (start 3.145 -1.631) (end 3.145 -0.628) (layer F.SilkS) (width 0.15))
(fp_line (start 3.005 0.745) (end 3.005 1.78) (layer F.SilkS) (width 0.15))
(fp_line (start 3.005 -1.78) (end 3.005 -0.745) (layer F.SilkS) (width 0.15))
(fp_line (start 2.865 0.823) (end 2.865 1.908) (layer F.SilkS) (width 0.15))
(fp_line (start 2.865 -1.908) (end 2.865 -0.823) (layer F.SilkS) (width 0.15))
(fp_line (start 2.725 0.871) (end 2.725 2.019) (layer F.SilkS) (width 0.15))
(fp_line (start 2.725 -2.019) (end 2.725 -0.871) (layer F.SilkS) (width 0.15))
(fp_line (start 2.585 0.896) (end 2.585 2.114) (layer F.SilkS) (width 0.15))
(fp_line (start 2.585 -2.114) (end 2.585 -0.896) (layer F.SilkS) (width 0.15))
(fp_line (start 2.445 0.898) (end 2.445 2.196) (layer F.SilkS) (width 0.15))
(fp_line (start 2.445 -2.196) (end 2.445 -0.898) (layer F.SilkS) (width 0.15))
(fp_line (start 2.305 0.879) (end 2.305 2.266) (layer F.SilkS) (width 0.15))
(fp_line (start 2.305 -2.266) (end 2.305 -0.879) (layer F.SilkS) (width 0.15))
(fp_line (start 2.165 0.835) (end 2.165 2.327) (layer F.SilkS) (width 0.15))
(fp_line (start 2.165 -2.327) (end 2.165 -0.835) (layer F.SilkS) (width 0.15))
(fp_line (start 2.025 0.764) (end 2.025 2.377) (layer F.SilkS) (width 0.15))
(fp_line (start 2.025 -2.377) (end 2.025 -0.764) (layer F.SilkS) (width 0.15))
(fp_line (start 1.885 0.657) (end 1.885 2.418) (layer F.SilkS) (width 0.15))
(fp_line (start 1.885 -2.418) (end 1.885 -0.657) (layer F.SilkS) (width 0.15))
(fp_line (start 1.745 0.49) (end 1.745 2.451) (layer F.SilkS) (width 0.15))
(fp_line (start 1.745 -2.451) (end 1.745 -0.49) (layer F.SilkS) (width 0.15))
(fp_line (start 1.605 0.095) (end 1.605 2.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1.605 -2.475) (end 1.605 -0.095) (layer F.SilkS) (width 0.15))
(fp_line (start 1.465 -2.491) (end 1.465 2.491) (layer F.SilkS) (width 0.15))
(fp_line (start 1.325 -2.499) (end 1.325 2.499) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole circle (at 2.5 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 thru_hole rect (at 0 0 270) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 24 "Net-(C31-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_ThroughHole.3dshapes/C_Radial_D5_L11_P2.5.wrl
(at (xyz 0.049213 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A82D)
(at 85 43.05 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5936ED37)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C32 (at -1.55 -2.25 270) (layer B.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.9 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 24 "Net-(C31-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 5978A833)
(at 101.97 56.18 180)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /593620C9)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C33 (at -0.03 -1.82 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 25 "Net-(C33-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A839)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(at 99.05 59.5)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59361D2F)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C34 (at 3.7 0) (layer B.SilkS)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(fp_text value 100n (at 0 -1.9) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 25 "Net-(C33-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 5978A83F)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(at 79.71 44.23 90)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5936EFE5)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C35 (at -0.02 -1.96 90) (layer B.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.9 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 26 "Net-(C35-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_THT:C_Radial_D5_L11_P2.5 (layer F.Cu) (tedit 0) (tstamp 5978A845)
(at 71.5 43.5 90)
(descr "Radial Electrolytic Capacitor Diameter 5mm x Length 11mm, Pitch 2.5mm")
(tags "Electrolytic Capacitor")
(path /5936E4FB)
(fp_text reference C36 (at 1.25 -3.8 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 22u (at 1.25 3.8 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 1.25 0) (end 1.25 -2.8) (layer F.CrtYd) (width 0.05))
(fp_circle (center 1.25 0) (end 1.25 -2.5375) (layer F.SilkS) (width 0.15))
(fp_circle (center 2.5 0) (end 2.5 -0.9) (layer F.SilkS) (width 0.15))
(fp_line (start 3.705 -0.472) (end 3.705 0.472) (layer F.SilkS) (width 0.15))
(fp_line (start 3.565 -0.944) (end 3.565 0.944) (layer F.SilkS) (width 0.15))
(fp_line (start 3.425 -1.233) (end 3.425 1.233) (layer F.SilkS) (width 0.15))
(fp_line (start 3.285 0.44) (end 3.285 1.452) (layer F.SilkS) (width 0.15))
(fp_line (start 3.285 -1.452) (end 3.285 -0.44) (layer F.SilkS) (width 0.15))
(fp_line (start 3.145 0.628) (end 3.145 1.631) (layer F.SilkS) (width 0.15))
(fp_line (start 3.145 -1.631) (end 3.145 -0.628) (layer F.SilkS) (width 0.15))
(fp_line (start 3.005 0.745) (end 3.005 1.78) (layer F.SilkS) (width 0.15))
(fp_line (start 3.005 -1.78) (end 3.005 -0.745) (layer F.SilkS) (width 0.15))
(fp_line (start 2.865 0.823) (end 2.865 1.908) (layer F.SilkS) (width 0.15))
(fp_line (start 2.865 -1.908) (end 2.865 -0.823) (layer F.SilkS) (width 0.15))
(fp_line (start 2.725 0.871) (end 2.725 2.019) (layer F.SilkS) (width 0.15))
(fp_line (start 2.725 -2.019) (end 2.725 -0.871) (layer F.SilkS) (width 0.15))
(fp_line (start 2.585 0.896) (end 2.585 2.114) (layer F.SilkS) (width 0.15))
(fp_line (start 2.585 -2.114) (end 2.585 -0.896) (layer F.SilkS) (width 0.15))
(fp_line (start 2.445 0.898) (end 2.445 2.196) (layer F.SilkS) (width 0.15))
(fp_line (start 2.445 -2.196) (end 2.445 -0.898) (layer F.SilkS) (width 0.15))
(fp_line (start 2.305 0.879) (end 2.305 2.266) (layer F.SilkS) (width 0.15))
(fp_line (start 2.305 -2.266) (end 2.305 -0.879) (layer F.SilkS) (width 0.15))
(fp_line (start 2.165 0.835) (end 2.165 2.327) (layer F.SilkS) (width 0.15))
(fp_line (start 2.165 -2.327) (end 2.165 -0.835) (layer F.SilkS) (width 0.15))
(fp_line (start 2.025 0.764) (end 2.025 2.377) (layer F.SilkS) (width 0.15))
(fp_line (start 2.025 -2.377) (end 2.025 -0.764) (layer F.SilkS) (width 0.15))
(fp_line (start 1.885 0.657) (end 1.885 2.418) (layer F.SilkS) (width 0.15))
(fp_line (start 1.885 -2.418) (end 1.885 -0.657) (layer F.SilkS) (width 0.15))
(fp_line (start 1.745 0.49) (end 1.745 2.451) (layer F.SilkS) (width 0.15))
(fp_line (start 1.745 -2.451) (end 1.745 -0.49) (layer F.SilkS) (width 0.15))
(fp_line (start 1.605 0.095) (end 1.605 2.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1.605 -2.475) (end 1.605 -0.095) (layer F.SilkS) (width 0.15))
(fp_line (start 1.465 -2.491) (end 1.465 2.491) (layer F.SilkS) (width 0.15))
(fp_line (start 1.325 -2.499) (end 1.325 2.499) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole circle (at 2.5 0 90) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 26 "Net-(C35-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.3 1.3) (drill 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Capacitors_ThroughHole.3dshapes/C_Radial_D5_L11_P2.5.wrl
(at (xyz 0.049213 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(module Diodes_SMD:SOD-123 (layer F.Cu) (tedit 58645DC7) (tstamp 5978A84B)
(at 32.71 54.71 90)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr SOD-123)
(tags SOD-123)
(path /5935E5FB)
(attr smd)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(fp_text reference D1 (at 0 -2 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SK15-DIO (at 0 2.1 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2.25 -1) (end 1.65 -1) (layer F.SilkS) (width 0.12))
(fp_line (start -2.25 1) (end 1.65 1) (layer F.SilkS) (width 0.12))
(fp_line (start -2.35 -1.15) (end -2.35 1.15) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.35 1.15) (end -2.35 1.15) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.35 -1.15) (end 2.35 1.15) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.35 -1.15) (end 2.35 -1.15) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.4 -0.9) (end 1.4 -0.9) (layer F.Fab) (width 0.1))
(fp_line (start 1.4 -0.9) (end 1.4 0.9) (layer F.Fab) (width 0.1))
(fp_line (start 1.4 0.9) (end -1.4 0.9) (layer F.Fab) (width 0.1))
(fp_line (start -1.4 0.9) (end -1.4 -0.9) (layer F.Fab) (width 0.1))
(fp_line (start -0.75 0) (end -0.35 0) (layer F.Fab) (width 0.1))
(fp_line (start -0.35 0) (end -0.35 -0.55) (layer F.Fab) (width 0.1))
(fp_line (start -0.35 0) (end -0.35 0.55) (layer F.Fab) (width 0.1))
(fp_line (start -0.35 0) (end 0.25 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.25 -0.4) (end 0.25 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.25 0.4) (end -0.35 0) (layer F.Fab) (width 0.1))
(fp_line (start 0.25 0) (end 0.75 0) (layer F.Fab) (width 0.1))
(fp_line (start -2.25 -1) (end -2.25 1) (layer F.SilkS) (width 0.12))
(pad 2 smd rect (at 1.65 0 90) (size 0.9 1.2) (layers F.Cu F.Paste F.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 1 Earth))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(pad 1 smd rect (at -1.65 0 90) (size 0.9 1.2) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 27 "Net-(D1-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model ${KISYS3DMOD}/Diodes_SMD.3dshapes/SOD-123.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module tht:AMPHENOL-ACJS-HHDR (layer F.Cu) (tedit 59397A20) (tstamp 5978A88B)
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(at 104.15 27)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(path /593770B0)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference J4 (at 6.85 8.8) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value JACK_TRS_6PINS (at -0.5 1.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -13.8 -8) (end 10.6 -8) (layer F.SilkS) (width 0.15))
(fp_line (start -13.8 8) (end -13.8 -8) (layer F.SilkS) (width 0.15))
(fp_line (start 10.6 8) (end -13.8 8) (layer F.SilkS) (width 0.15))
(fp_line (start 14 -5.7) (end 14 5.7) (layer F.SilkS) (width 0.15))
(fp_line (start 10.6 5.7) (end 14 5.7) (layer F.SilkS) (width 0.15))
(fp_line (start 10.6 -8) (end 10.6 8) (layer F.SilkS) (width 0.15))
(fp_line (start 10.6 -5.7) (end 14 -5.7) (layer F.SilkS) (width 0.15))
(pad 4 thru_hole circle (at 6.35 5.7) (size 2.5 2.5) (drill 1.4) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 32 "Net-(J4-Pad4)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 6 thru_hole circle (at 0 5.7) (size 2.5 2.5) (drill 1.4) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 33 "Net-(J4-Pad6)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 5 thru_hole circle (at -6.35 5.7) (size 2.5 2.5) (drill 1.4) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 34 "Net-(J4-Pad5)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 2 thru_hole circle (at -6.35 -5.7) (size 2.5 2.5) (drill 1.4) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 35 "Net-(J4-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 3 thru_hole circle (at 0 -5.7) (size 2.5 2.5) (drill 1.4) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 36 "Net-(J4-Pad3)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 thru_hole circle (at 6.35 -5.7) (size 2.5 2.5) (drill 1.4) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
(module "Relays_THT:Relay_DPDT_IM0(3,6,7)NS" (layer F.Cu) (tedit 55FAC2CB) (tstamp 5978A897)
(at 47.1 47 270)
(descr "IM Signal Relay, DPDT, IM0(3,6,7)NS, narrow footprint")
(tags "Relay DPDT IM-relay")
(path /59346B99)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(fp_text reference K1 (at 1.5 -1.9 270) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Relais-2 (at 1.95 10.25 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 4.597 -1.2065) (end -1.372 -1.2065) (layer F.SilkS) (width 0.15))
(fp_line (start -1.4 -1.2) (end -1.4 8.8) (layer F.SilkS) (width 0.15))
(fp_line (start 4.597 8.8265) (end -1.372 8.8265) (layer F.SilkS) (width 0.15))
(fp_line (start 4.6 -1.2) (end 4.6 8.8) (layer F.SilkS) (width 0.15))
(fp_line (start -1.65 -1.45) (end 4.85 -1.45) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.65 9.05) (end -1.65 -1.45) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.85 9.05) (end -1.65 9.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.85 -1.45) (end 4.85 9.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.565 1.016) (end 2.565 2.032) (layer F.SilkS) (width 0.15))
(fp_line (start 0.66 2.032) (end 2.565 2.032) (layer F.SilkS) (width 0.15))
(fp_line (start 0.66 1.016) (end 0.66 2.032) (layer F.SilkS) (width 0.15))
(fp_line (start 2.565 1.016) (end 0.66 1.016) (layer F.SilkS) (width 0.15))
(fp_line (start 3.2 1.524) (end 2.565 1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 3.2 0.889) (end 3.2 1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 0 1.524) (end 0.66 1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 0 0.889) (end 0 1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 2.184 1.016) (end 1.549 2.032) (layer F.SilkS) (width 0.15))
(pad 5 thru_hole circle (at 3.2 7.6 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 63 "Net-(C46-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 6 thru_hole circle (at 3.2 5.4 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 37 "Net-(K1-Pad6)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 7 thru_hole circle (at 3.2 3.2 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 11 /RUSB))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 4 thru_hole circle (at 0 7.6 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 61 "Net-(C45-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 3 thru_hole circle (at 0 5.4 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 38 "Net-(K1-Pad3)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 2 thru_hole circle (at 0 3.2 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 7 /LUSB))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 thru_hole circle (at 0 0 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 27 "Net-(D1-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 8 thru_hole circle (at 3.2 0 180) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 66 "Net-(K1-Pad8)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model "Relays_ThroughHole.3dshapes/Relay_DPDT_IM0(3,6,7)NS.wrl"
(at (xyz 0.0625 -0.15 -0.128))
(scale (xyz 0.39 0.39 0.39))
(rotate (xyz 180 0 90))
)
)
(module "Relays_THT:Relay_DPDT_IM0(3,6,7)NS" (layer F.Cu) (tedit 55FAC2CB) (tstamp 5978A8A3)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(at 27.75 50.25 90)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "IM Signal Relay, DPDT, IM0(3,6,7)NS, narrow footprint")
(tags "Relay DPDT IM-relay")
(path /5934743F)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(fp_text reference K2 (at 1.5 9.65 90) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(fp_text value Relais-2 (at 1.95 10.25 90) (layer F.Fab)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 4.597 -1.2065) (end -1.372 -1.2065) (layer F.SilkS) (width 0.15))
(fp_line (start -1.4 -1.2) (end -1.4 8.8) (layer F.SilkS) (width 0.15))
(fp_line (start 4.597 8.8265) (end -1.372 8.8265) (layer F.SilkS) (width 0.15))
(fp_line (start 4.6 -1.2) (end 4.6 8.8) (layer F.SilkS) (width 0.15))
(fp_line (start -1.65 -1.45) (end 4.85 -1.45) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.65 9.05) (end -1.65 -1.45) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.85 9.05) (end -1.65 9.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.85 -1.45) (end 4.85 9.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.565 1.016) (end 2.565 2.032) (layer F.SilkS) (width 0.15))
(fp_line (start 0.66 2.032) (end 2.565 2.032) (layer F.SilkS) (width 0.15))
(fp_line (start 0.66 1.016) (end 0.66 2.032) (layer F.SilkS) (width 0.15))
(fp_line (start 2.565 1.016) (end 0.66 1.016) (layer F.SilkS) (width 0.15))
(fp_line (start 3.2 1.524) (end 2.565 1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 3.2 0.889) (end 3.2 1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 0 1.524) (end 0.66 1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 0 0.889) (end 0 1.524) (layer F.SilkS) (width 0.15))
(fp_line (start 2.184 1.016) (end 1.549 2.032) (layer F.SilkS) (width 0.15))
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(pad 5 thru_hole circle (at 3.2 7.6) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 31 GNDA))
(pad 6 thru_hole circle (at 3.2 5.4) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 13 GNDPWR))
(pad 7 thru_hole circle (at 3.2 3.2) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 1 Earth))
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(pad 4 thru_hole circle (at 0 7.6) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 31 GNDA))
(pad 3 thru_hole circle (at 0 5.4) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 13 GNDPWR))
(pad 2 thru_hole circle (at 0 3.2) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 1 Earth))
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(pad 1 thru_hole circle (at 0 0) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 27 "Net-(D1-Pad1)"))
(pad 8 thru_hole circle (at 3.2 0) (size 1.5 1.5) (drill 0.65) (layers *.Cu *.Mask)
(net 67 "Net-(K2-Pad8)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model "Relays_ThroughHole.3dshapes/Relay_DPDT_IM0(3,6,7)NS.wrl"
(at (xyz 0.0625 -0.15 -0.128))
(scale (xyz 0.39 0.39 0.39))
(rotate (xyz 180 0 90))
)
)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(module Resistors_SMD:R_1812_HandSoldering (layer F.Cu) (tedit 58307D36) (tstamp 5978A8A9)
(at 23.5 38.5)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Resistor SMD 1812, hand soldering, Panasonic (see ERJ12)")
(tags "resistor 1812")
(path /5934B57E)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference L1 (at 0 2.75) (layer F.SilkS)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(effects (font (size 1 1) (thickness 0.15)))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(fp_text value 47u (at 0 3.175) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(fp_line (start -1.7272 -1.8796) (end 1.7272 -1.8796) (layer F.SilkS) (width 0.15))
(fp_line (start -1.7272 1.8796) (end 1.7272 1.8796) (layer F.SilkS) (width 0.15))
(fp_line (start -5.4356 2.2352) (end -5.4356 -2.2352) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.4356 2.2352) (end -5.4356 2.2352) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.4356 -2.2352) (end 5.4356 2.2352) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.4356 -2.2352) (end 5.4356 -2.2352) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.25 -1.6) (end 2.25 -1.6) (layer F.Fab) (width 0.1))
(fp_line (start 2.25 -1.6) (end 2.25 1.6) (layer F.Fab) (width 0.1))
(fp_line (start 2.25 1.6) (end -2.25 1.6) (layer F.Fab) (width 0.1))
(fp_line (start -2.25 1.6) (end -2.25 -1.6) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 3.4036 0) (size 3.5 3.5) (layers F.Cu F.Paste F.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 2 "Net-(C1-Pad1)"))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(pad 1 smd rect (at -3.4036 0) (size 3.5 3.5) (layers F.Cu F.Paste F.Mask)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(net 3 +5V))
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58307AEF) (tstamp 5978A8C1)
(at 90.86 37.62 270)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /59360759)
(attr smd)
(fp_text reference L5 (at 0 1.9 270) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 10u (at 0 -1.9 270) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 270) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 21 "Net-(C27-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0 270) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 19 +12V))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_1210_HandSoldering (layer F.Cu) (tedit 58307C8D) (tstamp 5978A8C7)
(at 86 36.5 270)
(descr "Resistor SMD 1210, hand soldering")
(tags "resistor 1210")
(path /5936CC12)
(attr smd)
(fp_text reference L6 (at 0 -2.7 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 2.7 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1 -1.475) (end 1 -1.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1 1.475) (end -1 1.475) (layer F.SilkS) (width 0.15))
(fp_line (start 3.3 -1.6) (end 3.3 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.6) (end -3.3 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 1.6) (end 3.3 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.6) (end 3.3 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.25) (end 1.6 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 -1.25) (end 1.6 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 1.25) (end -1.6 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.6 1.25) (end -1.6 -1.25) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 2 0 270) (size 2 2.5) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 24 "Net-(C31-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -2 0 270) (size 2 2.5) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 19 +12V))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_1210_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58307AEF) (tstamp 5978A8CD)
(at 98.044 55.88 90)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /59360894)
(attr smd)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(fp_text reference L7 (at 0 1.9 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(fp_text value 10u (at 0 -1.9 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 20 -12V))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 25 "Net-(C33-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_1210_HandSoldering (layer F.Cu) (tedit 58307C8D) (tstamp 5978A8D3)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(at 77.41 38.95 180)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Resistor SMD 1210, hand soldering")
(tags "resistor 1210")
(path /5936CF7D)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference L8 (at -4.09 0.95 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(fp_text value 1u (at 0 2.7 180) (layer F.Fab)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1 -1.475) (end 1 -1.475) (layer F.SilkS) (width 0.15))
(fp_line (start 1 1.475) (end -1 1.475) (layer F.SilkS) (width 0.15))
(fp_line (start 3.3 -1.6) (end 3.3 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.6) (end -3.3 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 1.6) (end 3.3 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.6) (end 3.3 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.25) (end 1.6 -1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 -1.25) (end 1.6 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 1.25) (end -1.6 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.6 1.25) (end -1.6 -1.25) (layer F.Fab) (width 0.1))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(pad 2 smd rect (at 2 0 180) (size 2 2.5) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 20 -12V))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(pad 1 smd rect (at -2 0 180) (size 2 2.5) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 26 "Net-(C35-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_1210_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58307AEF) (tstamp 5978A8D9)
(at 25 29.5 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5934E5F3)
(attr smd)
(fp_text reference R1 (at 0 1.9 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1k5 (at 0 -1.9 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 29 /D+))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 6 +3V3))
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A8DF)
(at 25 28.5)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5934E1D2)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R2 (at 0 1.75) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 22 (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 39 "Net-(R2-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 29 /D+))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A8E5)
(at 25 26.5 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5934E099)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R3 (at 0 1.75 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 22 (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 30 /D-))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 40 "Net-(R3-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A8EB)
(at 37 38 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5934FAAF)
(attr smd)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(fp_text reference R4 (at -2.25 1.75 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 16 (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 64 "Net-(C47-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 8 "Net-(C12-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A8F1)
(at 39.5 24.5)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /593487DE)
(attr smd)
(fp_text reference R5 (at 0 -1.9) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1M (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 10 "Net-(C14-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 5 "Net-(C5-Pad1)"))
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A8F7)
(at 42 38 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5934ED7E)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R6 (at -3.25 0 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 16 (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 9 "Net-(C13-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 12 "Net-(C15-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A8FD)
(at 94.5 58.5)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5938A1C1)
(attr smd)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference R7 (at 0 1.7) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 2k (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 41 "Net-(R7-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 42 "Net-(R11-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58307AEF) (tstamp 5978A903)
(at 94.24 56.44 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5938AA58)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R8 (at 0.24 1.69 180) (layer B.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1k (at 0 -1.9 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 41 "Net-(R7-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A909)
(at 98.5 48)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /59389142)
(attr smd)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(fp_text reference R9 (at 0.46 -1.6) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 2k (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 43 "Net-(R10-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 44 "Net-(R12-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58307AEF) (tstamp 5978A90F)
(at 98.5 48.5)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /593893F1)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R10 (at 0 -2) (layer B.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1k (at 0 -1.9) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 43 "Net-(R10-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_1206_HandSoldering (layer F.Cu) (tedit 58307C0D) (tstamp 5978A915)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(at 78.47 58.42)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Resistor SMD 1206, hand soldering")
(tags "resistor 1206")
(path /5937135E)
(attr smd)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference R11 (at -0.1 2) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 50 (at 0 2.3) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1 -1.075) (end 1 -1.075) (layer F.SilkS) (width 0.15))
(fp_line (start 1 1.075) (end -1 1.075) (layer F.SilkS) (width 0.15))
(fp_line (start 3.3 -1.2) (end 3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end -3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 1.2) (end 3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end 3.3 -1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1))
(fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 2 0) (size 2 1.7) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 42 "Net-(R11-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -2 0) (size 2 1.7) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 22 "Net-(C29-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_1206_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_1206_HandSoldering (layer F.Cu) (tedit 58307C0D) (tstamp 5978A91B)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(at 86.96 58.78)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Resistor SMD 1206, hand soldering")
(tags "resistor 1206")
(path /593721CE)
(attr smd)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference R12 (at 0 2) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 50 (at 0 2.3) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1 -1.075) (end 1 -1.075) (layer F.SilkS) (width 0.15))
(fp_line (start 1 1.075) (end -1 1.075) (layer F.SilkS) (width 0.15))
(fp_line (start 3.3 -1.2) (end 3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end -3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 1.2) (end 3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end 3.3 -1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1))
(fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 2 0) (size 2 1.7) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 44 "Net-(R12-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -2 0) (size 2 1.7) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 23 "Net-(C30-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_1206_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A921)
(at 90 49 90)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5938E18E)
(attr smd)
Layout: fix silkscreen position
2017-07-27 20:14:20 +02:00
(fp_text reference R13 (at -4.09 -0.03 90) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 45 "Net-(R13-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A927)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(at 72.25 51.75 270)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5938D7A2)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R14 (at -0.5 2 270) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text value 1k (at 0 1.9 270) (layer F.Fab)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(pad 2 smd rect (at 1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(pad 1 smd rect (at -1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 46 "Net-(R14-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A92D)
(at 74 47.5 90)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5938C14D)
(attr smd)
(fp_text reference R15 (at 0 -1.9 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 47 "Net-(R15-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 46 "Net-(R14-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 5978A933)
(at 91 44.5 270)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5938BE81)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R16 (at 0.25 -1.75 270) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.9 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 45 "Net-(R13-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -1.1 0 270) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 48 "Net-(R16-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(module Resistors_SMD:R_1206_HandSoldering (layer F.Cu) (tedit 58307C0D) (tstamp 5978A939)
(at 90.75 38.5 270)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Resistor SMD 1206, hand soldering")
(tags "resistor 1206")
(path /59377722)
(attr smd)
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(fp_text reference R17 (at 0 -2.3 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(fp_text value 5 (at 0 2.3 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(fp_line (start -1 -1.075) (end 1 -1.075) (layer F.SilkS) (width 0.15))
(fp_line (start 1 1.075) (end -1 1.075) (layer F.SilkS) (width 0.15))
(fp_line (start 3.3 -1.2) (end 3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end -3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 1.2) (end 3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end 3.3 -1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1))
(fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 2 0 270) (size 2 1.7) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 47 "Net-(R15-Pad2)"))
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(pad 1 smd rect (at -2 0 270) (size 2 1.7) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 35 "Net-(J4-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_1206_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_1206_HandSoldering (layer F.Cu) (tedit 58307C0D) (tstamp 5978A93F)
(at 98.19 37.09 180)
(descr "Resistor SMD 1206, hand soldering")
(tags "resistor 1206")
(path /59377880)
(attr smd)
fix silkscreen
2017-08-28 23:00:45 +02:00
(fp_text reference R18 (at 4.69 0.84 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 5 (at 0 2.3 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1 -1.075) (end 1 -1.075) (layer F.SilkS) (width 0.15))
(fp_line (start 1 1.075) (end -1 1.075) (layer F.SilkS) (width 0.15))
(fp_line (start 3.3 -1.2) (end 3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end -3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 1.2) (end 3.3 1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.3 -1.2) (end 3.3 -1.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -0.8) (end 1.6 -0.8) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 -0.8) (end 1.6 0.8) (layer F.Fab) (width 0.1))
(fp_line (start 1.6 0.8) (end -1.6 0.8) (layer F.Fab) (width 0.1))
(fp_line (start -1.6 0.8) (end -1.6 -0.8) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 2 0 180) (size 2 1.7) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 48 "Net-(R16-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -2 0 180) (size 2 1.7) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 36 "Net-(J4-Pad3)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Resistors_SMD.3dshapes/R_1206_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module tht:ALPS-RK09L12B0 (layer F.Cu) (tedit 5978937F) (tstamp 5978A978)
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(at 107.5 48)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(path /5935E896)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference RV1 (at 1.5 -6 180) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value "ALPS 50k" (at 4.75 -6) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 7.5 -5.35) (end -2.25 -5.35) (layer F.SilkS) (width 0.15))
(fp_line (start 12.25 4.5) (end 12.5 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12 4.25) (end 12.25 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 11.75 4.5) (end 12 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 11.5 4.25) (end 11.75 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 11.25 4.5) (end 11.5 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 11 4.25) (end 11.25 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 10.75 4.5) (end 11 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 10.5 4.25) (end 10.75 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 10.25 4.5) (end 10.5 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 10 4.25) (end 10.25 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 9.75 4.5) (end 10 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 9.5 4.25) (end 9.75 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 9.25 4.5) (end 9.5 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 9 4.25) (end 9.25 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 8.75 4.5) (end 9 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 8.5 4.25) (end 8.75 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 8.25 4.5) (end 8.5 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 8 4.25) (end 8.25 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 7.75 4.5) (end 8 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 7.5 4.25) (end 7.75 4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 7.75 -4.5) (end 7.5 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12.25 -4.5) (end 12.5 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12 -4.25) (end 12.25 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 11.75 -4.5) (end 12 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 11.5 -4.25) (end 11.75 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 11.25 -4.5) (end 11.5 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 11 -4.25) (end 11.25 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 10.75 -4.5) (end 11 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 10.5 -4.25) (end 10.75 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 10.25 -4.5) (end 10.5 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 10 -4.25) (end 10.25 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 9.75 -4.5) (end 10 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 9.5 -4.25) (end 9.75 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 9.25 -4.5) (end 9.5 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 9 -4.25) (end 9.25 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 8.75 -4.5) (end 9 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 8.5 -4.25) (end 8.75 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 8.25 -4.5) (end 8.5 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 8 -4.25) (end 8.25 -4.5) (layer F.SilkS) (width 0.15))
(fp_line (start 8.25 -4.5) (end 8 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 7.75 -4.5) (end 8 -4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 12.5 -4.25) (end 12.5 4.25) (layer F.SilkS) (width 0.15))
(fp_line (start 7.5 -5.35) (end 7.5 5.35) (layer F.SilkS) (width 0.15))
(fp_line (start 7.5 5.35) (end -2.25 5.35) (layer F.SilkS) (width 0.15))
(pad 12 thru_hole circle (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 58 "Net-(R24-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 11 thru_hole circle (at 0 2.5) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 13 thru_hole circle (at 0 -2.5) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 37 "Net-(K1-Pad6)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 21 thru_hole circle (at 2.5 2.5) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 22 thru_hole circle (at 2.5 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 56 "Net-(R23-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 23 thru_hole circle (at 2.5 -2.5) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 38 "Net-(K1-Pad3)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 30 thru_hole rect (at -3.3 -4.75) (size 1.8 2.5) (drill oval 1.1 1.8) (layers *.Cu *.Mask))
(pad 30 thru_hole rect (at -3.3 4.75) (size 1.8 2.5) (drill oval 1.1 1.8) (layers *.Cu *.Mask))
)
(module Housings_SSOP:SSOP-28_5.3x10.2mm_Pitch0.65mm (layer F.Cu) (tedit 54130A77) (tstamp 5978A9A7)
(at 39.5 31)
(descr "28-Lead Plastic Shrink Small Outline (SS)-5.30 mm Body [SSOP] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SSOP 0.65")
(path /59348397)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference U1 (at 4.5 -6.25) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value PCM2704 (at 0 6.25) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2.875 -4.75) (end -4.475 -4.75) (layer F.SilkS) (width 0.15))
(fp_line (start -2.875 5.325) (end 2.875 5.325) (layer F.SilkS) (width 0.15))
(fp_line (start -2.875 -5.325) (end 2.875 -5.325) (layer F.SilkS) (width 0.15))
(fp_line (start -2.875 5.325) (end -2.875 4.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2.875 5.325) (end 2.875 4.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2.875 -5.325) (end 2.875 -4.675) (layer F.SilkS) (width 0.15))
(fp_line (start -2.875 -5.325) (end -2.875 -4.75) (layer F.SilkS) (width 0.15))
(fp_line (start -4.75 5.5) (end 4.75 5.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.75 -5.5) (end 4.75 -5.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.75 -5.5) (end 4.75 5.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.75 -5.5) (end -4.75 5.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.65 -4.1) (end -1.65 -5.1) (layer F.Fab) (width 0.15))
(fp_line (start -2.65 5.1) (end -2.65 -4.1) (layer F.Fab) (width 0.15))
(fp_line (start 2.65 5.1) (end -2.65 5.1) (layer F.Fab) (width 0.15))
(fp_line (start 2.65 -5.1) (end 2.65 5.1) (layer F.Fab) (width 0.15))
(fp_line (start -1.65 -5.1) (end 2.65 -5.1) (layer F.Fab) (width 0.15))
(pad 28 smd rect (at 3.6 -4.225) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 10 "Net-(C14-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 27 smd rect (at 3.6 -3.575) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 69 /SSPND))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 26 smd rect (at 3.6 -2.925) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 6 +3V3))
(pad 25 smd rect (at 3.6 -2.275) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 6 +3V3))
(pad 24 smd rect (at 3.6 -1.625) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 49 "Net-(TP1-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 23 smd rect (at 3.6 -0.975) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 50 "Net-(TP2-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 22 smd rect (at 3.6 -0.325) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 51 "Net-(TP3-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 21 smd rect (at 3.6 0.325) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 6 +3V3))
(pad 20 smd rect (at 3.6 0.975) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 18 "Net-(C22-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 19 smd rect (at 3.6 1.625) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 18 smd rect (at 3.6 2.275) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 17 "Net-(C21-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 17 smd rect (at 3.6 2.925) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 16 smd rect (at 3.6 3.575) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 16 "Net-(C18-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 15 smd rect (at 3.6 4.225) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 12 "Net-(C15-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 14 smd rect (at -3.6 4.225) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 64 "Net-(C47-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 13 smd rect (at -3.6 3.575) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 4 "Net-(C4-Pad2)"))
(pad 12 smd rect (at -3.6 2.925) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 11 smd rect (at -3.6 2.275) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 10 smd rect (at -3.6 1.625) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 2 "Net-(C1-Pad1)"))
(pad 9 smd rect (at -3.6 0.975) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 39 "Net-(R2-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 8 smd rect (at -3.6 0.325) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 40 "Net-(R3-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 7 smd rect (at -3.6 -0.325) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 6 +3V3))
(pad 6 smd rect (at -3.6 -0.975) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 1 Earth))
(pad 5 smd rect (at -3.6 -1.625) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 52 "Net-(U1-Pad5)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 4 smd rect (at -3.6 -2.275) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 6 +3V3))
(pad 3 smd rect (at -3.6 -2.925) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 68 "Net-(R25-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 2 smd rect (at -3.6 -3.575) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 53 "Net-(U1-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -3.6 -4.225) (size 1.75 0.45) (layers F.Cu F.Paste F.Mask)
(net 5 "Net-(C5-Pad1)"))
(model Housings_SSOP.3dshapes/SSOP-28_5.3x10.2mm_Pitch0.65mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Housings_SOIC:SOIC-8_3.9x4.9mm_Pitch1.27mm (layer F.Cu) (tedit 54130A77) (tstamp 5978A9C0)
(at 96 53.5 90)
(descr "8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
(path /5935FD14)
(attr smd)
Layout: Fix silkscreen positions
2017-07-27 19:58:10 +02:00
(fp_text reference U3 (at 0 3.6 90) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value OPA2134 (at 0 3.5 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2.075 -2.525) (end -3.475 -2.525) (layer F.SilkS) (width 0.15))
(fp_line (start -2.075 2.575) (end 2.075 2.575) (layer F.SilkS) (width 0.15))
(fp_line (start -2.075 -2.575) (end 2.075 -2.575) (layer F.SilkS) (width 0.15))
(fp_line (start -2.075 2.575) (end -2.075 2.43) (layer F.SilkS) (width 0.15))
(fp_line (start 2.075 2.575) (end 2.075 2.43) (layer F.SilkS) (width 0.15))
(fp_line (start 2.075 -2.575) (end 2.075 -2.43) (layer F.SilkS) (width 0.15))
(fp_line (start -2.075 -2.575) (end -2.075 -2.525) (layer F.SilkS) (width 0.15))
(fp_line (start -3.75 2.75) (end 3.75 2.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.75 -2.75) (end 3.75 -2.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.75 -2.75) (end 3.75 2.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.75 -2.75) (end -3.75 2.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.95 -1.45) (end -0.95 -2.45) (layer F.Fab) (width 0.15))
(fp_line (start -1.95 2.45) (end -1.95 -1.45) (layer F.Fab) (width 0.15))
(fp_line (start 1.95 2.45) (end -1.95 2.45) (layer F.Fab) (width 0.15))
(fp_line (start 1.95 -2.45) (end 1.95 2.45) (layer F.Fab) (width 0.15))
(fp_line (start -0.95 -2.45) (end 1.95 -2.45) (layer F.Fab) (width 0.15))
(pad 8 smd rect (at 2.7 -1.905 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 21 "Net-(C27-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 7 smd rect (at 2.7 -0.635 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 44 "Net-(R12-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 6 smd rect (at 2.7 0.635 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 43 "Net-(R10-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 5 smd rect (at 2.7 1.905 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 59 "Net-(R24-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 4 smd rect (at -2.7 1.905 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 25 "Net-(C33-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 3 smd rect (at -2.7 0.635 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 57 "Net-(R23-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 2 smd rect (at -2.7 -0.635 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 41 "Net-(R7-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -2.7 -1.905 90) (size 1.55 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 42 "Net-(R11-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Housings_SOIC.3dshapes/SOIC-8_3.9x4.9mm_Pitch1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(module smd:SOIC-20W_ThermalPad (layer F.Cu) (tedit 59D3B7C6) (tstamp 5978A9E9)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(at 82.8 47.555)
(descr "20-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
(path /5936C2F8)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference U4 (at 0 7.445) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TPA6120 (at 0 7.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -3.875 -6.325) (end -5.675 -6.325) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 6.575) (end 3.875 6.575) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 -6.575) (end 3.875 -6.575) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 6.575) (end -3.875 6.24) (layer F.SilkS) (width 0.15))
(fp_line (start 3.875 6.575) (end 3.875 6.24) (layer F.SilkS) (width 0.15))
(fp_line (start 3.875 -6.575) (end 3.875 -6.24) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 -6.575) (end -3.875 -6.325) (layer F.SilkS) (width 0.15))
(fp_line (start -5.95 6.75) (end 5.95 6.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.95 -6.75) (end 5.95 -6.75) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.95 -6.75) (end 5.95 6.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.95 -6.75) (end -5.95 6.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.75 -5.4) (end -2.75 -6.4) (layer F.Fab) (width 0.15))
(fp_line (start -3.75 6.4) (end -3.75 -5.4) (layer F.Fab) (width 0.15))
(fp_line (start 3.75 6.4) (end -3.75 6.4) (layer F.Fab) (width 0.15))
(fp_line (start 3.75 -6.4) (end 3.75 6.4) (layer F.Fab) (width 0.15))
(fp_line (start -2.75 -6.4) (end 3.75 -6.4) (layer F.Fab) (width 0.15))
(pad 20 smd rect (at 4.7 -5.715) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 26 "Net-(C35-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 19 smd rect (at 4.7 -4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 48 "Net-(R16-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 18 smd rect (at 4.7 -3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 24 "Net-(C31-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 17 smd rect (at 4.7 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 23 "Net-(C30-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 16 smd rect (at 4.7 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 45 "Net-(R13-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 15 smd rect (at 4.7 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 14 smd rect (at 4.7 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 13 smd rect (at 4.7 3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 12 smd rect (at 4.7 4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 11 smd rect (at 4.7 5.715) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 10 smd rect (at -4.7 5.715) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 9 smd rect (at -4.7 4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 8 smd rect (at -4.7 3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 7 smd rect (at -4.7 1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 6 smd rect (at -4.7 0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at -4.7 -0.635) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 46 "Net-(R14-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 4 smd rect (at -4.7 -1.905) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 22 "Net-(C29-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 3 smd rect (at -4.7 -3.175) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 24 "Net-(C31-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 2 smd rect (at -4.7 -4.445) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 47 "Net-(R15-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -4.7 -5.715) (size 1.95 0.6) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 26 "Net-(C35-Pad2)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 21 smd rect (at 0 0) (size 3 4) (layers F.Cu F.Paste F.Mask)
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(net 13 GNDPWR) (zone_connect 2))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Housings_SOIC.3dshapes/SOIC-20_7.5x12.8mm_Pitch1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Crystals:Crystal_HC49-SD_SMD (layer F.Cu) (tedit 0) (tstamp 5978A9EF)
(at 39.5 21)
(descr "Crystal Quarz HC49-SD SMD")
(tags "Crystal Quarz HC49-SD SMD")
(path /59348602)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference Y1 (at -0.05 -1) (layer F.SilkS)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 12MHz (at 2.54 5.08) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -5.84962 -2.49936) (end -5.84962 -1.651) (layer F.SilkS) (width 0.15))
(fp_line (start -5.84962 2.49936) (end -5.84962 1.651) (layer F.SilkS) (width 0.15))
(fp_line (start 5.84962 -2.49936) (end 5.84962 -1.651) (layer F.SilkS) (width 0.15))
(fp_line (start 5.84962 2.49936) (end 5.84962 1.651) (layer F.SilkS) (width 0.15))
(fp_line (start 5.84962 -2.49936) (end -5.84962 -2.49936) (layer F.SilkS) (width 0.15))
(fp_line (start -5.84962 2.49936) (end 5.84962 2.49936) (layer F.SilkS) (width 0.15))
(fp_circle (center 0 0) (end 0.14986 0.0508) (layer F.Adhes) (width 0.381))
(fp_circle (center 0 0) (end 0.50038 0) (layer F.Adhes) (width 0.381))
(fp_circle (center 0 0) (end 0.8509 0) (layer F.Adhes) (width 0.381))
(pad 2 smd rect (at 4.84886 0) (size 5.6007 2.10058) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 10 "Net-(C14-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(pad 1 smd rect (at -4.84886 0) (size 5.6007 2.10058) (layers F.Cu F.Paste F.Mask)
(net 5 "Net-(C5-Pad1)"))
)
(module Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm (layer F.Cu) (tedit 5862ED52) (tstamp 5978B3F5)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(at 50.5 25)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5976273D)
(fp_text reference TP1 (at 0 -2.39) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TEST (at 0 2.39) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.6 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.6 1.6) (end 1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 1.6) (end 1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.6) (end -1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.39 -1.39) (end 0 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 0) (end -1.39 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.27) (end -1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.39) (end 1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.39) (end 1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.27) (end -1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 49 "Net-(TP1-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x01_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm (layer F.Cu) (tedit 5862ED52) (tstamp 5978B3F9)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(at 50.5 30)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /59762630)
(fp_text reference TP2 (at 0 -2.39) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TEST (at 0 2.39) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.6 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.6 1.6) (end 1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 1.6) (end 1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.6) (end -1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.39 -1.39) (end 0 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 0) (end -1.39 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.27) (end -1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.39) (end 1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.39) (end 1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.27) (end -1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 50 "Net-(TP2-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x01_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm (layer F.Cu) (tedit 5862ED52) (tstamp 5978B3FD)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(at 50.5 35)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /597624B7)
(fp_text reference TP3 (at 0 -2.39) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TEST (at 0 2.39) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.6 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.6 1.6) (end 1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 1.6) (end 1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.6) (end -1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.39 -1.39) (end 0 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 0) (end -1.39 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.27) (end -1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.39) (end 1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.39) (end 1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.27) (end -1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 51 "Net-(TP3-Pad1)"))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x01_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(module Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm (layer F.Cu) (tedit 5862ED52) (tstamp 597A1D40)
(at 50.5 20)
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /597A3040)
(fp_text reference TP4 (at 0 -2.39) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TEST (at 0 2.39) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.6 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.6 1.6) (end 1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 1.6) (end 1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.6) (end -1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.39 -1.39) (end 0 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 0) (end -1.39 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.27) (end -1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.39) (end 1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.39) (end 1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.27) (end -1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 69 /SSPND))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x01_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
Layout: Audio-in jack: plated mounting holes => unplated
2017-07-27 20:08:06 +02:00
(module tht:Lumberg-1503 (layer F.Cu) (tedit 597A2BAE) (tstamp 5978A873)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(at 18.7 48.5 180)
Layout: Audio-in jack: plated mounting holes => unplated
2017-07-27 20:08:06 +02:00
(path /59763E9A)
(fp_text reference J2 (at 0.88 -4.46 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Jack_3.5mm_3pin (at 0 4.75 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 9.75 2.5) (end 9.75 0) (layer F.SilkS) (width 0.15))
(fp_line (start -0.75 3) (end -2.5 3) (layer F.SilkS) (width 0.15))
(fp_line (start -0.75 3) (end -0.5 3) (layer F.SilkS) (width 0.15))
(fp_line (start 2.5 3) (end 1 3) (layer F.SilkS) (width 0.15))
(fp_line (start 1 -3) (end 2.5 -3) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -3) (end -2.5 -3) (layer F.SilkS) (width 0.15))
(fp_line (start -4.25 0.25) (end -4.25 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -4.25 0.25) (end -4.25 -1.25) (layer F.SilkS) (width 0.15))
(fp_line (start 7.25 -3) (end 5 -3) (layer F.SilkS) (width 0.15))
(fp_line (start 7.25 0.75) (end 7.25 -3) (layer F.SilkS) (width 0.15))
(fp_line (start 7.25 3) (end 5 3) (layer F.SilkS) (width 0.15))
(fp_line (start 7.25 3) (end 7.25 0.75) (layer F.SilkS) (width 0.15))
(fp_line (start 7.25 2.5) (end 9.75 2.5) (layer F.SilkS) (width 0.15))
(fp_line (start 9.75 0) (end 9.75 -2.5) (layer F.SilkS) (width 0.15))
(fp_line (start 9.75 -2.5) (end 7.25 -2.5) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole rect (at 3.75 -3 180) (size 2 2) (drill oval 1.3 1) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 60 "Net-(C45-Pad2)"))
Layout: Audio-in jack: plated mounting holes => unplated
2017-07-27 20:08:06 +02:00
(pad 2 thru_hole rect (at 3.75 3 180) (size 2 2) (drill oval 1.3 1) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 60 "Net-(C45-Pad2)"))
Layout: Audio-in jack: plated mounting holes => unplated
2017-07-27 20:08:06 +02:00
(pad 1 thru_hole rect (at -3.75 -2.2 180) (size 2 1.5) (drill oval 1.3 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 31 GNDA))
Layout: Audio-in jack: plated mounting holes => unplated
2017-07-27 20:08:06 +02:00
(pad 3 thru_hole rect (at -3.75 2.2 180) (size 2 1.5) (drill oval 1.3 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 62 "Net-(C46-Pad2)"))
Layout: Audio-in jack: plated mounting holes => unplated
2017-07-27 20:08:06 +02:00
(pad "" np_thru_hole circle (at 0.25 -2.5 180) (size 1.05 1.05) (drill 1.05) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 0.25 2.5 180) (size 1.05 1.05) (drill 1.05) (layers *.Cu *.Mask))
)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 597B6AB6)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(at 74 19.5)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /597BF3DD)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C37 (at 0 -1.75) (layer F.SilkS)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 54 "Net-(C37-Pad1)"))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 597B6ABC)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(at 71.85 31.62)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /597BF53A)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C38 (at 0.65 -1.62) (layer F.SilkS)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(fp_text value 1u (at 0 1.9) (layer F.Fab)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(pad 2 smd rect (at 0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(pad 1 smd rect (at -0.95 0) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 55 "Net-(C38-Pad1)"))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module TO_SOT_Packages_THT:TO-92_Molded_Wide_Oval (layer F.Cu) (tedit 58610977) (tstamp 597B6AC3)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(at 70.17 24.5)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(descr "TO-92 leads molded, wide, oval pads, drill 0.8mm (see NXP sot054_po.pdf)")
(tags "to-92 sc-43 sc-43a sot54 PA33 transistor")
(path /597BB5E7)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference Q1 (at 2.58 0) (layer F.SilkS)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_NPN_CBE (at 2.54 3.048) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.35 2.2) (end 6.35 -3.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 -3.8) (end 6.35 -3.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 2.2) (end 6.35 2.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 2.2) (end -1.25 -3.8) (layer F.CrtYd) (width 0.05))
(fp_arc (start 2.54 0) (end 4.34 1.85) (angle -20) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.54 0) (end 2.54 -2.48) (angle -135) (layer F.Fab) (width 0.1))
(fp_arc (start 2.54 0) (end 2.54 -2.48) (angle 135) (layer F.Fab) (width 0.1))
(fp_arc (start 2.54 0) (end 2.54 -2.6) (angle 65) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.54 0) (end 2.54 -2.6) (angle -65) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.54 0) (end 0.74 1.85) (angle 20) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 1.75) (end 4.3 1.75) (layer F.Fab) (width 0.1))
(fp_line (start 0.74 1.85) (end 4.34 1.85) (layer F.SilkS) (width 0.12))
(pad 3 thru_hole oval (at 5.08 0 90) (size 1.50114 1.99898) (drill 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 19 +12V))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(pad 1 thru_hole rect (at 0 0 90) (size 1.50114 1.99898) (drill 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 14 "Net-(C16-Pad1)"))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(pad 2 thru_hole oval (at 2.54 -2.54 90) (size 1.99898 1.50114) (drill 0.8) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 54 "Net-(C37-Pad1)"))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(model TO_SOT_Packages_THT.3dshapes/TO-92_Molded_Wide_Oval.wrl
(at (xyz 0.1 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 -90))
)
)
(module TO_SOT_Packages_THT:TO-92_Molded_Wide_Oval (layer F.Cu) (tedit 58610977) (tstamp 597B6ACA)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(at 67.21 35.35 180)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(descr "TO-92 leads molded, wide, oval pads, drill 0.8mm (see NXP sot054_po.pdf)")
(tags "to-92 sc-43 sc-43a sot54 PA33 transistor")
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(path /59D4D009)
(fp_text reference Q2 (at 2.45 0.03 180) (layer F.SilkS)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(fp_text value Q_PNP_EBC (at 2.54 3.048 180) (layer F.Fab)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.35 2.2) (end 6.35 -3.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 -3.8) (end 6.35 -3.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 2.2) (end 6.35 2.2) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 2.2) (end -1.25 -3.8) (layer F.CrtYd) (width 0.05))
(fp_arc (start 2.54 0) (end 4.34 1.85) (angle -20) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.54 0) (end 2.54 -2.48) (angle -135) (layer F.Fab) (width 0.1))
(fp_arc (start 2.54 0) (end 2.54 -2.48) (angle 135) (layer F.Fab) (width 0.1))
(fp_arc (start 2.54 0) (end 2.54 -2.6) (angle 65) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.54 0) (end 2.54 -2.6) (angle -65) (layer F.SilkS) (width 0.12))
(fp_arc (start 2.54 0) (end 0.74 1.85) (angle 20) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 1.75) (end 4.3 1.75) (layer F.Fab) (width 0.1))
(fp_line (start 0.74 1.85) (end 4.34 1.85) (layer F.SilkS) (width 0.12))
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(pad 3 thru_hole oval (at 5.08 0 270) (size 1.50114 1.99898) (drill 0.8) (layers *.Cu *.Mask)
(net 15 "Net-(C17-Pad2)"))
(pad 1 thru_hole rect (at 0 0 270) (size 1.50114 1.99898) (drill 0.8) (layers *.Cu *.Mask)
(net 20 -12V))
(pad 2 thru_hole oval (at 2.54 -2.54 270) (size 1.99898 1.50114) (drill 0.8) (layers *.Cu *.Mask)
(net 55 "Net-(C38-Pad1)"))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(model TO_SOT_Packages_THT.3dshapes/TO-92_Molded_Wide_Oval.wrl
(at (xyz 0.1 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 -90))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 597B6AD0)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(at 68.25 19.5)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /597BC448)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R19 (at 0 -1.75) (layer F.SilkS)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 54 "Net-(C37-Pad1)"))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 14 "Net-(C16-Pad1)"))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 597B6AD6)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(at 68.75 30.5 90)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /597BE8B7)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference R20 (at 1.25 1.5 90) (layer F.SilkS)
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 15 "Net-(C17-Pad2)"))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 55 "Net-(C38-Pad1)"))
removed 120uF from power supply, added transistor dropout circuit to reduce noise
2017-07-28 19:00:41 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(module artwork:shimatta_audio (layer B.Cu) (tedit 0) (tstamp 59918ACF)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(at 33.32 22.79 180)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(fp_text reference G*** (at 0 0 180) (layer B.SilkS) hide
(effects (font (thickness 0.3)) (justify mirror))
)
(fp_text value LOGO (at 0.75 0 180) (layer B.SilkS) hide
(effects (font (thickness 0.3)) (justify mirror))
)
(fp_poly (pts (xy 1.083923 3.780581) (xy 2.256561 3.701685) (xy 3.382808 3.572332) (xy 4.454558 3.394026)
(xy 5.463706 3.168273) (xy 6.402146 2.896575) (xy 7.261774 2.580436) (xy 7.809525 2.334844)
(xy 8.384579 2.023416) (xy 8.873954 1.69145) (xy 9.273387 1.342507) (xy 9.578613 0.98015)
(xy 9.7282 0.731815) (xy 9.803743 0.571684) (xy 9.849376 0.432985) (xy 9.872408 0.279403)
(xy 9.880148 0.074625) (xy 9.8806 -0.0254) (xy 9.87678 -0.259611) (xy 9.860681 -0.427543)
(xy 9.825339 -0.564373) (xy 9.763791 -0.705282) (xy 9.734809 -0.762) (xy 9.616467 -0.963088)
(xy 9.476324 -1.162494) (xy 9.330453 -1.341343) (xy 9.194928 -1.480762) (xy 9.085821 -1.561877)
(xy 9.042626 -1.5748) (xy 8.914632 -1.565327) (xy 8.859393 -1.529812) (xy 8.878214 -1.457604)
(xy 8.972399 -1.338056) (xy 9.086323 -1.218) (xy 9.381397 -0.866288) (xy 9.574881 -0.515649)
(xy 9.666777 -0.16572) (xy 9.657085 0.183865) (xy 9.545805 0.533467) (xy 9.33294 0.883452)
(xy 9.090855 1.162584) (xy 8.689558 1.513121) (xy 8.195168 1.844969) (xy 7.614938 2.155354)
(xy 6.956121 2.441498) (xy 6.225969 2.700627) (xy 5.431736 2.929965) (xy 4.580675 3.126737)
(xy 3.680039 3.288166) (xy 3.445437 3.323039) (xy 2.134519 3.480102) (xy 0.868107 3.568602)
(xy -0.37984 3.588534) (xy -1.635359 3.539892) (xy -2.924491 3.422672) (xy -3.7084 3.321768)
(xy -4.528024 3.186232) (xy -5.329458 3.015996) (xy -6.097861 2.815549) (xy -6.818397 2.589378)
(xy -7.476224 2.341972) (xy -8.056505 2.077819) (xy -8.3566 1.915866) (xy -8.790878 1.634197)
(xy -9.168447 1.328038) (xy -9.481405 1.006975) (xy -9.721851 0.680593) (xy -9.881881 0.35848)
(xy -9.953595 0.050221) (xy -9.9568 -0.0254) (xy -9.908996 -0.328564) (xy -9.770848 -0.64804)
(xy -9.550261 -0.974242) (xy -9.255136 -1.297582) (xy -8.893375 -1.608475) (xy -8.47288 -1.897334)
(xy -8.3566 -1.966665) (xy -7.772363 -2.265923) (xy -7.10044 -2.541279) (xy -6.352365 -2.790704)
(xy -5.53967 -3.012169) (xy -4.673888 -3.203645) (xy -3.766552 -3.363105) (xy -2.829193 -3.48852)
(xy -1.873345 -3.577861) (xy -0.91054 -3.6291) (xy 0.04769 -3.640208) (xy 0.983458 -3.609516)
(xy 1.35343 -3.586474) (xy 1.735177 -3.558912) (xy 2.10036 -3.529141) (xy 2.420637 -3.499471)
(xy 2.667 -3.472297) (xy 3.064718 -3.423742) (xy 3.375929 -3.38972) (xy 3.614598 -3.369675)
(xy 3.794692 -3.363049) (xy 3.930175 -3.369287) (xy 4.035014 -3.387833) (xy 4.1148 -3.414623)
(xy 4.186579 -3.445696) (xy 4.21715 -3.469091) (xy 4.194698 -3.489182) (xy 4.107413 -3.510343)
(xy 3.943481 -3.536949) (xy 3.691091 -3.573374) (xy 3.683 -3.574526) (xy 3.430026 -3.610827)
(xy 3.20044 -3.644286) (xy 3.020588 -3.671031) (xy 2.921 -3.686496) (xy 2.579883 -3.731608)
(xy 2.154895 -3.769792) (xy 1.663549 -3.800714) (xy 1.123359 -3.824039) (xy 0.551839 -3.839432)
(xy -0.033497 -3.84656) (xy -0.615134 -3.845087) (xy -1.175559 -3.83468) (xy -1.697259 -3.815003)
(xy -2.162718 -3.785724) (xy -2.1844 -3.783985) (xy -3.443025 -3.651751) (xy -4.616655 -3.465941)
(xy -5.706865 -3.226169) (xy -6.715225 -2.932048) (xy -7.643308 -2.583191) (xy -8.299658 -2.279332)
(xy -8.766756 -2.011274) (xy -9.186903 -1.70637) (xy -9.546107 -1.37722) (xy -9.830374 -1.036427)
(xy -10.003694 -0.744785) (xy -10.089982 -0.546252) (xy -10.137656 -0.375505) (xy -10.15728 -0.183915)
(xy -10.16 -0.0254) (xy -10.152928 0.205753) (xy -10.124666 0.384492) (xy -10.064647 0.55945)
(xy -10.003694 0.693986) (xy -9.769002 1.074425) (xy -9.439469 1.437561) (xy -9.020653 1.781642)
(xy -8.518117 2.104914) (xy -7.937422 2.405625) (xy -7.284127 2.682021) (xy -6.563794 2.93235)
(xy -5.781983 3.154858) (xy -4.944256 3.347792) (xy -4.056172 3.5094) (xy -3.123294 3.637929)
(xy -2.151181 3.731625) (xy -1.145395 3.788735) (xy -0.127 3.807517) (xy 1.083923 3.780581)) (layer B.Mask) (width 0.01))
(fp_poly (pts (xy 4.847475 -1.839154) (xy 4.909673 -1.845819) (xy 4.955325 -1.861635) (xy 4.991124 -1.90214)
(xy 5.023761 -1.982871) (xy 5.059928 -2.119368) (xy 5.10632 -2.327168) (xy 5.154711 -2.552489)
(xy 5.204552 -2.749827) (xy 5.259534 -2.914008) (xy 5.30913 -3.01446) (xy 5.316952 -3.023695)
(xy 5.383345 -3.124467) (xy 5.354799 -3.195709) (xy 5.23421 -3.235295) (xy 5.024476 -3.241096)
(xy 5.021189 -3.240941) (xy 4.840482 -3.220052) (xy 4.719247 -3.182669) (xy 4.668739 -3.136831)
(xy 4.700216 -3.090575) (xy 4.772581 -3.063404) (xy 4.854348 -3.013608) (xy 4.867475 -2.907464)
(xy 4.866833 -2.90166) (xy 4.846046 -2.818678) (xy 4.789679 -2.776259) (xy 4.668784 -2.757069)
(xy 4.61935 -2.753494) (xy 4.472013 -2.750722) (xy 4.39024 -2.776683) (xy 4.33907 -2.845342)
(xy 4.32725 -2.870184) (xy 4.278796 -2.985248) (xy 4.277842 -3.035584) (xy 4.327358 -3.047789)
(xy 4.347124 -3.048) (xy 4.407909 -3.085875) (xy 4.410149 -3.1369) (xy 4.37396 -3.193842)
(xy 4.277892 -3.226332) (xy 4.131565 -3.240997) (xy 3.976992 -3.240379) (xy 3.867556 -3.222187)
(xy 3.837856 -3.204374) (xy 3.850514 -3.140192) (xy 3.923503 -3.050748) (xy 3.938282 -3.037387)
(xy 4.014952 -2.948647) (xy 4.125166 -2.792744) (xy 4.254056 -2.591841) (xy 4.276569 -2.553916)
(xy 4.536166 -2.553916) (xy 4.613547 -2.58921) (xy 4.6482 -2.5908) (xy 4.745179 -2.569516)
(xy 4.774798 -2.487214) (xy 4.7752 -2.467954) (xy 4.761973 -2.334397) (xy 4.742995 -2.261186)
(xy 4.71224 -2.217998) (xy 4.666784 -2.24962) (xy 4.61633 -2.320532) (xy 4.537381 -2.466789)
(xy 4.536166 -2.553916) (xy 4.276569 -2.553916) (xy 4.38387 -2.373165) (xy 4.515777 -2.144455)
(xy 4.610757 -1.99056) (xy 4.681051 -1.89738) (xy 4.738898 -1.850818) (xy 4.796535 -1.836776)
(xy 4.847475 -1.839154)) (layer B.Mask) (width 0.01))
(fp_poly (pts (xy 6.617219 -2.194219) (xy 6.646927 -2.239124) (xy 6.636594 -2.300822) (xy 6.614138 -2.416939)
(xy 6.588468 -2.587443) (xy 6.574176 -2.699699) (xy 6.558665 -2.862084) (xy 6.565343 -2.950985)
(xy 6.600662 -2.99329) (xy 6.648689 -3.010321) (xy 6.741482 -3.057058) (xy 6.736668 -3.118129)
(xy 6.635937 -3.186351) (xy 6.604 -3.2004) (xy 6.45832 -3.237856) (xy 6.318223 -3.208131)
(xy 6.303808 -3.202309) (xy 6.157838 -3.167317) (xy 6.053148 -3.196146) (xy 5.869714 -3.248225)
(xy 5.704293 -3.201409) (xy 5.634872 -3.145672) (xy 5.566731 -3.049602) (xy 5.554585 -2.974366)
(xy 5.591159 -2.843254) (xy 5.614545 -2.692325) (xy 5.622384 -2.553854) (xy 5.612315 -2.460119)
(xy 5.593768 -2.4384) (xy 5.547829 -2.395908) (xy 5.5372 -2.3368) (xy 5.570731 -2.253963)
(xy 5.6515 -2.234506) (xy 5.795667 -2.220235) (xy 5.887864 -2.20115) (xy 5.963462 -2.187073)
(xy 5.9927 -2.215475) (xy 5.987295 -2.309882) (xy 5.976764 -2.379644) (xy 5.935751 -2.638682)
(xy 5.909696 -2.813481) (xy 5.899598 -2.92044) (xy 5.906457 -2.975955) (xy 5.931271 -2.996425)
(xy 5.975041 -2.998247) (xy 6.014396 -2.9972) (xy 6.102069 -2.982414) (xy 6.167718 -2.926846)
(xy 6.220584 -2.813677) (xy 6.26991 -2.626088) (xy 6.300551 -2.4765) (xy 6.335687 -2.312864)
(xy 6.371227 -2.225552) (xy 6.424412 -2.190688) (xy 6.511508 -2.1844) (xy 6.617219 -2.194219)) (layer B.Mask) (width 0.01))
(fp_poly (pts (xy 8.060504 -1.77152) (xy 8.053622 -1.8415) (xy 8.029598 -1.962308) (xy 7.99761 -2.140364)
(xy 7.962126 -2.348483) (xy 7.927613 -2.559477) (xy 7.898537 -2.74616) (xy 7.879366 -2.881348)
(xy 7.874162 -2.9337) (xy 7.916289 -2.985735) (xy 7.972601 -2.9972) (xy 8.078285 -3.022314)
(xy 8.094878 -3.085848) (xy 8.017977 -3.170092) (xy 8.015946 -3.171524) (xy 7.858094 -3.241108)
(xy 7.71088 -3.235799) (xy 7.620774 -3.175933) (xy 7.563006 -3.127651) (xy 7.495083 -3.146713)
(xy 7.450851 -3.175933) (xy 7.276809 -3.245431) (xy 7.104585 -3.214995) (xy 6.98269 -3.126509)
(xy 6.883101 -2.959752) (xy 6.866385 -2.81068) (xy 7.165866 -2.81068) (xy 7.16772 -2.948692)
(xy 7.196666 -3.014133) (xy 7.293262 -3.050357) (xy 7.402328 -3.006191) (xy 7.493276 -2.895065)
(xy 7.551506 -2.734619) (xy 7.583116 -2.557881) (xy 7.58348 -2.552176) (xy 7.581683 -2.424085)
(xy 7.545837 -2.364866) (xy 7.481598 -2.346147) (xy 7.381324 -2.364962) (xy 7.288148 -2.463724)
(xy 7.265888 -2.498536) (xy 7.200274 -2.648073) (xy 7.165866 -2.81068) (xy 6.866385 -2.81068)
(xy 6.859968 -2.753454) (xy 6.914382 -2.536209) (xy 6.957071 -2.454342) (xy 7.101078 -2.282082)
(xy 7.277788 -2.200062) (xy 7.473227 -2.193643) (xy 7.601314 -2.199283) (xy 7.657686 -2.17384)
(xy 7.67077 -2.103388) (xy 7.6708 -2.096842) (xy 7.651866 -2.00695) (xy 7.62 -1.9812)
(xy 7.574537 -1.940225) (xy 7.5692 -1.907387) (xy 7.614288 -1.846173) (xy 7.729046 -1.790055)
(xy 7.7597 -1.780671) (xy 7.932381 -1.738182) (xy 8.026876 -1.733937) (xy 8.060504 -1.77152)) (layer B.Mask) (width 0.01))
(fp_poly (pts (xy 8.767698 -2.197565) (xy 8.765323 -2.250126) (xy 8.746797 -2.377022) (xy 8.715911 -2.552966)
(xy 8.708657 -2.591431) (xy 8.674112 -2.774078) (xy 8.64848 -2.912467) (xy 8.636429 -2.981321)
(xy 8.636059 -2.9845) (xy 8.679544 -2.994142) (xy 8.760001 -2.9972) (xy 8.88097 -3.018092)
(xy 8.908987 -3.071666) (xy 8.841519 -3.144266) (xy 8.792583 -3.172836) (xy 8.596105 -3.243295)
(xy 8.447914 -3.227674) (xy 8.383928 -3.177323) (xy 8.349921 -3.083685) (xy 8.34633 -2.913378)
(xy 8.358225 -2.770923) (xy 8.372799 -2.572735) (xy 8.363428 -2.465047) (xy 8.337118 -2.4384)
(xy 8.289992 -2.396237) (xy 8.2804 -2.343704) (xy 8.303479 -2.280343) (xy 8.387591 -2.240304)
(xy 8.5173 -2.216539) (xy 8.659229 -2.20004) (xy 8.750988 -2.194964) (xy 8.767698 -2.197565)) (layer B.Mask) (width 0.01))
(fp_poly (pts (xy 9.793759 -2.198924) (xy 9.967715 -2.293224) (xy 9.984509 -2.30909) (xy 10.086746 -2.470894)
(xy 10.106282 -2.649701) (xy 10.056636 -2.829887) (xy 9.951323 -2.995827) (xy 9.803863 -3.131898)
(xy 9.627771 -3.222473) (xy 9.436567 -3.251928) (xy 9.243767 -3.20464) (xy 9.2202 -3.192539)
(xy 9.062548 -3.057905) (xy 8.999516 -2.89141) (xy 9.349447 -2.89141) (xy 9.364719 -2.96958)
(xy 9.433896 -3.037703) (xy 9.538357 -3.036561) (xy 9.643516 -2.970648) (xy 9.676819 -2.929015)
(xy 9.748269 -2.774519) (xy 9.772529 -2.620521) (xy 9.756202 -2.486006) (xy 9.705889 -2.38996)
(xy 9.628194 -2.35137) (xy 9.529717 -2.389221) (xy 9.49868 -2.416741) (xy 9.417106 -2.546893)
(xy 9.36339 -2.721506) (xy 9.349447 -2.89141) (xy 8.999516 -2.89141) (xy 8.99449 -2.878136)
(xy 9.016991 -2.65777) (xy 9.07465 -2.507339) (xy 9.202526 -2.339463) (xy 9.383468 -2.228078)
(xy 9.589778 -2.17922) (xy 9.793759 -2.198924)) (layer B.Mask) (width 0.01))
(fp_poly (pts (xy 8.765514 -1.703497) (xy 8.819321 -1.783696) (xy 8.814608 -1.894311) (xy 8.759579 -1.984979)
(xy 8.680399 -2.060629) (xy 8.613739 -2.071763) (xy 8.5471 -2.049156) (xy 8.494664 -1.981365)
(xy 8.488712 -1.870373) (xy 8.527756 -1.76254) (xy 8.557359 -1.729225) (xy 8.671942 -1.677433)
(xy 8.765514 -1.703497)) (layer B.Mask) (width 0.01))
(fp_poly (pts (xy -7.116737 1.7272) (xy -7.101669 0.38624) (xy -7.096292 -0.045558) (xy -7.089115 -0.38695)
(xy -7.077362 -0.649126) (xy -7.058259 -0.843274) (xy -7.02903 -0.980584) (xy -6.986899 -1.072245)
(xy -6.929092 -1.129446) (xy -6.852833 -1.163378) (xy -6.755346 -1.185228) (xy -6.70995 -1.193065)
(xy -6.426135 -1.19212) (xy -6.136151 -1.104018) (xy -5.860065 -0.93976) (xy -5.617938 -0.710343)
(xy -5.480813 -0.519229) (xy -5.407641 -0.398911) (xy -5.358598 -0.320811) (xy -5.350378 -0.308833)
(xy -5.306712 -0.324941) (xy -5.221972 -0.392532) (xy -5.209018 -0.404504) (xy -5.084437 -0.521542)
(xy -5.238187 -0.74501) (xy -5.483739 -1.029383) (xy -5.783539 -1.261198) (xy -6.114393 -1.427211)
(xy -6.45311 -1.51418) (xy -6.602457 -1.524) (xy -6.761421 -1.5) (xy -6.944309 -1.439657)
(xy -7.009363 -1.4097) (xy -7.130867 -1.346014) (xy -7.227188 -1.284959) (xy -7.301396 -1.21441)
(xy -7.356559 -1.122244) (xy -7.395748 -0.996337) (xy -7.422033 -0.824563) (xy -7.438482 -0.5948)
(xy -7.448167 -0.294922) (xy -7.454156 0.087194) (xy -7.457233 0.35921) (xy -7.472265 1.727201)
(xy -7.294501 1.727201) (xy -7.116737 1.7272)) (layer B.Mask) (width 0.01))
(fp_poly (pts (xy -2.302923 1.8246) (xy -2.256409 1.795545) (xy -2.238312 1.71695) (xy -2.235204 1.564134)
(xy -2.2352 1.541906) (xy -2.2352 1.255012) (xy -1.8161 1.288252) (xy -1.605324 1.307564)
(xy -1.422086 1.32898) (xy -1.299375 1.348527) (xy -1.2827 1.352471) (xy -1.202181 1.360999)
(xy -1.171987 1.308835) (xy -1.1684 1.231689) (xy -1.172136 1.153282) (xy -1.197773 1.105611)
(xy -1.266961 1.077745) (xy -1.401348 1.058754) (xy -1.5367 1.045734) (xy -1.808962 1.020168)
(xy -1.995708 0.997653) (xy -2.11243 0.970276) (xy -2.174621 0.930129) (xy -2.197772 0.869301)
(xy -2.197374 0.779881) (xy -2.192397 0.710928) (xy -2.174993 0.463102) (xy -1.912997 0.496337)
(xy -1.663581 0.524265) (xy -1.497239 0.531419) (xy -1.397177 0.515706) (xy -1.346602 0.475033)
(xy -1.33058 0.423778) (xy -1.330423 0.366206) (xy -1.360106 0.324683) (xy -1.436003 0.293504)
(xy -1.574493 0.266965) (xy -1.791951 0.239361) (xy -1.8923 0.22811) (xy -2.1844 0.19589)
(xy -2.181046 -0.4826) (xy -1.738223 -0.694669) (xy -1.535447 -0.794312) (xy -1.35972 -0.885261)
(xy -1.236875 -0.953936) (xy -1.202557 -0.976271) (xy -1.143071 -1.030072) (xy -1.146343 -1.082641)
(xy -1.211948 -1.170602) (xy -1.290695 -1.252727) (xy -1.356538 -1.261663) (xy -1.431792 -1.222027)
(xy -1.717931 -1.045859) (xy -1.93572 -0.916848) (xy -2.079701 -0.838134) (xy -2.143312 -0.8128)
(xy -2.174512 -0.856227) (xy -2.1844 -0.936492) (xy -2.225435 -1.162343) (xy -2.343122 -1.332304)
(xy -2.433695 -1.394566) (xy -2.591547 -1.442349) (xy -2.809763 -1.466792) (xy -3.04977 -1.467647)
(xy -3.272991 -1.444665) (xy -3.433309 -1.400992) (xy -3.578733 -1.30982) (xy -3.700009 -1.192929)
(xy -3.79658 -1.007905) (xy -3.800436 -0.873988) (xy -3.495631 -0.873988) (xy -3.468294 -0.973977)
(xy -3.371077 -1.078921) (xy -3.230743 -1.162439) (xy -3.186569 -1.178644) (xy -3.038383 -1.20078)
(xy -2.857729 -1.195949) (xy -2.687735 -1.168386) (xy -2.571533 -1.122329) (xy -2.565428 -1.117623)
(xy -2.514748 -1.02874) (xy -2.491521 -0.897533) (xy -2.498248 -0.768877) (xy -2.537432 -0.687651)
(xy -2.541307 -0.684992) (xy -2.618729 -0.662185) (xy -2.759584 -0.639166) (xy -2.858807 -0.628078)
(xy -3.073879 -0.6326) (xy -3.268545 -0.679832) (xy -3.416867 -0.759756) (xy -3.492905 -0.862356)
(xy -3.495631 -0.873988) (xy -3.800436 -0.873988) (xy -3.801717 -0.829515) (xy -3.725544 -0.667243)
(xy -3.578188 -0.530568) (xy -3.369774 -0.428974) (xy -3.110428 -0.371941) (xy -2.819285 -0.368204)
(xy -2.4892 -0.3947) (xy -2.4892 0.216186) (xy -2.69846 0.182724) (xy -2.857436 0.170457)
(xy -3.070196 0.170859) (xy -3.28266 0.183238) (xy -3.474882 0.203003) (xy -3.587079 0.224765)
(xy -3.6406 0.257289) (xy -3.656793 0.309344) (xy -3.6576 0.337207) (xy -3.654364 0.388654)
(xy -3.633122 0.422784) (xy -3.57658 0.443152) (xy -3.46744 0.453309) (xy -3.288407 0.456808)
(xy -3.0734 0.4572) (xy -2.4892 0.4572) (xy -2.4892 0.9652) (xy -3.867549 0.9652)
(xy -3.851475 1.099514) (xy -3.8354 1.233828) (xy -2.520588 1.2446) (xy -2.533977 1.5367)
(xy -2.547367 1.8288) (xy -2.391284 1.8288) (xy -2.302923 1.8246)) (layer B.Mask) (width 0.01))
(fp_poly (pts (xy 5.29202 1.819239) (xy 5.345527 1.800339) (xy 5.349396 1.73943) (xy 5.328905 1.613327)
(xy 5.303797 1.508239) (xy 5.264241 1.352298) (xy 5.238508 1.236744) (xy 5.233002 1.200008)
(xy 5.277828 1.181544) (xy 5.39669 1.184886) (xy 5.564946 1.207662) (xy 5.757952 1.247498)
(xy 5.7785 1.252537) (xy 5.858765 1.259026) (xy 5.88911 1.205723) (xy 5.8928 1.127144)
(xy 5.888482 1.04983) (xy 5.863424 0.996992) (xy 5.799461 0.960139) (xy 5.678434 0.93078)
(xy 5.48218 0.900424) (xy 5.376714 0.885848) (xy 5.140028 0.853448) (xy 4.954024 0.287024)
(xy 4.846958 -0.029422) (xy 4.733412 -0.348491) (xy 4.619986 -0.653204) (xy 4.513279 -0.926579)
(xy 4.419891 -1.151638) (xy 4.346421 -1.311399) (xy 4.305179 -1.382397) (xy 4.236652 -1.434679)
(xy 4.140667 -1.418168) (xy 4.1148 -1.407358) (xy 4.017123 -1.363956) (xy 3.974564 -1.344148)
(xy 3.98953 -1.298304) (xy 4.040241 -1.17976) (xy 4.118385 -1.00737) (xy 4.199765 -0.833431)
(xy 4.319615 -0.563102) (xy 4.448873 -0.243534) (xy 4.568472 0.076985) (xy 4.629085 0.254)
(xy 4.819969 0.8382) (xy 4.416584 0.852955) (xy 4.215829 0.861955) (xy 4.095882 0.875533)
(xy 4.035983 0.900778) (xy 4.01537 0.944776) (xy 4.0132 0.990677) (xy 4.017969 1.049718)
(xy 4.045475 1.086888) (xy 4.115514 1.108318) (xy 4.247883 1.120138) (xy 4.4577 1.128323)
(xy 4.9022 1.143) (xy 4.973329 1.485901) (xy 5.013825 1.666921) (xy 5.0498 1.769785)
(xy 5.09449 1.816372) (xy 5.16113 1.828562) (xy 5.180762 1.828801) (xy 5.29202 1.819239)) (layer B.Mask) (width 0.01))
(fp_poly (pts (xy 5.579185 -0.500757) (xy 5.617246 -0.610164) (xy 5.633526 -0.662829) (xy 5.697698 -0.821557)
(xy 5.790423 -0.9341) (xy 5.927358 -1.006874) (xy 6.124161 -1.046297) (xy 6.39649 -1.058784)
(xy 6.593588 -1.056255) (xy 6.841947 -1.050758) (xy 7.007061 -1.051557) (xy 7.10723 -1.061587)
(xy 7.160756 -1.083787) (xy 7.185937 -1.121092) (xy 7.195271 -1.152812) (xy 7.208564 -1.240738)
(xy 7.187378 -1.301543) (xy 7.117566 -1.340122) (xy 6.984981 -1.361367) (xy 6.775474 -1.370173)
(xy 6.562901 -1.371559) (xy 6.287085 -1.368509) (xy 6.088567 -1.357354) (xy 5.943167 -1.335024)
(xy 5.826709 -1.298448) (xy 5.764144 -1.270115) (xy 5.545467 -1.106349) (xy 5.388978 -0.864311)
(xy 5.335022 -0.714764) (xy 5.317992 -0.604788) (xy 5.363995 -0.541953) (xy 5.417794 -0.513782)
(xy 5.514503 -0.471958) (xy 5.556949 -0.4572) (xy 5.579185 -0.500757)) (layer B.Mask) (width 0.01))
(fp_poly (pts (xy 2.070811 0.647843) (xy 2.194619 0.628115) (xy 2.296059 0.590502) (xy 2.3368 0.569501)
(xy 2.557555 0.398886) (xy 2.692492 0.174465) (xy 2.742781 -0.105801) (xy 2.7432 -0.137035)
(xy 2.702864 -0.439555) (xy 2.580026 -0.692499) (xy 2.371938 -0.898462) (xy 2.075856 -1.060037)
(xy 1.689031 -1.179821) (xy 1.624254 -1.194083) (xy 1.373901 -1.243154) (xy 1.202881 -1.264671)
(xy 1.092308 -1.257083) (xy 1.023298 -1.218838) (xy 0.976966 -1.148384) (xy 0.973354 -1.140609)
(xy 0.93044 -1.041478) (xy 0.9144 -0.995577) (xy 0.96073 -0.983887) (xy 1.082391 -0.968082)
(xy 1.25339 -0.951518) (xy 1.259354 -0.951016) (xy 1.617387 -0.893958) (xy 1.929724 -0.790837)
(xy 2.179596 -0.649342) (xy 2.35024 -0.477163) (xy 2.373099 -0.440233) (xy 2.425903 -0.268101)
(xy 2.429944 -0.063156) (xy 2.386491 0.122633) (xy 2.358039 0.177021) (xy 2.234728 0.297017)
(xy 2.050044 0.368874) (xy 1.798759 0.392454) (xy 1.475648 0.367618) (xy 1.075485 0.294228)
(xy 0.593045 0.172144) (xy 0.431272 0.125941) (xy 0.349101 0.12696) (xy 0.290451 0.20293)
(xy 0.271812 0.248006) (xy 0.21448 0.399896) (xy 0.67874 0.511836) (xy 0.953437 0.566396)
(xy 1.271873 0.612164) (xy 1.57619 0.6412) (xy 1.651 0.645251) (xy 1.898362 0.652588)
(xy 2.070811 0.647843)) (layer B.Mask) (width 0.01))
(fp_poly (pts (xy 6.905096 0.60004) (xy 6.951749 0.553626) (xy 6.9596 0.463169) (xy 6.955863 0.389425)
(xy 6.930687 0.3436) (xy 6.863124 0.316016) (xy 6.732227 0.296994) (xy 6.5659 0.281262)
(xy 6.196381 0.238184) (xy 5.864179 0.180704) (xy 5.6261 0.121714) (xy 5.562561 0.122777)
(xy 5.538886 0.193834) (xy 5.5372 0.247154) (xy 5.56661 0.380623) (xy 5.6261 0.426805)
(xy 5.754444 0.457584) (xy 5.949474 0.494823) (xy 6.179574 0.53355) (xy 6.413129 0.568793)
(xy 6.618522 0.59558) (xy 6.764138 0.60894) (xy 6.788454 0.6096) (xy 6.905096 0.60004)) (layer B.Mask) (width 0.01))
)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 59918DD0)
(at 85 29.75 180)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59919857)
(attr smd)
Layout: Silkscreen Fix
2017-09-10 20:10:51 +02:00
(fp_text reference C39 (at -2.75 1.25 270) (layer F.SilkS)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 19 +12V))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 59918DD6)
(at 71.25 35.25 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5991A29D)
(attr smd)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(fp_text reference C40 (at 3 0.25 180) (layer F.SilkS)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 0 1.9 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 20 -12V))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 59918DDC)
(at 77.5 21 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59919D29)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C41 (at 1.75 2 90) (layer F.SilkS)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 0 1.9 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 19 +12V))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 59918DE2)
(at 69.5 35.25 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5991A2A3)
(attr smd)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(fp_text reference C42 (at -1 1.75 270) (layer F.SilkS)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 0 1.9 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 20 -12V))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 541A9B4D) (tstamp 59918DE8)
(at 85 31.5 180)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59919E53)
(attr smd)
Layout: Silkscreen Fix
2017-09-10 20:10:51 +02:00
(fp_text reference C43 (at -2.75 0 270) (layer F.SilkS)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100n (at 0 1.9 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.15))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.15))
(fp_line (start 1.85 -0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end -1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.15))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 19 +12V))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 541A9B4D) (tstamp 59918DEE)
(at 98.5 52.75 180)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /5991A2A9)
(attr smd)
(fp_text reference C44 (at 0 1.9 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 100n (at 0 -1.9 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.15))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.15))
(fp_line (start 1.85 0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end -1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 -0.75) (end 1.85 -0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.85 0.75) (end 1.85 0.75) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.15))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.15))
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 20 -12V))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(model Capacitors_SMD.3dshapes/C_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58307AEF) (tstamp 5991AFDC)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(at 37.75 43 90)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5991F1EB)
(attr smd)
(fp_text reference R21 (at 0 1.9 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 10 (at 0 -1.9 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 1 Earth))
(pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 66 "Net-(K1-Pad8)"))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58307AEF) (tstamp 5991AFE2)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(at 27.75 41.75 90)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /5991F691)
(attr smd)
(fp_text reference R22 (at 0 1.9 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 10 (at 0 -1.9 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 1 Earth))
(pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 67 "Net-(K2-Pad8)"))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add balance poti
2017-08-28 22:59:34 +02:00
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58307AEF) (tstamp 59A483D6)
(at 108.4 53.75)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /59A4CCD3)
(attr smd)
(fp_text reference R23 (at 0 1.9) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 330 (at 0 -1.9) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.5 0.675) (end 0.5 0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 0.5 -0.675) (end -0.5 -0.675) (layer B.SilkS) (width 0.15))
(fp_line (start 2 0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end -2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 56 "Net-(R23-Pad2)"))
add balance poti
2017-08-28 22:59:34 +02:00
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 57 "Net-(R23-Pad1)"))
add balance poti
2017-08-28 22:59:34 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58307AEF) (tstamp 59A483DC)
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(at 101.75 49.75)
add balance poti
2017-08-28 22:59:34 +02:00
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /59A4D380)
(attr smd)
(fp_text reference R24 (at 0 -1.9) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 330 (at 0 1.9) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.5 -0.675) (end 0.5 -0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 0.5 0.675) (end -0.5 0.675) (layer F.SilkS) (width 0.15))
(fp_line (start 2 -0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end -2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 0.8) (end 2 0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -2 -0.8) (end 2 -0.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd rect (at 1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 58 "Net-(R24-Pad2)"))
add balance poti
2017-08-28 22:59:34 +02:00
(pad 1 smd rect (at -1.1 0) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 59 "Net-(R24-Pad1)"))
add balance poti
2017-08-28 22:59:34 +02:00
(model Resistors_SMD.3dshapes/R_0603_HandSoldering.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Potentiometers:Potentiometer_Bourns_3296Y_3-8Zoll_Angular_ScrewUp (layer F.Cu) (tedit 54130BC5) (tstamp 59A483E3)
(at 109.08 37.5 90)
(descr "3296, 3/8, Square, Trimpot, Trimming, Potentiometer, Bourns")
(tags "3296, 3/8, Square, Trimpot, Trimming, Potentiometer, Bourns")
(path /59A4C01D)
fix silkscreen
2017-08-28 23:00:45 +02:00
(fp_text reference RV2 (at 1.25 -2.58 180) (layer F.SilkS)
add balance poti
2017-08-28 22:59:34 +02:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 5.08 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.27 2.286) (end -2.54 2.286) (layer F.SilkS) (width 0.15))
(fp_line (start 1.27 2.286) (end -1.27 2.286) (layer F.SilkS) (width 0.15))
(fp_line (start -3.81 -7.366) (end 1.27 -7.366) (layer F.SilkS) (width 0.15))
(fp_line (start -3.81 2.286) (end -3.81 -7.366) (layer F.SilkS) (width 0.15))
(fp_line (start -2.54 2.286) (end -3.81 2.286) (layer F.SilkS) (width 0.15))
(fp_line (start -1.8415 1.3462) (end -1.7526 1.1684) (layer F.SilkS) (width 0.15))
(fp_line (start -2.0955 1.6891) (end -1.8415 1.3462) (layer F.SilkS) (width 0.15))
(fp_line (start -2.5019 1.7907) (end -2.0955 1.6891) (layer F.SilkS) (width 0.15))
(fp_line (start -2.8194 1.7399) (end -2.5019 1.7907) (layer F.SilkS) (width 0.15))
(fp_line (start -3.1115 1.5621) (end -2.8194 1.7399) (layer F.SilkS) (width 0.15))
(fp_line (start -3.3147 1.2065) (end -3.1115 1.5621) (layer F.SilkS) (width 0.15))
(fp_line (start -3.302 0.762) (end -3.3147 1.2065) (layer F.SilkS) (width 0.15))
(fp_line (start -3.0861 0.4445) (end -3.302 0.762) (layer F.SilkS) (width 0.15))
(fp_line (start -2.8067 0.2667) (end -3.0861 0.4445) (layer F.SilkS) (width 0.15))
(fp_line (start -2.5527 0.2286) (end -2.8067 0.2667) (layer F.SilkS) (width 0.15))
(fp_line (start -3.302 1.016) (end -2.032 1.016) (layer F.SilkS) (width 0.15))
(fp_line (start 0.635 -7.366) (end 0.635 -6.35) (layer F.SilkS) (width 0.15))
(fp_line (start 0.635 -3.81) (end 0.635 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 0.635 1.27) (end 0.635 2.286) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole circle (at 0 0 90) (size 1.524 1.524) (drill 0.8128) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 57 "Net-(R23-Pad1)"))
add balance poti
2017-08-28 22:59:34 +02:00
(pad 3 thru_hole circle (at 0 -5.08 90) (size 1.524 1.524) (drill 0.8128) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 59 "Net-(R24-Pad1)"))
add balance poti
2017-08-28 22:59:34 +02:00
(pad 2 thru_hole circle (at -2.54 -2.54 90) (size 1.524 1.524) (drill 0.8128) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
add balance poti
2017-08-28 22:59:34 +02:00
(model Potentiometers.3dshapes/Potentiometer_Bourns_3296Y_3-8Zoll_Angular_ScrewUp.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(module Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm (layer F.Cu) (tedit 5862ED52) (tstamp 59B450DD)
(at 38.5 56.5)
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /59B48619)
(fp_text reference TP5 (at -0.5 -2.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TEST (at 0 2.39) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.6 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.6 1.6) (end 1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 1.6) (end 1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.6) (end -1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.39 -1.39) (end 0 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 0) (end -1.39 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.27) (end -1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.39) (end 1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.39) (end 1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.27) (end -1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 27 "Net-(D1-Pad1)"))
last changes. Stream out
2017-09-09 23:11:00 +02:00
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x01_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
(module Pin_Headers:Pin_Header_Straight_1x01_Pitch2.54mm (layer F.Cu) (tedit 5862ED52) (tstamp 59B450E2)
(at 41.04 56.5)
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /59B47D65)
(fp_text reference TP6 (at 0.46 -2.5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TEST (at 0 2.39) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.6 -1.6) (end -1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.6 1.6) (end 1.6 -1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 1.6) (end 1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.6 -1.6) (end -1.6 1.6) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.39 -1.39) (end 0 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 0) (end -1.39 -1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.27) (end -1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.39 1.39) (end 1.39 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.39) (end 1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start -1.39 1.27) (end -1.39 1.39) (layer F.SilkS) (width 0.12))
(fp_line (start 1.27 -1.27) (end -1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 3 +5V))
(model Pin_Headers.3dshapes/Pin_Header_Straight_1x01_Pitch2.54mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 90))
)
)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(module tht:SIL7-reduced (layer F.Cu) (tedit 59B578F8) (tstamp 5978A9B4)
(at 54.5 38 90)
(path /5930537C)
(fp_text reference U2 (at -1.27 -3.81 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SIM2-XXXXD (at 3.81 -5.08 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 10.8 -1.4) (end 10.8 5.7) (layer F.SilkS) (width 0.15))
(fp_line (start -8.7 -1.4) (end 10.8 -1.4) (layer F.SilkS) (width 0.15))
(fp_line (start -8.7 5.7) (end 10.8 5.7) (layer F.SilkS) (width 0.15))
(fp_line (start -8.7 5.7) (end -8.7 -1.4) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole circle (at -6.35 0 90) (size 1.4 1.4) (drill 0.6) (layers *.Cu *.Mask)
(net 3 +5V))
(pad 2 thru_hole circle (at -3.81 0 90) (size 1.4 1.4) (drill 0.6) (layers *.Cu *.Mask)
(net 1 Earth))
(pad 4 thru_hole circle (at 1.27 0 90) (size 1.4 1.4) (drill 0.6) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 15 "Net-(C17-Pad2)"))
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(pad 5 thru_hole circle (at 3.81 0 90) (size 1.4 1.4) (drill 0.6) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 13 GNDPWR))
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(pad 6 thru_hole circle (at 6.35 0 90) (size 1.4 1.4) (drill 0.6) (layers *.Cu *.Mask)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(net 14 "Net-(C16-Pad1)"))
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 58AA848B) (tstamp 5A082C0C)
(at 28 42 180)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59D3ED93)
(attr smd)
(fp_text reference C45 (at -2.5 1 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 1.5 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 0.65) (end -1.8 0.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 0.65) (end 1.8 -0.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -0.65) (end -1.8 0.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -0.65) (end 1.8 -0.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.12))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.12))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_text user %R (at 0 -1.25 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 smd rect (at 0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 60 "Net-(C45-Pad2)"))
(pad 1 smd rect (at -0.95 0 180) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 61 "Net-(C45-Pad1)"))
(model Capacitors_SMD.3dshapes/C_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer B.Cu) (tedit 58AA848B) (tstamp 5A082C1D)
(at 17.01 48.27 90)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59D3F786)
(attr smd)
(fp_text reference C46 (at 0 1.25 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 1u (at 0 -1.5 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text user %R (at 0 1.25 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.35 0.6) (end 0.35 0.6) (layer B.SilkS) (width 0.12))
(fp_line (start 0.35 -0.6) (end -0.35 -0.6) (layer B.SilkS) (width 0.12))
(fp_line (start -1.8 0.65) (end 1.8 0.65) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.8 0.65) (end -1.8 -0.65) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 -0.65) (end 1.8 0.65) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.8 -0.65) (end -1.8 -0.65) (layer B.CrtYd) (width 0.05))
(pad 1 smd rect (at -0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 63 "Net-(C46-Pad1)"))
(pad 2 smd rect (at 0.95 0 90) (size 1.2 0.75) (layers B.Cu B.Paste B.Mask)
(net 62 "Net-(C46-Pad2)"))
(model Capacitors_SMD.3dshapes/C_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 58AA848B) (tstamp 5A082C2E)
(at 36 41.5 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59D41952)
(attr smd)
(fp_text reference C47 (at 0 -1.25 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 1.5 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 -1.25 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.12))
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -0.65) (end 1.8 -0.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -0.65) (end -1.8 0.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 0.65) (end 1.8 -0.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 0.65) (end -1.8 0.65) (layer F.CrtYd) (width 0.05))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 64 "Net-(C47-Pad1)"))
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 7 /LUSB))
(model Capacitors_SMD.3dshapes/C_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Capacitors_SMD:C_0603_HandSoldering (layer F.Cu) (tedit 58AA848B) (tstamp 5A082C3F)
(at 45 41.5 270)
(descr "Capacitor SMD 0603, hand soldering")
(tags "capacitor 0603")
(path /59D41856)
(attr smd)
(fp_text reference C48 (at 0 -1.25 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1u (at 0 1.5 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 0.65) (end -1.8 0.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 0.65) (end 1.8 -0.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -0.65) (end -1.8 0.65) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -0.65) (end 1.8 -0.65) (layer F.CrtYd) (width 0.05))
(fp_line (start 0.35 0.6) (end -0.35 0.6) (layer F.SilkS) (width 0.12))
(fp_line (start -0.35 -0.6) (end 0.35 -0.6) (layer F.SilkS) (width 0.12))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_text user %R (at 0 -1.25 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 2 smd rect (at 0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 11 /RUSB))
(pad 1 smd rect (at -0.95 0 270) (size 1.2 0.75) (layers F.Cu F.Paste F.Mask)
(net 12 "Net-(C15-Pad1)"))
(model Capacitors_SMD.3dshapes/C_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module LEDs:LED_D3.0mm_Horizontal_O1.27mm_Z2.0mm (layer F.Cu) (tedit 5880A862) (tstamp 5A082C69)
(at 19 18.5 270)
(descr "LED, diameter 3.0mm z-position of LED center 2.0mm, 2 pins")
(tags "LED diameter 3.0mm z-position of LED center 2.0mm 2 pins")
(path /59D4E851)
(fp_text reference D2 (at 0.79 -2.02 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 1.27 7.63 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 3.75 -1.25) (end -1.25 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.75 6.9) (end 3.75 -1.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 6.9) (end 3.75 6.9) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.25 -1.25) (end -1.25 6.9) (layer F.CrtYd) (width 0.05))
(fp_line (start 2.54 1.08) (end 2.54 1.08) (layer F.SilkS) (width 0.12))
(fp_line (start 2.54 1.21) (end 2.54 1.08) (layer F.SilkS) (width 0.12))
(fp_line (start 2.54 1.21) (end 2.54 1.21) (layer F.SilkS) (width 0.12))
(fp_line (start 2.54 1.08) (end 2.54 1.21) (layer F.SilkS) (width 0.12))
(fp_line (start 0 1.08) (end 0 1.08) (layer F.SilkS) (width 0.12))
(fp_line (start 0 1.21) (end 0 1.08) (layer F.SilkS) (width 0.12))
(fp_line (start 0 1.21) (end 0 1.21) (layer F.SilkS) (width 0.12))
(fp_line (start 0 1.08) (end 0 1.21) (layer F.SilkS) (width 0.12))
(fp_line (start 2.83 1.21) (end 3.23 1.21) (layer F.SilkS) (width 0.12))
(fp_line (start 2.83 2.33) (end 2.83 1.21) (layer F.SilkS) (width 0.12))
(fp_line (start 3.23 2.33) (end 2.83 2.33) (layer F.SilkS) (width 0.12))
(fp_line (start 3.23 1.21) (end 3.23 2.33) (layer F.SilkS) (width 0.12))
(fp_line (start -0.29 1.21) (end 2.83 1.21) (layer F.SilkS) (width 0.12))
(fp_line (start 2.83 1.21) (end 2.83 5.07) (layer F.SilkS) (width 0.12))
(fp_line (start -0.29 1.21) (end -0.29 5.07) (layer F.SilkS) (width 0.12))
(fp_line (start 2.54 0) (end 2.54 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 1.27) (end 2.54 0) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 1.27) (end 2.54 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 0) (end 2.54 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 0 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 1.27) (end 0 0) (layer F.Fab) (width 0.1))
(fp_line (start 0 1.27) (end 0 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0 0) (end 0 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.77 1.27) (end 3.17 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.77 2.27) (end 2.77 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 3.17 2.27) (end 2.77 2.27) (layer F.Fab) (width 0.1))
(fp_line (start 3.17 1.27) (end 3.17 2.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.23 1.27) (end 2.77 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.77 1.27) (end 2.77 5.07) (layer F.Fab) (width 0.1))
(fp_line (start -0.23 1.27) (end -0.23 5.07) (layer F.Fab) (width 0.1))
(fp_arc (start 1.27 5.07) (end -0.29 5.07) (angle -180) (layer F.SilkS) (width 0.12))
(fp_arc (start 1.27 5.07) (end -0.23 5.07) (angle -180) (layer F.Fab) (width 0.1))
(pad 2 thru_hole circle (at 2.54 0 270) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 65 "Net-(D2-Pad2)"))
(pad 1 thru_hole rect (at 0 0 270) (size 1.8 1.8) (drill 0.9) (layers *.Cu *.Mask)
(net 1 Earth))
(model ${KISYS3DMOD}/LEDs.3dshapes/LED_D3.0mm_Horizontal_O1.27mm_Z2.0mm.wrl
(at (xyz 0 0 0))
(scale (xyz 0.393701 0.393701 0.393701))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58E0A804) (tstamp 5A082C7A)
(at 32.25 25.5 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /59D4727F)
(attr smd)
(fp_text reference R25 (at 0 1.5 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k5 (at 0 1.55 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.95 0.7) (end -1.96 0.7) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.95 0.7) (end 1.95 -0.7) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.96 -0.7) (end -1.96 0.7) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.96 -0.7) (end 1.95 -0.7) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.5 -0.68) (end 0.5 -0.68) (layer F.SilkS) (width 0.12))
(fp_line (start 0.5 0.68) (end -0.5 0.68) (layer F.SilkS) (width 0.12))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.075)))
)
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 6 +3V3))
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 68 "Net-(R25-Pad1)"))
(model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58E0A804) (tstamp 5A082C8B)
(at 54.71 51 90)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /59D427C6)
(attr smd)
(fp_text reference R26 (at 0 1.45 90) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 330 (at 0 -1.55 90) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_line (start 1.95 -0.7) (end -1.96 -0.7) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.95 -0.7) (end 1.95 0.7) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.96 0.7) (end -1.96 -0.7) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.96 0.7) (end 1.95 0.7) (layer B.CrtYd) (width 0.05))
(fp_line (start -0.5 0.68) (end 0.5 0.68) (layer B.SilkS) (width 0.12))
(fp_line (start 0.5 -0.68) (end -0.5 -0.68) (layer B.SilkS) (width 0.12))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(fp_text user %R (at 0 0 90) (layer B.Fab)
(effects (font (size 0.4 0.4) (thickness 0.075)) (justify mirror))
)
(pad 2 smd rect (at 1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 13 GNDPWR))
(pad 1 smd rect (at -1.1 0 90) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 38 "Net-(K1-Pad3)"))
(model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer B.Cu) (tedit 58E0A804) (tstamp 5A082C9C)
(at 49.04 56.44 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /59D4423C)
(attr smd)
(fp_text reference R27 (at 0 -1.5 180) (layer B.SilkS)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text value 330 (at 0 -1.55 180) (layer B.Fab)
(effects (font (size 1 1) (thickness 0.15)) (justify mirror))
)
(fp_text user %R (at 0 0 180) (layer B.Fab)
(effects (font (size 0.4 0.4) (thickness 0.075)) (justify mirror))
)
(fp_line (start -0.8 -0.4) (end -0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end -0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end 0.8 -0.4) (layer B.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end 0.8 0.4) (layer B.Fab) (width 0.1))
(fp_line (start 0.5 -0.68) (end -0.5 -0.68) (layer B.SilkS) (width 0.12))
(fp_line (start -0.5 0.68) (end 0.5 0.68) (layer B.SilkS) (width 0.12))
(fp_line (start -1.96 0.7) (end 1.95 0.7) (layer B.CrtYd) (width 0.05))
(fp_line (start -1.96 0.7) (end -1.96 -0.7) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.95 -0.7) (end 1.95 0.7) (layer B.CrtYd) (width 0.05))
(fp_line (start 1.95 -0.7) (end -1.96 -0.7) (layer B.CrtYd) (width 0.05))
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 37 "Net-(K1-Pad6)"))
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers B.Cu B.Paste B.Mask)
(net 13 GNDPWR))
(model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
(module Resistors_SMD:R_0603_HandSoldering (layer F.Cu) (tedit 58E0A804) (tstamp 5A2A52ED)
(at 22.75 21 180)
(descr "Resistor SMD 0603, hand soldering")
(tags "resistor 0603")
(path /59D4DBF0)
(attr smd)
(fp_text reference R28 (at 0 -1.45 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.55 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.95 0.7) (end -1.96 0.7) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.95 0.7) (end 1.95 -0.7) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.96 -0.7) (end -1.96 0.7) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.96 -0.7) (end 1.95 -0.7) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.5 -0.68) (end 0.5 -0.68) (layer F.SilkS) (width 0.12))
(fp_line (start 0.5 0.68) (end -0.5 0.68) (layer F.SilkS) (width 0.12))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.075)))
)
(pad 2 smd rect (at 1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 65 "Net-(D2-Pad2)"))
(pad 1 smd rect (at -1.1 0 180) (size 1.2 0.9) (layers F.Cu F.Paste F.Mask)
(net 3 +5V))
(model ${KISYS3DMOD}/Resistors_SMD.3dshapes/R_0603.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(gr_text "High Fidelitity Headphone Amplifier\nMario Hüttel Aug. 2017" (at 73.25 18.25) (layer B.Mask)
(effects (font (size 1 1) (thickness 0.1875)) (justify mirror))
)
(gr_line (start 13 63.5) (end 13 13.5) (layer Edge.Cuts) (width 0.15))
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(gr_line (start 113 63.5) (end 13 63.5) (layer Edge.Cuts) (width 0.15))
(gr_line (start 113 13.5) (end 113 63.5) (layer Edge.Cuts) (width 0.15))
(gr_line (start 13 13.5) (end 113 13.5) (layer Edge.Cuts) (width 0.15))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(via (at 17.4 24.03) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 17.4 24.03) (end 17 23.500004) (width 0.25) (layer B.Cu) (net 1))
(segment (start 17 23.500004) (end 17 19.35) (width 0.25) (layer B.Cu) (net 1))
(segment (start 17.950076 24.04992) (end 20.35026 24.04992) (width 0.25) (layer F.Cu) (net 1))
(segment (start 17 19.35) (end 17.85 18.5) (width 0.25) (layer B.Cu) (net 1))
(segment (start 17.85 18.5) (end 19 18.5) (width 0.25) (layer B.Cu) (net 1))
(segment (start 17.4 24.03) (end 17.396443 24.25) (width 0.25) (layer B.Cu) (net 1))
(segment (start 17.396443 24.25) (end 16.750004 24.25) (width 0.25) (layer B.Cu) (net 1))
(segment (start 17.4 24.03) (end 17.950076 24.04992) (width 0.25) (layer F.Cu) (net 1))
(segment (start 16.750004 24.25) (end 14.75 26.250004) (width 0.25) (layer B.Cu) (net 1))
(segment (start 33.93 29.4) (end 37.9 29.4) (width 0.25) (layer B.Cu) (net 1))
(segment (start 37.9 29.4) (end 37.990001 29.490001) (width 0.25) (layer B.Cu) (net 1))
(segment (start 37.990001 29.490001) (end 38.24 29.74) (width 0.25) (layer B.Cu) (net 1))
(segment (start 34.05 30.025) (end 33.075 30.025) (width 0.25) (layer F.Cu) (net 1))
(segment (start 35.9 30.025) (end 34.05 30.025) (width 0.25) (layer F.Cu) (net 1))
(via (at 33.93 29.4) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 34.05 30.025) (end 34.05 29.52) (width 0.25) (layer F.Cu) (net 1))
(segment (start 34.05 29.52) (end 33.93 29.4) (width 0.25) (layer F.Cu) (net 1))
(segment (start 18.79 30.28) (end 18.79 30.79) (width 0.25) (layer F.Cu) (net 1))
(segment (start 18.79 30.79) (end 19.25 31.25) (width 0.25) (layer F.Cu) (net 1))
(segment (start 18.98 30.09) (end 18.79 30.28) (width 0.25) (layer F.Cu) (net 1))
(segment (start 19.0385 30.09) (end 18.98 30.09) (width 0.25) (layer F.Cu) (net 1))
(segment (start 20.44932 30.1002) (end 19.0487 30.1002) (width 0.25) (layer F.Cu) (net 1))
(segment (start 19.0487 30.1002) (end 19.0385 30.09) (width 0.25) (layer F.Cu) (net 1))
(segment (start 37.75 41.9) (end 39.63 41.9) (width 0.4) (layer B.Cu) (net 1))
(segment (start 39.63 41.9) (end 39.74 42.01) (width 0.4) (layer B.Cu) (net 1))
(segment (start 30.95 50.25) (end 30.95 51.3) (width 0.6) (layer F.Cu) (net 1))
(segment (start 30.95 51.3) (end 32.71 53.06) (width 0.6) (layer F.Cu) (net 1))
(segment (start 30.95 47.05) (end 30.95 39.25) (width 0.6) (layer B.Cu) (net 1))
(segment (start 30.95 39.25) (end 31.98 38.22) (width 0.6) (layer B.Cu) (net 1))
(segment (start 30.95 50.25) (end 30.95 47.05) (width 0.6) (layer B.Cu) (net 1))
(segment (start 28.49 38.18) (end 27.75 38.18) (width 1.5) (layer B.Cu) (net 1))
(segment (start 27.75 38.18) (end 22.91 38.18) (width 1.5) (layer B.Cu) (net 1))
(segment (start 27.75 40.65) (end 27.75 38.18) (width 0.6) (layer B.Cu) (net 1))
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(segment (start 56.5 42.1) (end 54.79 42.1) (width 0.8) (layer B.Cu) (net 1))
(segment (start 54.79 42.1) (end 54.5 41.81) (width 0.8) (layer B.Cu) (net 1))
(segment (start 48.89 42.11) (end 49.19 41.81) (width 0.4) (layer B.Cu) (net 1))
(segment (start 49.19 41.81) (end 54.5 41.81) (width 0.4) (layer B.Cu) (net 1))
(segment (start 54.5 41.81) (end 58.5 41.81) (width 0.4) (layer F.Cu) (net 1))
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(segment (start 61.775 50) (end 61.75 49.975) (width 0.6) (layer F.Cu) (net 1))
(segment (start 61.75 49.975) (end 61.75 43.25) (width 0.6) (layer F.Cu) (net 1))
(segment (start 61.75 43.25) (end 60.31 41.81) (width 0.6) (layer F.Cu) (net 1))
(segment (start 60.31 41.81) (end 58.5 41.81) (width 0.6) (layer F.Cu) (net 1))
(segment (start 22.5 34.5) (end 20.25 34.5) (width 0.4) (layer F.Cu) (net 1))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 14.749999 30.749999) (end 14.5 30.5) (width 0.25) (layer F.Cu) (net 1))
(segment (start 14.85116 30.85116) (end 14.749999 30.749999) (width 0.25) (layer F.Cu) (net 1))
(segment (start 14.85116 32.95008) (end 14.85116 30.85116) (width 0.25) (layer F.Cu) (net 1))
(segment (start 14.749999 30.749999) (end 14.5 30.5) (width 0.25) (layer B.Cu) (net 1))
(segment (start 15.609999 31.609999) (end 14.749999 30.749999) (width 0.25) (layer B.Cu) (net 1))
(segment (start 18.720001 31.609999) (end 15.609999 31.609999) (width 0.25) (layer B.Cu) (net 1))
(via (at 14.5 30.5) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 14.85116 26.148844) (end 14.75 26.250004) (width 0.25) (layer F.Cu) (net 1))
(segment (start 14.85116 24.04992) (end 14.85116 26.148844) (width 0.25) (layer F.Cu) (net 1))
(via (at 14.75 26.250004) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 20.35026 32.95008) (end 20.35026 31.60026) (width 0.4) (layer B.Cu) (net 1))
(segment (start 20.35026 31.60026) (end 20 31.25) (width 0.4) (layer B.Cu) (net 1))
(segment (start 18.720001 31.609999) (end 18.890001 31.609999) (width 0.4) (layer B.Cu) (net 1))
(segment (start 18.890001 31.609999) (end 19.25 31.25) (width 0.4) (layer B.Cu) (net 1))
(segment (start 20 31.25) (end 19.25 31.25) (width 0.8) (layer F.Cu) (net 1))
(via (at 19.25 31.25) (size 0.7) (drill 0.4) (layers F.Cu B.Cu) (net 1))
(segment (start 20.75 31.25) (end 21.5 31.25) (width 0.8) (layer F.Cu) (net 1))
(via (at 21.5 31.25) (size 0.7) (drill 0.4) (layers F.Cu B.Cu) (net 1))
(via (at 20.75 31.25) (size 0.7) (drill 0.4) (layers F.Cu B.Cu) (net 1))
(segment (start 20.44932 31.25) (end 20.75 31.25) (width 0.8) (layer F.Cu) (net 1))
(segment (start 20.44932 31.25) (end 20.44932 32.85102) (width 0.4) (layer F.Cu) (net 1))
(segment (start 20.44932 31.25) (end 20 31.25) (width 0.8) (layer F.Cu) (net 1))
(segment (start 20.44932 30.1002) (end 20.44932 31.25) (width 0.4) (layer F.Cu) (net 1))
(via (at 20 31.25) (size 0.7) (drill 0.4) (layers F.Cu B.Cu) (net 1))
(segment (start 20.44932 32.85102) (end 20.35026 32.95008) (width 0.4) (layer F.Cu) (net 1))
(segment (start 37.96 33.12) (end 37.710001 32.870001) (width 0.4) (layer B.Cu) (net 1))
(segment (start 37.710001 32.870001) (end 37.630001 32.870001) (width 0.4) (layer B.Cu) (net 1))
(segment (start 37.630001 32.870001) (end 37.4 32.64) (width 0.4) (layer B.Cu) (net 1))
(segment (start 38.55 34.5) (end 38.55 33.24) (width 0.4) (layer B.Cu) (net 1))
(segment (start 38.55 33.24) (end 38.43 33.12) (width 0.4) (layer B.Cu) (net 1))
(segment (start 38.43 33.12) (end 37.96 33.12) (width 0.4) (layer B.Cu) (net 1))
(segment (start 37.4 32.64) (end 37.4 30.58) (width 0.25) (layer B.Cu) (net 1))
(segment (start 35.75 32.64) (end 36.525 32.64) (width 0.4) (layer B.Cu) (net 1))
(segment (start 36.525 32.64) (end 37.4 32.64) (width 0.4) (layer B.Cu) (net 1))
(segment (start 37.990001 29.989999) (end 38.24 29.74) (width 0.25) (layer B.Cu) (net 1))
(segment (start 37.4 30.58) (end 37.990001 29.989999) (width 0.25) (layer B.Cu) (net 1))
(segment (start 38.489999 29.490001) (end 38.24 29.74) (width 0.25) (layer B.Cu) (net 1))
(segment (start 39.26 28.72) (end 38.489999 29.490001) (width 0.25) (layer B.Cu) (net 1))
(segment (start 37.955 30.025) (end 37.990001 29.989999) (width 0.25) (layer F.Cu) (net 1))
(segment (start 35.9 30.025) (end 37.955 30.025) (width 0.25) (layer F.Cu) (net 1))
(segment (start 37.990001 29.989999) (end 38.24 29.74) (width 0.25) (layer F.Cu) (net 1))
(segment (start 39.26 18.54) (end 39.26 28.72) (width 0.25) (layer B.Cu) (net 1))
(via (at 38.24 29.74) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 32.7 53.05) (end 32.71 53.06) (width 0.4) (layer F.Cu) (net 1))
(segment (start 37.61 38.27) (end 35.5 38.27) (width 1.5) (layer B.Cu) (net 1))
(segment (start 35.5 38.27) (end 28.58 38.27) (width 1.5) (layer B.Cu) (net 1))
(segment (start 44.43 37.65) (end 43.5 37.65) (width 1.5) (layer B.Cu) (net 1))
(segment (start 43.5 37.65) (end 38.23 37.65) (width 1.5) (layer B.Cu) (net 1))
(segment (start 43.5 40.9) (end 43.5 37.65) (width 0.4) (layer B.Cu) (net 1))
(segment (start 48.89 42.11) (end 44.43 37.65) (width 0.4) (layer B.Cu) (net 1))
(segment (start 35.9 33.925) (end 33.575 33.925) (width 0.4) (layer F.Cu) (net 1))
(segment (start 33.575 33.925) (end 33.5 33.85) (width 0.4) (layer F.Cu) (net 1))
(via (at 33.5 33.85) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 33.5 33.5) (end 33.5 33.85) (width 0.4) (layer F.Cu) (net 1))
(segment (start 34.4 33.5) (end 33.5 33.5) (width 0.4) (layer F.Cu) (net 1))
(segment (start 35.9 33.275) (end 34.625 33.275) (width 0.4) (layer F.Cu) (net 1))
(segment (start 34.625 33.275) (end 34.4 33.5) (width 0.4) (layer F.Cu) (net 1))
(segment (start 20.35026 35.62026) (end 20.35026 34.5) (width 1.5) (layer B.Cu) (net 1))
(segment (start 20.35026 34.5) (end 20.35026 32.95008) (width 1.5) (layer B.Cu) (net 1))
(segment (start 22.5 34.5) (end 20.35026 34.5) (width 0.6) (layer B.Cu) (net 1))
(segment (start 22.5 34.5) (end 24.5 34.5) (width 0.6) (layer B.Cu) (net 1))
(segment (start 24.55 35.5) (end 24.55 34.55) (width 0.6) (layer F.Cu) (net 1))
(segment (start 24.55 34.55) (end 24.5 34.5) (width 0.6) (layer F.Cu) (net 1))
(via (at 24.5 34.5) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 22.45 35.5) (end 22.45 34.55) (width 0.6) (layer F.Cu) (net 1))
(segment (start 22.45 34.55) (end 22.5 34.5) (width 0.6) (layer F.Cu) (net 1))
(via (at 22.5 34.5) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 31.98 38.22) (end 31.060762 38.22) (width 0.4) (layer B.Cu) (net 1))
(segment (start 31.060762 38.22) (end 31.010762 38.27) (width 0.4) (layer B.Cu) (net 1))
(segment (start 31.010762 38.27) (end 28.58 38.27) (width 0.4) (layer B.Cu) (net 1))
(segment (start 35.9 33.275) (end 37.805 33.275) (width 0.25) (layer F.Cu) (net 1))
(via (at 37.96 33.12) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 37.805 33.275) (end 37.96 33.12) (width 0.25) (layer F.Cu) (net 1))
(segment (start 20.60045 32.95008) (end 20.35026 32.95008) (width 0.25) (layer B.Cu) (net 1))
(segment (start 22.91 38.18) (end 20.35026 35.62026) (width 1.5) (layer B.Cu) (net 1))
(segment (start 38.23 37.65) (end 37.61 38.27) (width 1.5) (layer B.Cu) (net 1))
(segment (start 43.1 32.625) (end 41.095 32.625) (width 0.25) (layer F.Cu) (net 1))
(segment (start 40.879999 33.339999) (end 40.63 33.09) (width 0.25) (layer B.Cu) (net 1))
(segment (start 40.99 33.45) (end 40.879999 33.339999) (width 0.25) (layer B.Cu) (net 1))
(segment (start 38.775 34.5) (end 40.185 33.09) (width 0.25) (layer B.Cu) (net 1))
(segment (start 40.879999 32.840001) (end 40.63 33.09) (width 0.25) (layer F.Cu) (net 1))
(segment (start 40.185 33.09) (end 40.276447 33.09) (width 0.25) (layer B.Cu) (net 1))
(segment (start 41.465 33.925) (end 40.879999 33.339999) (width 0.25) (layer F.Cu) (net 1))
(segment (start 41.095 32.625) (end 40.879999 32.840001) (width 0.25) (layer F.Cu) (net 1))
(segment (start 40.879999 33.339999) (end 40.63 33.09) (width 0.25) (layer F.Cu) (net 1))
(segment (start 42.5 33.45) (end 40.99 33.45) (width 0.25) (layer B.Cu) (net 1))
(segment (start 43.1 33.925) (end 41.465 33.925) (width 0.25) (layer F.Cu) (net 1))
(segment (start 38.55 34.5) (end 38.775 34.5) (width 0.25) (layer B.Cu) (net 1))
(segment (start 40.276447 33.09) (end 40.63 33.09) (width 0.25) (layer B.Cu) (net 1))
(via (at 40.63 33.09) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 46 34.95) (end 45.375 34.95) (width 0.25) (layer F.Cu) (net 1))
(segment (start 45.375 34.95) (end 44.35 33.925) (width 0.25) (layer F.Cu) (net 1))
(segment (start 44.35 33.925) (end 44.225 33.925) (width 0.25) (layer F.Cu) (net 1))
(segment (start 44.225 33.925) (end 43.1 33.925) (width 0.25) (layer F.Cu) (net 1))
(segment (start 39.26 18.54) (end 38.7 18.54) (width 0.25) (layer B.Cu) (net 1))
(segment (start 39.78 18.54) (end 39.26 18.54) (width 0.25) (layer B.Cu) (net 1))
(segment (start 38.7 18.54) (end 38.67 18.57) (width 0.25) (layer B.Cu) (net 1))
(segment (start 40.55 17.5) (end 40.55 17.77) (width 0.25) (layer F.Cu) (net 1))
(segment (start 40.55 17.77) (end 39.78 18.54) (width 0.25) (layer F.Cu) (net 1))
(via (at 39.78 18.54) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 38.45 17.5) (end 38.45 18.35) (width 0.25) (layer F.Cu) (net 1))
(segment (start 38.45 18.35) (end 38.67 18.57) (width 0.25) (layer F.Cu) (net 1))
(via (at 38.67 18.57) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 38.23 35.445) (end 38.23 37.65) (width 0.25) (layer B.Cu) (net 1))
(segment (start 38.23 37.65) (end 38.23 40.5) (width 0.25) (layer B.Cu) (net 1))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 33.075 30.025) (end 32.5 29.45) (width 0.25) (layer F.Cu) (net 1))
(segment (start 38.55 34.5) (end 38.55 35.125) (width 0.25) (layer B.Cu) (net 1))
(segment (start 38.55 35.125) (end 38.23 35.445) (width 0.25) (layer B.Cu) (net 1))
(segment (start 39.74 42.01) (end 38.23 40.5) (width 0.25) (layer B.Cu) (net 1))
(segment (start 39.71 42.45) (end 41 42.45) (width 0.25) (layer F.Cu) (net 1))
(segment (start 39.125 42.45) (end 39.71 42.45) (width 0.25) (layer F.Cu) (net 1))
(segment (start 39.71 42.45) (end 39.71 42.04) (width 0.25) (layer F.Cu) (net 1))
(segment (start 39.71 42.04) (end 39.74 42.01) (width 0.25) (layer F.Cu) (net 1))
(via (at 39.74 42.01) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 1))
(segment (start 38.5 42.45) (end 39.125 42.45) (width 0.25) (layer F.Cu) (net 1))
(segment (start 28.49 38.18) (end 28.58 38.27) (width 0.6) (layer B.Cu) (net 1))
(segment (start 20.35026 35.62026) (end 23 38.27) (width 0.6) (layer B.Cu) (net 1))
(segment (start 23 38.27) (end 28.58 38.27) (width 0.6) (layer B.Cu) (net 1))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(segment (start 31.98 36.22) (end 31.98 33.32) (width 0.4) (layer F.Cu) (net 2))
(segment (start 31.98 33.32) (end 32.675 32.625) (width 0.4) (layer F.Cu) (net 2))
(segment (start 26.9036 38.5) (end 26.9036 35.9536) (width 0.6) (layer F.Cu) (net 2))
(segment (start 26.9036 35.9536) (end 26.45 35.5) (width 0.6) (layer F.Cu) (net 2))
(segment (start 26.9036 38.5) (end 29.7 38.5) (width 0.6) (layer F.Cu) (net 2))
(segment (start 29.7 38.5) (end 31.98 36.22) (width 0.6) (layer F.Cu) (net 2))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 35.9 32.625) (end 32.675 32.625) (width 0.25) (layer F.Cu) (net 2))
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(segment (start 20.56 59.03) (end 20.0964 58.5664) (width 0.8) (layer F.Cu) (net 3))
(segment (start 20.0964 58.5664) (end 20.0964 38.5) (width 0.8) (layer F.Cu) (net 3))
(segment (start 20.0964 38.5) (end 17.22 38.5) (width 0.8) (layer F.Cu) (net 3))
(segment (start 17.22 38.5) (end 16.35 37.63) (width 0.8) (layer F.Cu) (net 3))
(segment (start 16.35 37.63) (end 16.35 31.749221) (width 0.8) (layer F.Cu) (net 3))
(segment (start 15.73 30.984121) (end 16.35 31.749221) (width 0.6) (layer F.Cu) (net 3))
(segment (start 20.44932 26.8998) (end 17.7302 26.8998) (width 0.6) (layer F.Cu) (net 3))
(segment (start 17.7302 26.8998) (end 15.9 28.73) (width 0.6) (layer F.Cu) (net 3))
(segment (start 15.9 28.73) (end 15.9 29.91) (width 0.6) (layer F.Cu) (net 3))
(segment (start 15.9 29.91) (end 15.73 30.08) (width 0.6) (layer F.Cu) (net 3))
(segment (start 15.73 30.08) (end 15.73 30.984121) (width 0.6) (layer F.Cu) (net 3))
(segment (start 20.44932 26.8998) (end 21.34975 26.8998) (width 0.25) (layer F.Cu) (net 3))
(segment (start 21.34975 26.8998) (end 23.85 24.39955) (width 0.25) (layer F.Cu) (net 3))
(segment (start 23.85 24.39955) (end 23.85 21) (width 0.25) (layer F.Cu) (net 3))
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(segment (start 54.5 44.35) (end 56.15 44.35) (width 0.8) (layer B.Cu) (net 3))
(segment (start 56.15 44.35) (end 56.5 44) (width 0.8) (layer B.Cu) (net 3))
(segment (start 54.225 48.625) (end 54.5 48.35) (width 0.4) (layer F.Cu) (net 3))
(segment (start 54.5 48.35) (end 54.5 44.35) (width 0.4) (layer F.Cu) (net 3))
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(segment (start 39.61 59.03) (end 45.21 59.03) (width 0.8) (layer F.Cu) (net 3))
(segment (start 45.21 59.03) (end 44.34 58.16) (width 0.8) (layer F.Cu) (net 3))
(segment (start 44.34 58.16) (end 52.5 50) (width 0.8) (layer F.Cu) (net 3))
(segment (start 52.5 50) (end 54.225 50) (width 0.8) (layer F.Cu) (net 3))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 20.56 59.03) (end 39.61 59.03) (width 0.8) (layer F.Cu) (net 3))
(segment (start 39.66 58.98) (end 39.61 59.03) (width 0.8) (layer F.Cu) (net 3))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(segment (start 20.0964 38.5) (end 20.0964 35.9536) (width 0.6) (layer F.Cu) (net 3))
(segment (start 20.0964 35.9536) (end 20.55 35.5) (width 0.6) (layer F.Cu) (net 3))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 54.225 50) (end 54.225 48.625) (width 0.8) (layer F.Cu) (net 3))
(segment (start 37.3 36.18) (end 37.3 34.7) (width 0.4) (layer F.Cu) (net 4))
(segment (start 37.3 34.7) (end 37.175 34.575) (width 0.4) (layer F.Cu) (net 4))
(segment (start 37.175 34.575) (end 35.9 34.575) (width 0.4) (layer F.Cu) (net 4))
(segment (start 35.75 34.54) (end 35.75 34.63) (width 0.4) (layer B.Cu) (net 4))
(via (at 37.3 36.18) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 4))
(segment (start 35.75 34.63) (end 37.3 36.18) (width 0.4) (layer B.Cu) (net 4))
(segment (start 35.9 26.775) (end 35.9 26.3) (width 0.25) (layer F.Cu) (net 5))
(segment (start 35.9 26.3) (end 36.85085 25.34915) (width 0.25) (layer F.Cu) (net 5))
(segment (start 36.85085 25.34915) (end 36.85085 24.5) (width 0.25) (layer F.Cu) (net 5))
(segment (start 34.65114 21) (end 34.65114 22.30029) (width 0.25) (layer F.Cu) (net 5))
(segment (start 34.65114 22.30029) (end 36.85085 24.5) (width 0.25) (layer F.Cu) (net 5))
(segment (start 36.85085 24.5) (end 37.55 24.5) (width 0.25) (layer F.Cu) (net 5))
(segment (start 37.55 24.5) (end 38.4 24.5) (width 0.25) (layer F.Cu) (net 5))
(segment (start 34.65114 21) (end 34.65114 19.17386) (width 0.25) (layer F.Cu) (net 5))
(segment (start 34.65114 19.17386) (end 36.325 17.5) (width 0.25) (layer F.Cu) (net 5))
(segment (start 36.325 17.5) (end 36.55 17.5) (width 0.25) (layer F.Cu) (net 5))
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(segment (start 32.5 27.55) (end 31.875 27.55) (width 0.25) (layer F.Cu) (net 6))
(segment (start 31.15 26.2) (end 31.15 25.5) (width 0.25) (layer F.Cu) (net 6))
(segment (start 31.875 27.55) (end 31.15 26.825) (width 0.25) (layer F.Cu) (net 6))
(segment (start 31.15 26.825) (end 31.15 26.2) (width 0.25) (layer F.Cu) (net 6))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(segment (start 41.4 28.075) (end 43.1 28.075) (width 0.25) (layer F.Cu) (net 6))
(segment (start 40.315 28.075) (end 41.4 28.075) (width 0.4) (layer F.Cu) (net 6))
(segment (start 41.42 28.725) (end 39.835 28.725) (width 0.4) (layer F.Cu) (net 6))
(segment (start 43.1 28.725) (end 41.42 28.725) (width 0.25) (layer F.Cu) (net 6))
(segment (start 39.835 28.725) (end 39.75 28.64) (width 0.4) (layer F.Cu) (net 6))
(segment (start 38.685 31.325) (end 38.035 30.675) (width 0.4) (layer F.Cu) (net 6))
(segment (start 39.75 31.325) (end 38.685 31.325) (width 0.4) (layer F.Cu) (net 6))
(segment (start 39.75 31.325) (end 40.97 31.325) (width 0.4) (layer F.Cu) (net 6))
(segment (start 39.75 30.96) (end 39.75 31.325) (width 0.4) (layer F.Cu) (net 6))
(segment (start 39.75 30.96) (end 39.75 28.79) (width 0.25) (layer F.Cu) (net 6))
(segment (start 39.75 28.64) (end 39.75 30.96) (width 0.4) (layer F.Cu) (net 6))
(segment (start 40.315 28.075) (end 39.75 28.64) (width 0.4) (layer F.Cu) (net 6))
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(segment (start 38.035 30.675) (end 35.9 30.675) (width 0.25) (layer F.Cu) (net 6))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(segment (start 39.815 28.725) (end 39.75 28.79) (width 0.25) (layer F.Cu) (net 6))
(segment (start 39.75 28.79) (end 39.75 28.64) (width 0.25) (layer F.Cu) (net 6))
(segment (start 43.1 31.325) (end 40.97 31.325) (width 0.25) (layer F.Cu) (net 6))
(segment (start 28.570001 28.079999) (end 28.82 27.83) (width 0.25) (layer B.Cu) (net 6))
(segment (start 27.15 29.5) (end 28.570001 28.079999) (width 0.25) (layer B.Cu) (net 6))
(segment (start 26.1 29.5) (end 27.15 29.5) (width 0.25) (layer B.Cu) (net 6))
(segment (start 29.1 27.55) (end 29.069999 27.580001) (width 0.25) (layer F.Cu) (net 6))
(segment (start 29.069999 27.580001) (end 28.82 27.83) (width 0.25) (layer F.Cu) (net 6))
(segment (start 32.5 27.55) (end 29.1 27.55) (width 0.25) (layer F.Cu) (net 6))
(via (at 28.82 27.83) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 6))
(segment (start 32.5 27.775) (end 33.535 27.775) (width 0.25) (layer F.Cu) (net 6))
(segment (start 33.535 27.775) (end 34.485 28.725) (width 0.25) (layer F.Cu) (net 6))
(segment (start 34.485 28.725) (end 34.775 28.725) (width 0.25) (layer F.Cu) (net 6))
(segment (start 34.775 28.725) (end 35.9 28.725) (width 0.25) (layer F.Cu) (net 6))
(segment (start 35.9 30.675) (end 31.465 30.675) (width 0.25) (layer F.Cu) (net 6))
(segment (start 31.705 27.775) (end 32.5 27.775) (width 0.25) (layer F.Cu) (net 6))
(segment (start 31.465 30.675) (end 31.26 30.47) (width 0.25) (layer F.Cu) (net 6))
(segment (start 31.26 30.47) (end 31.26 28.22) (width 0.25) (layer F.Cu) (net 6))
(segment (start 31.26 28.22) (end 31.705 27.775) (width 0.25) (layer F.Cu) (net 6))
(segment (start 32.5 27.55) (end 32.5 27.775) (width 0.25) (layer F.Cu) (net 6))
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(segment (start 36 42.45) (end 34 42.45) (width 0.4) (layer F.Cu) (net 7))
(segment (start 36 43.24) (end 36 42.45) (width 0.4) (layer F.Cu) (net 7))
(segment (start 45.44 44.37) (end 45 43.93) (width 0.4) (layer F.Cu) (net 11))
(segment (start 45 43.93) (end 45 42.45) (width 0.4) (layer F.Cu) (net 11))
(segment (start 45.44 44.37) (end 45.44 48.66) (width 0.4) (layer F.Cu) (net 11))
(segment (start 45.44 48.66) (end 43.9 50.2) (width 0.4) (layer F.Cu) (net 11))
(segment (start 43 42.45) (end 45 42.45) (width 0.4) (layer F.Cu) (net 11))
(segment (start 43 40.55) (end 45 40.55) (width 0.4) (layer F.Cu) (net 12))
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(segment (start 108.5 21.3) (end 110.5 21.3) (width 0.6) (layer B.Cu) (net 13))
(segment (start 101.760002 37.239998) (end 101.760002 29.039998) (width 0.6) (layer B.Cu) (net 13))
(segment (start 101.760002 29.039998) (end 107.250001 23.549999) (width 0.6) (layer B.Cu) (net 13))
(segment (start 107.250001 23.549999) (end 107.250001 22.549999) (width 0.6) (layer B.Cu) (net 13))
(segment (start 107.250001 22.549999) (end 108.5 21.3) (width 0.6) (layer B.Cu) (net 13))
(segment (start 84.225 43.1) (end 83.891386 43.1) (width 0.4) (layer B.Cu) (net 13))
(segment (start 83.891386 43.1) (end 82.8 44.191386) (width 0.4) (layer B.Cu) (net 13))
(segment (start 85 42.1) (end 85 42.325) (width 0.4) (layer B.Cu) (net 13))
(segment (start 82.8 44.191386) (end 82.8 44.193998) (width 0.4) (layer B.Cu) (net 13))
(segment (start 85 42.325) (end 84.225 43.1) (width 0.4) (layer B.Cu) (net 13))
(segment (start 81.16 45.98) (end 81.225 45.98) (width 0.25) (layer B.Cu) (net 13))
(segment (start 81.225 45.98) (end 82.8 47.555) (width 0.25) (layer B.Cu) (net 13))
(segment (start 84.52 46.01) (end 81.19 46.01) (width 0.25) (layer F.Cu) (net 13))
(segment (start 81.19 46.01) (end 81.16 45.98) (width 0.25) (layer F.Cu) (net 13))
(via (at 81.16 45.98) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 13))
(segment (start 84.52 46.01) (end 84.345 46.01) (width 0.25) (layer F.Cu) (net 13))
(segment (start 84.345 46.01) (end 82.8 47.555) (width 0.25) (layer F.Cu) (net 13))
(segment (start 84.82 47.555) (end 90.07 47.555) (width 1.5) (layer B.Cu) (net 13))
(segment (start 82.8 47.555) (end 84.82 47.555) (width 1.5) (layer B.Cu) (net 13))
(segment (start 84.82 47.555) (end 84.82 46.31) (width 0.25) (layer B.Cu) (net 13))
(segment (start 84.82 46.31) (end 84.52 46.01) (width 0.25) (layer B.Cu) (net 13))
(via (at 84.52 46.01) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 13))
(segment (start 84.13 49.58) (end 82.8 48.25) (width 0.25) (layer F.Cu) (net 13))
(segment (start 82.8 48.25) (end 82.8 47.555) (width 0.25) (layer F.Cu) (net 13))
(segment (start 82.8 49.69) (end 84.02 49.69) (width 0.25) (layer B.Cu) (net 13))
(segment (start 84.02 49.69) (end 84.13 49.58) (width 0.25) (layer B.Cu) (net 13))
(via (at 84.13 49.58) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 13))
(segment (start 82.8 47.555) (end 82.8 49.69) (width 0.4) (layer B.Cu) (net 13))
(segment (start 82.8 49.69) (end 82.8 55.2) (width 0.4) (layer B.Cu) (net 13))
(segment (start 81.74 49.63) (end 82.093553 49.63) (width 0.25) (layer B.Cu) (net 13))
(segment (start 82.093553 49.63) (end 82.153553 49.69) (width 0.25) (layer B.Cu) (net 13))
(segment (start 82.153553 49.69) (end 82.8 49.69) (width 0.25) (layer B.Cu) (net 13))
(segment (start 82.8 47.555) (end 82.8 48.57) (width 0.25) (layer F.Cu) (net 13))
(segment (start 82.8 48.57) (end 81.74 49.63) (width 0.25) (layer F.Cu) (net 13))
(via (at 81.74 49.63) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 13))
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(segment (start 57.06 51.55) (end 57.06 53.300004) (width 0.25) (layer B.Cu) (net 13))
(segment (start 57.06 53.300004) (end 56.350004 54.01) (width 0.25) (layer B.Cu) (net 13))
(segment (start 54.71 49.9) (end 55.41 49.9) (width 0.25) (layer B.Cu) (net 13))
(segment (start 55.41 49.9) (end 57.06 51.55) (width 0.25) (layer B.Cu) (net 13))
(segment (start 34.17 60.05) (end 48.04 60.05) (width 1.5) (layer B.Cu) (net 13))
(segment (start 48.04 60.05) (end 50.22 60.05) (width 1.5) (layer B.Cu) (net 13))
(segment (start 47.94 57.14) (end 48.04 57.24) (width 0.25) (layer B.Cu) (net 13))
(segment (start 47.94 56.44) (end 47.94 57.14) (width 0.25) (layer B.Cu) (net 13))
(segment (start 48.04 57.24) (end 48.04 60.05) (width 0.25) (layer B.Cu) (net 13))
(segment (start 33.15 50.25) (end 33.15 53.73) (width 0.8) (layer B.Cu) (net 13))
(segment (start 33.15 53.73) (end 30.5 56.38) (width 0.8) (layer B.Cu) (net 13))
(segment (start 33.15 47.05) (end 33.15 50.25) (width 0.8) (layer B.Cu) (net 13))
(segment (start 62.13 35.35) (end 62.13 33.37) (width 0.8) (layer F.Cu) (net 15))
(segment (start 62.13 33.37) (end 64.5 31) (width 0.8) (layer F.Cu) (net 15))
(segment (start 54.5 36.73) (end 60.50108 36.73) (width 0.8) (layer F.Cu) (net 15))
(segment (start 60.50108 36.73) (end 61.88108 35.35) (width 0.8) (layer F.Cu) (net 15))
(segment (start 61.88108 35.35) (end 62.13 35.35) (width 0.8) (layer F.Cu) (net 15))
(segment (start 67.21 35.35) (end 67.21 54.002) (width 0.8) (layer F.Cu) (net 20))
(segment (start 67.21 54.002) (end 69.342 56.134) (width 0.8) (layer F.Cu) (net 20))
(segment (start 69.5 36.2) (end 68.06 36.2) (width 0.8) (layer F.Cu) (net 20))
(segment (start 68.06 36.2) (end 67.21 35.35) (width 0.8) (layer F.Cu) (net 20))
(segment (start 70.5 36.4036) (end 69.7036 36.4036) (width 0.8) (layer F.Cu) (net 20))
(segment (start 69.7036 36.4036) (end 69.5 36.2) (width 0.8) (layer F.Cu) (net 20))
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(segment (start 95.88 42.5) (end 94.173614 44.206386) (width 0.6) (layer B.Cu) (net 24))
(segment (start 94.173614 44.206386) (end 93.243614 44.206386) (width 0.6) (layer B.Cu) (net 24))
(segment (start 96 42.5) (end 95.88 42.5) (width 0.6) (layer B.Cu) (net 24))
(segment (start 85 44) (end 85.975 44) (width 0.6) (layer B.Cu) (net 24))
(segment (start 85.975 44) (end 86.181386 44.206386) (width 0.6) (layer B.Cu) (net 24))
(segment (start 86.181386 44.206386) (end 93.243614 44.206386) (width 0.6) (layer B.Cu) (net 24))
(segment (start 83.319999 42.939999) (end 82.92 42.54) (width 0.6) (layer F.Cu) (net 24))
(segment (start 83.916386 44.206386) (end 83.916386 43.536386) (width 0.6) (layer F.Cu) (net 24))
(segment (start 83.916386 43.536386) (end 83.319999 42.939999) (width 0.6) (layer F.Cu) (net 24))
(segment (start 87.5 44.38) (end 84.09 44.38) (width 0.6) (layer F.Cu) (net 24))
(segment (start 84.09 44.38) (end 83.916386 44.206386) (width 0.6) (layer F.Cu) (net 24))
(segment (start 78.1 44.38) (end 81.56 44.38) (width 0.6) (layer F.Cu) (net 24))
(segment (start 81.56 44.38) (end 82.05 43.89) (width 0.6) (layer F.Cu) (net 24))
(segment (start 82.92 42.54) (end 82.92 43.02) (width 0.6) (layer F.Cu) (net 24))
(segment (start 82.92 43.02) (end 82.05 43.89) (width 0.6) (layer F.Cu) (net 24))
(segment (start 82.92 42.54) (end 82.92 43.02) (width 0.6) (layer B.Cu) (net 24))
(segment (start 82.92 43.02) (end 82.05 43.89) (width 0.6) (layer B.Cu) (net 24))
(segment (start 83.86 44.16) (end 83.87 44.16) (width 0.4) (layer B.Cu) (net 24))
(segment (start 83.319999 42.140001) (end 82.92 42.54) (width 0.8) (layer B.Cu) (net 24))
(segment (start 83.75 41.71) (end 83.319999 42.140001) (width 0.8) (layer B.Cu) (net 24))
(segment (start 84.482071 44.206386) (end 83.916386 44.206386) (width 0.4) (layer B.Cu) (net 24))
(segment (start 84.122772 44) (end 83.916386 44.206386) (width 0.4) (layer B.Cu) (net 24))
(segment (start 85 44) (end 84.122772 44) (width 0.4) (layer B.Cu) (net 24))
(segment (start 83.87 44.16) (end 83.916386 44.206386) (width 0.4) (layer B.Cu) (net 24))
(segment (start 78.1 44.38) (end 80.99 44.38) (width 0.4) (layer F.Cu) (net 24))
(segment (start 83.75 39.25) (end 83.75 41.71) (width 0.8) (layer B.Cu) (net 24))
(via (at 83.916386 44.206386) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 24))
(via (at 82.92 42.54) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 24))
(segment (start 93.243614 44.206386) (end 84.482071 44.206386) (width 0.4) (layer B.Cu) (net 24))
(via (at 82.05 43.89) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 24))
(segment (start 81.599999 41.540001) (end 81.3 41.84) (width 0.4) (layer F.Cu) (net 26))
(segment (start 87.5 41.84) (end 86.125 41.84) (width 0.4) (layer F.Cu) (net 26))
(segment (start 86.125 41.84) (end 85.825001 41.540001) (width 0.4) (layer F.Cu) (net 26))
(segment (start 85.825001 41.540001) (end 81.599999 41.540001) (width 0.4) (layer F.Cu) (net 26))
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(segment (start 38.5 56.5) (end 38.5 54.75) (width 0.6) (layer F.Cu) (net 27))
(segment (start 48 51.75) (end 49.25 50.5) (width 0.6) (layer F.Cu) (net 27))
(segment (start 38.5 54.75) (end 41.5 51.75) (width 0.6) (layer F.Cu) (net 27))
(segment (start 49.25 47.75) (end 48.5 47) (width 0.6) (layer F.Cu) (net 27))
(segment (start 41.5 51.75) (end 48 51.75) (width 0.6) (layer F.Cu) (net 27))
(segment (start 49.25 50.5) (end 49.25 47.75) (width 0.6) (layer F.Cu) (net 27))
(segment (start 48.5 47) (end 47.1 47) (width 0.6) (layer F.Cu) (net 27))
(segment (start 32.71 56.36) (end 31.51 56.36) (width 0.6) (layer F.Cu) (net 27))
(segment (start 31.51 56.36) (end 27.75 52.6) (width 0.6) (layer F.Cu) (net 27))
(segment (start 27.75 52.6) (end 27.75 51.31066) (width 0.6) (layer F.Cu) (net 27))
(segment (start 27.75 51.31066) (end 27.75 50.25) (width 0.6) (layer F.Cu) (net 27))
(segment (start 22.45 50.7) (end 22.45 49.35) (width 0.6) (layer F.Cu) (net 31))
(segment (start 33.55 45.25) (end 34.600001 46.300001) (width 0.6) (layer F.Cu) (net 31))
(segment (start 22.45 49.35) (end 26.55 45.25) (width 0.6) (layer F.Cu) (net 31))
(segment (start 26.55 45.25) (end 33.55 45.25) (width 0.6) (layer F.Cu) (net 31))
(segment (start 34.600001 46.300001) (end 35.35 47.05) (width 0.6) (layer F.Cu) (net 31))
(segment (start 35.35 50.25) (end 35.35 47.05) (width 0.6) (layer B.Cu) (net 31))
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(segment (start 90.75 36.5) (end 90.75 28.35) (width 0.6) (layer F.Cu) (net 35))
(segment (start 90.75 28.35) (end 96.49 22.61) (width 0.6) (layer F.Cu) (net 35))
(segment (start 96.49 22.61) (end 97.8 21.3) (width 0.6) (layer F.Cu) (net 35))
(segment (start 100.19 37.09) (end 100.19 25.66) (width 0.6) (layer F.Cu) (net 36))
(segment (start 100.19 25.66) (end 104.15 21.7) (width 0.6) (layer F.Cu) (net 36))
(segment (start 104.15 21.7) (end 104.15 21.3) (width 0.6) (layer F.Cu) (net 36))
(segment (start 52.17 55.92) (end 58.320011 62.070011) (width 0.4) (layer F.Cu) (net 37))
(segment (start 58.320011 62.070011) (end 104.249989 62.070011) (width 0.4) (layer F.Cu) (net 37))
(segment (start 104.249989 62.070011) (end 111.25 55.07) (width 0.4) (layer F.Cu) (net 37))
(segment (start 112.28 51.78) (end 112.28 45.63) (width 0.4) (layer F.Cu) (net 37))
(segment (start 111.25 55.07) (end 111.25 52.81) (width 0.4) (layer F.Cu) (net 37))
(segment (start 111.25 52.81) (end 112.28 51.78) (width 0.4) (layer F.Cu) (net 37))
(segment (start 112.28 45.63) (end 110.62 43.97) (width 0.4) (layer F.Cu) (net 37))
(segment (start 110.62 43.97) (end 109.03 43.97) (width 0.4) (layer F.Cu) (net 37))
(segment (start 109.03 43.97) (end 107.5 45.5) (width 0.4) (layer F.Cu) (net 37))
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(segment (start 50.14 56.44) (end 51.65 56.44) (width 0.25) (layer B.Cu) (net 37))
(segment (start 51.65 56.44) (end 52.17 55.92) (width 0.25) (layer B.Cu) (net 37))
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(segment (start 53.58 53.91) (end 60.489989 60.819989) (width 0.4) (layer F.Cu) (net 38))
(segment (start 60.489989 60.819989) (end 101.830011 60.819989) (width 0.4) (layer F.Cu) (net 38))
(segment (start 101.830011 60.819989) (end 111.58 51.07) (width 0.4) (layer F.Cu) (net 38))
(segment (start 111.58 51.07) (end 111.58 47.08) (width 0.4) (layer F.Cu) (net 38))
(segment (start 111.58 47.08) (end 110 45.5) (width 0.4) (layer F.Cu) (net 38))
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(segment (start 53.58 53.91) (end 53.58 52.53) (width 0.25) (layer B.Cu) (net 38))
(segment (start 53.58 52.53) (end 54.01 52.1) (width 0.25) (layer B.Cu) (net 38))
(segment (start 54.01 52.1) (end 54.71 52.1) (width 0.25) (layer B.Cu) (net 38))
(segment (start 53.58 53.91) (end 48.42 48.75) (width 0.4) (layer B.Cu) (net 38))
(segment (start 48.42 48.75) (end 47 48.75) (width 0.4) (layer B.Cu) (net 38))
(segment (start 47 48.75) (end 45.75 47.5) (width 0.4) (layer B.Cu) (net 38))
(segment (start 45 45.5) (end 43.2 45.5) (width 0.4) (layer B.Cu) (net 38))
(segment (start 45.75 47.5) (end 45.75 46.25) (width 0.4) (layer B.Cu) (net 38))
(segment (start 45.75 46.25) (end 45 45.5) (width 0.4) (layer B.Cu) (net 38))
(segment (start 43.2 45.5) (end 41.7 47) (width 0.4) (layer B.Cu) (net 38))
(segment (start 68.75 31.6) (end 67.17108 31.6) (width 0.4) (layer F.Cu) (net 55))
(segment (start 67.17108 31.6) (end 64.67 34.10108) (width 0.4) (layer F.Cu) (net 55))
(segment (start 64.67 34.10108) (end 64.67 37.89) (width 0.4) (layer F.Cu) (net 55))
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(segment (start 109.5 53.75) (end 110.5 53.75) (width 0.4) (layer B.Cu) (net 56))
(segment (start 110.5 53.75) (end 111.43 52.82) (width 0.4) (layer B.Cu) (net 56))
(segment (start 111.43 52.82) (end 111.43 49.43) (width 0.4) (layer B.Cu) (net 56))
(segment (start 111.43 49.43) (end 110.899999 48.899999) (width 0.4) (layer B.Cu) (net 56))
(segment (start 110.899999 48.899999) (end 110 48) (width 0.4) (layer B.Cu) (net 56))
(segment (start 109.08 37.5) (end 109.08 41.33) (width 0.4) (layer B.Cu) (net 57))
(segment (start 109.08 41.33) (end 112.31 44.56) (width 0.4) (layer B.Cu) (net 57))
(segment (start 108 55) (end 107.3 54.3) (width 0.4) (layer B.Cu) (net 57))
(segment (start 112.31 44.56) (end 112.31 53.19) (width 0.4) (layer B.Cu) (net 57))
(segment (start 107.3 54.3) (end 107.3 53.75) (width 0.4) (layer B.Cu) (net 57))
(segment (start 112.31 53.19) (end 110.5 55) (width 0.4) (layer B.Cu) (net 57))
(segment (start 110.5 55) (end 108 55) (width 0.4) (layer B.Cu) (net 57))
(segment (start 107.5 48) (end 103.75 48) (width 0.4) (layer F.Cu) (net 58))
(segment (start 103.75 48) (end 102.85 48.9) (width 0.4) (layer F.Cu) (net 58))
(segment (start 102.85 48.9) (end 102.85 49.75) (width 0.4) (layer F.Cu) (net 58))
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(segment (start 25.37 44.14) (end 26.91 44.14) (width 0.4) (layer F.Cu) (net 60))
(segment (start 26.91 44.14) (end 27.05 44) (width 0.4) (layer F.Cu) (net 60))
(segment (start 17.71 44.14) (end 25.37 44.14) (width 0.4) (layer B.Cu) (net 60))
(via (at 25.37 44.14) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 60))
(segment (start 14.95 45.5) (end 16.35 45.5) (width 0.4) (layer B.Cu) (net 60))
(segment (start 16.35 45.5) (end 17.71 44.14) (width 0.4) (layer B.Cu) (net 60))
(segment (start 27.05 44) (end 27.05 42) (width 0.4) (layer F.Cu) (net 60))
(segment (start 28.95 44) (end 28.95 42) (width 0.4) (layer F.Cu) (net 61))
(segment (start 38.43934 46.93934) (end 39.43934 46.93934) (width 0.4) (layer F.Cu) (net 61))
(segment (start 39.43934 46.93934) (end 39.5 47) (width 0.4) (layer F.Cu) (net 61))
(segment (start 28.95 44) (end 35.5 44) (width 0.4) (layer F.Cu) (net 61))
(segment (start 35.5 44) (end 38.43934 46.93934) (width 0.4) (layer F.Cu) (net 61))
(segment (start 43.9 47) (end 43.9 45.17) (width 0.4) (layer F.Cu) (net 7))
(segment (start 43.07 44.34) (end 37.1 44.34) (width 0.4) (layer F.Cu) (net 7))
(segment (start 43.9 45.17) (end 43.07 44.34) (width 0.4) (layer F.Cu) (net 7))
(segment (start 37.1 44.34) (end 36 43.24) (width 0.4) (layer F.Cu) (net 7))
(segment (start 20.06 47.25) (end 21.5 47.25) (width 0.4) (layer B.Cu) (net 62))
(segment (start 21.5 47.25) (end 22.45 46.3) (width 0.4) (layer B.Cu) (net 62))
(segment (start 17.01 47.32) (end 19.99 47.32) (width 0.4) (layer B.Cu) (net 62))
(segment (start 19.99 47.32) (end 20.06 47.25) (width 0.4) (layer B.Cu) (net 62))
(segment (start 26.05 48.47) (end 26.08 48.5) (width 0.4) (layer F.Cu) (net 63))
(segment (start 37.8 48.5) (end 39.5 50.2) (width 0.4) (layer F.Cu) (net 63))
(segment (start 26.08 48.5) (end 37.8 48.5) (width 0.4) (layer F.Cu) (net 63))
(segment (start 20.06 49.15) (end 25.37 49.15) (width 0.4) (layer B.Cu) (net 63))
(segment (start 25.37 49.15) (end 26.05 48.47) (width 0.4) (layer B.Cu) (net 63))
(via (at 26.05 48.47) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 63))
(segment (start 20.06 49.15) (end 17.08 49.15) (width 0.4) (layer B.Cu) (net 63))
(segment (start 17.08 49.15) (end 17.01 49.22) (width 0.4) (layer B.Cu) (net 63))
(segment (start 35.9 38) (end 35.9 40.45) (width 0.4) (layer F.Cu) (net 64))
(segment (start 35.9 40.45) (end 36 40.55) (width 0.4) (layer F.Cu) (net 64))
(segment (start 34 40.55) (end 36 40.55) (width 0.4) (layer F.Cu) (net 64))
(segment (start 35.9 35.225) (end 35.9 35.7) (width 0.25) (layer F.Cu) (net 64))
(segment (start 35.9 35.7) (end 35.9 38) (width 0.25) (layer F.Cu) (net 64))
(segment (start 38.1 38) (end 38.1 40.15) (width 0.25) (layer F.Cu) (net 8))
(segment (start 38.1 40.15) (end 38.5 40.55) (width 0.25) (layer F.Cu) (net 8))
(segment (start 40.9 38) (end 40.9 40.45) (width 0.25) (layer F.Cu) (net 9))
(segment (start 40.9 40.45) (end 41 40.55) (width 0.25) (layer F.Cu) (net 9))
(segment (start 44.34886 21) (end 44.34886 19.17386) (width 0.25) (layer F.Cu) (net 10))
(segment (start 44.34886 19.17386) (end 42.675 17.5) (width 0.25) (layer F.Cu) (net 10))
(segment (start 42.675 17.5) (end 42.45 17.5) (width 0.25) (layer F.Cu) (net 10))
(segment (start 43.1 26.775) (end 43.1 26.3) (width 0.25) (layer F.Cu) (net 10))
(segment (start 43.1 26.3) (end 42.14915 25.34915) (width 0.25) (layer F.Cu) (net 10))
(segment (start 42.14915 25.34915) (end 42.14915 24.5) (width 0.25) (layer F.Cu) (net 10))
(segment (start 44.34886 21) (end 44.34886 22.30029) (width 0.25) (layer F.Cu) (net 10))
(segment (start 44.34886 22.30029) (end 42.14915 24.5) (width 0.25) (layer F.Cu) (net 10))
(segment (start 42.14915 24.5) (end 41.45 24.5) (width 0.25) (layer F.Cu) (net 10))
(segment (start 41.45 24.5) (end 40.6 24.5) (width 0.25) (layer F.Cu) (net 10))
(segment (start 43.9 50.2) (end 45.39 48.71) (width 0.25) (layer F.Cu) (net 11))
(segment (start 43.1 38) (end 43.1 40.45) (width 0.25) (layer F.Cu) (net 12))
(segment (start 43.1 40.45) (end 43 40.55) (width 0.25) (layer F.Cu) (net 12))
(segment (start 43.1 35.225) (end 43.1 35.7) (width 0.25) (layer F.Cu) (net 12))
(segment (start 43.1 35.7) (end 43.1 38) (width 0.25) (layer F.Cu) (net 12))
(segment (start 54.5 34.19) (end 54.64 34.19) (width 0.8) (layer B.Cu) (net 13))
(segment (start 54.64 34.19) (end 56 35.55) (width 0.8) (layer B.Cu) (net 13))
(segment (start 54.5 34.19) (end 54.76 34.19) (width 0.8) (layer B.Cu) (net 13))
(segment (start 54.76 34.19) (end 56 32.95) (width 0.8) (layer B.Cu) (net 13))
(segment (start 54.5 34.19) (end 57.28 34.19) (width 0.8) (layer F.Cu) (net 13))
(segment (start 57.28 34.19) (end 57.29 34.18) (width 0.8) (layer F.Cu) (net 13))
(segment (start 101 55) (end 100.925 55) (width 0.4) (layer B.Cu) (net 13))
(segment (start 100.925 55) (end 99.45 53.525) (width 0.4) (layer B.Cu) (net 13))
(segment (start 99.45 53.525) (end 99.45 52.75) (width 0.4) (layer B.Cu) (net 13))
(segment (start 102.7 55.1) (end 101.1 55.1) (width 0.6) (layer B.Cu) (net 13))
(segment (start 101.1 55.1) (end 101 55) (width 0.6) (layer B.Cu) (net 13))
(segment (start 101.08 50.5) (end 99.5 50.5) (width 0.25) (layer B.Cu) (net 13))
(segment (start 99.5 50.5) (end 98.7 50.5) (width 0.25) (layer B.Cu) (net 13))
(segment (start 99.45 52.75) (end 99.45 50.55) (width 0.4) (layer B.Cu) (net 13))
(segment (start 99.45 50.55) (end 99.5 50.5) (width 0.4) (layer B.Cu) (net 13))
(segment (start 101.760002 39.75) (end 101.760002 37.239998) (width 1.5) (layer B.Cu) (net 13))
(segment (start 105.5 50.5) (end 108 50.5) (width 0.4) (layer B.Cu) (net 13))
(segment (start 101.08 50.5) (end 105.5 50.5) (width 0.4) (layer B.Cu) (net 13))
(segment (start 99.700001 45.200001) (end 100 45.5) (width 0.4) (layer B.Cu) (net 13))
(segment (start 99.5 45) (end 99.700001 45.200001) (width 0.4) (layer B.Cu) (net 13))
(segment (start 96 45) (end 99.5 45) (width 0.4) (layer B.Cu) (net 13))
(via (at 100 45.5) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 97.160001 44.350001) (end 101.760002 39.75) (width 1.5) (layer B.Cu) (net 13))
(segment (start 106.54 40.04) (end 102.050002 40.04) (width 0.4) (layer B.Cu) (net 13))
(segment (start 102.050002 40.04) (end 101.760002 39.75) (width 0.4) (layer B.Cu) (net 13))
(segment (start 72.25 52.85) (end 75.65 52.85) (width 0.4) (layer F.Cu) (net 13))
(segment (start 75.65 52.85) (end 75.75 52.75) (width 0.4) (layer F.Cu) (net 13))
(segment (start 75.75 52.674264) (end 75.75 52.75) (width 0.4) (layer B.Cu) (net 13))
(segment (start 75.82 52.604264) (end 75.75 52.674264) (width 0.4) (layer B.Cu) (net 13))
(segment (start 75.82 52.6) (end 75.82 52.604264) (width 0.4) (layer B.Cu) (net 13))
(segment (start 75.5 53) (end 75.75 52.75) (width 0.4) (layer F.Cu) (net 13))
(segment (start 75.5 54.05) (end 75.5 53) (width 0.4) (layer F.Cu) (net 13))
(via (at 75.75 52.75) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 94.95 47.3) (end 95 47.25) (width 0.4) (layer F.Cu) (net 13))
(segment (start 94.95 48.5) (end 94.95 47.3) (width 0.4) (layer F.Cu) (net 13))
(segment (start 93.75 47.25) (end 95 47.25) (width 0.4) (layer B.Cu) (net 13))
(via (at 95 47.25) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 13))
(segment (start 96 45) (end 96.46 45.46) (width 0.4) (layer B.Cu) (net 13))
(segment (start 102.7 56.93) (end 108.020002 56.93) (width 0.4) (layer B.Cu) (net 13))
(segment (start 108.020002 56.93) (end 108.680001 56.270001) (width 0.4) (layer B.Cu) (net 13))
(segment (start 109.5 59.5) (end 108.98 58.98) (width 0.4) (layer B.Cu) (net 13))
(segment (start 108.680001 56.270001) (end 108.98 55.970002) (width 0.4) (layer B.Cu) (net 13))
(segment (start 108.98 56.394266) (end 108.98 55.970002) (width 0.4) (layer B.Cu) (net 13))
(segment (start 108.98 58.98) (end 108.98 56.394266) (width 0.4) (layer B.Cu) (net 13))
(segment (start 108.680001 56.270001) (end 108.98 55.970002) (width 0.4) (layer F.Cu) (net 13))
(segment (start 53.980002 56.03) (end 59.370002 61.42) (width 0.4) (layer F.Cu) (net 13))
(segment (start 59.370002 61.42) (end 103.530002 61.42) (width 0.4) (layer F.Cu) (net 13))
(via (at 108.98 55.970002) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 103.530002 61.42) (end 108.680001 56.270001) (width 0.4) (layer F.Cu) (net 13))
(segment (start 53.680003 56.329999) (end 53.980002 56.03) (width 0.4) (layer B.Cu) (net 13))
(segment (start 53.79 56.48) (end 53.680003 56.370003) (width 0.4) (layer B.Cu) (net 13))
(segment (start 53.680003 56.370003) (end 53.680003 56.329999) (width 0.4) (layer B.Cu) (net 13))
(via (at 53.980002 56.03) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 53.79 56.48) (end 53.880004 56.48) (width 1.5) (layer B.Cu) (net 13))
(segment (start 53.880004 56.48) (end 56.350004 54.01) (width 1.5) (layer B.Cu) (net 13))
(segment (start 56.350004 54.01) (end 73 54.01) (width 1.5) (layer B.Cu) (net 13))
(segment (start 93.14 56.44) (end 91.44 56.44) (width 0.4) (layer B.Cu) (net 13))
(segment (start 91.44 56.44) (end 91 56) (width 0.4) (layer B.Cu) (net 13))
(via (at 91 56) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(via (at 109.5 59.5) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 82.8 55.2) (end 81.5 56.5) (width 0.4) (layer B.Cu) (net 13))
(via (at 81.5 56.5) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 73 54.01) (end 74.41 54.01) (width 1.5) (layer B.Cu) (net 13))
(segment (start 73 56.5) (end 74 57.5) (width 0.4) (layer B.Cu) (net 13))
(segment (start 73 54.01) (end 73 56.5) (width 0.4) (layer B.Cu) (net 13))
(via (at 74 57.5) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 59.36 35.37) (end 59.55 35.18) (width 0.4) (layer F.Cu) (net 13))
(segment (start 58.054264 35.37) (end 59.36 35.37) (width 0.4) (layer F.Cu) (net 13))
(segment (start 57.41 35.15) (end 57.834264 35.15) (width 0.4) (layer F.Cu) (net 13))
(segment (start 57.834264 35.15) (end 58.054264 35.37) (width 0.4) (layer F.Cu) (net 13))
(segment (start 102.7 57.42) (end 102.7 56.93) (width 0.4) (layer B.Cu) (net 13))
(segment (start 102.7 56.93) (end 102.7 55.1) (width 0.4) (layer B.Cu) (net 13))
(segment (start 50.22 60.05) (end 53.79 56.48) (width 1.5) (layer B.Cu) (net 13))
(segment (start 30.5 56.38) (end 34.17 60.05) (width 1.5) (layer B.Cu) (net 13))
(segment (start 57.28 34.19) (end 57.29 34.18) (width 0.25) (layer B.Cu) (net 13))
(segment (start 57.135 34.19) (end 57.28 34.19) (width 0.25) (layer B.Cu) (net 13))
(segment (start 57.3 34.19) (end 57.29 34.18) (width 0.4) (layer F.Cu) (net 13))
(segment (start 58.5 34.19) (end 57.3 34.19) (width 0.4) (layer F.Cu) (net 13))
(segment (start 57.3 34.19) (end 57.29 34.18) (width 0.25) (layer B.Cu) (net 13))
(segment (start 58.5 34.19) (end 57.3 34.19) (width 0.25) (layer B.Cu) (net 13))
(via (at 57.29 34.18) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 56 35.55) (end 56 35.325) (width 0.25) (layer B.Cu) (net 13))
(segment (start 56 35.325) (end 57.135 34.19) (width 0.25) (layer B.Cu) (net 13))
(segment (start 58.5 34.19) (end 58.37 34.19) (width 0.4) (layer F.Cu) (net 13))
(segment (start 58.37 34.19) (end 57.41 35.15) (width 0.4) (layer F.Cu) (net 13))
(via (at 57.41 35.15) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 58.5 34.19) (end 57.26 32.95) (width 0.4) (layer F.Cu) (net 13))
(via (at 57.26 32.95) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 74.95 22.26) (end 72.05 25.16) (width 0.4) (layer F.Cu) (net 13))
(segment (start 72.05 25.16) (end 72.05 28) (width 0.4) (layer F.Cu) (net 13))
(segment (start 74.95 19.5) (end 74.95 22.26) (width 0.4) (layer F.Cu) (net 13))
(segment (start 64.5 29) (end 65.55 29) (width 0.4) (layer F.Cu) (net 13))
(segment (start 65.55 29) (end 66.55 28) (width 0.4) (layer F.Cu) (net 13))
(segment (start 66.55 28) (end 71.05 28) (width 0.4) (layer F.Cu) (net 13))
(segment (start 71.05 28) (end 72.05 28) (width 0.4) (layer F.Cu) (net 13))
(segment (start 58.5 34.19) (end 63.69 29) (width 0.4) (layer F.Cu) (net 13))
(segment (start 63.69 29) (end 64.5 29) (width 0.4) (layer F.Cu) (net 13))
(segment (start 71.25 34.3) (end 69.5 34.3) (width 0.4) (layer F.Cu) (net 13))
(segment (start 73 34.3) (end 71.25 34.3) (width 0.4) (layer F.Cu) (net 13))
(segment (start 76.196 33.086) (end 74.39 31.28) (width 0.4) (layer F.Cu) (net 13))
(segment (start 74.39 31.28) (end 72.05 28.94) (width 0.4) (layer F.Cu) (net 13))
(segment (start 72.8 31.62) (end 73.8 31.62) (width 0.4) (layer F.Cu) (net 13))
(segment (start 73.8 31.62) (end 74.14 31.28) (width 0.4) (layer F.Cu) (net 13))
(segment (start 74.14 31.28) (end 74.39 31.28) (width 0.4) (layer F.Cu) (net 13))
(segment (start 78.5 31) (end 78.5 32.05) (width 0.4) (layer F.Cu) (net 13))
(segment (start 78.5 32.05) (end 77.464 33.086) (width 0.4) (layer F.Cu) (net 13))
(segment (start 72.05 28.94) (end 72.05 28) (width 0.4) (layer F.Cu) (net 13))
(segment (start 77.464 33.086) (end 76.196 33.086) (width 0.4) (layer F.Cu) (net 13))
(segment (start 93.445 47.555) (end 93.75 47.25) (width 1.5) (layer B.Cu) (net 13))
(segment (start 93.75 47.25) (end 96 45) (width 1.5) (layer B.Cu) (net 13))
(segment (start 76.25 31.75) (end 77 31.75) (width 0.4) (layer F.Cu) (net 13))
(via (at 77 31.75) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 76.25 31) (end 76.25 31.75) (width 0.4) (layer B.Cu) (net 13))
(via (at 76.25 31.75) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 76.25 30.25) (end 76.25 31) (width 0.4) (layer F.Cu) (net 13))
(via (at 76.25 31) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 77 30.25) (end 76.25 30.25) (width 0.4) (layer B.Cu) (net 13))
(via (at 76.25 30.25) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 78.5 31) (end 77.75 31) (width 0.4) (layer F.Cu) (net 13))
(segment (start 77.75 31) (end 77 30.25) (width 0.4) (layer F.Cu) (net 13))
(via (at 77 30.25) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 78.5 31) (end 77 31) (width 0.4) (layer F.Cu) (net 13))
(via (at 77 31) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 83 26.5) (end 79.75 29.75) (width 0.8) (layer F.Cu) (net 13))
(segment (start 79.75 29.75) (end 78.5 31) (width 0.8) (layer F.Cu) (net 13))
(segment (start 84.05 29.75) (end 79.75 29.75) (width 0.4) (layer F.Cu) (net 13))
(segment (start 83 26) (end 83 26.5) (width 0.8) (layer F.Cu) (net 13))
(segment (start 74.95 19.5) (end 76.95 19.5) (width 0.4) (layer F.Cu) (net 13))
(segment (start 76.95 19.5) (end 77.5 20.05) (width 0.4) (layer F.Cu) (net 13))
(segment (start 84.05 31.5) (end 79 31.5) (width 0.4) (layer F.Cu) (net 13))
(segment (start 79 31.5) (end 78.5 31) (width 0.4) (layer F.Cu) (net 13))
(segment (start 101.31 58.81) (end 101.31 59.39) (width 0.6) (layer B.Cu) (net 13))
(segment (start 101.31 59.39) (end 101.2 59.5) (width 0.6) (layer B.Cu) (net 13))
(segment (start 101.2 59.5) (end 100 59.5) (width 0.6) (layer B.Cu) (net 13))
(segment (start 79.71 45.18) (end 81.813998 45.18) (width 0.4) (layer B.Cu) (net 13))
(segment (start 81.813998 45.18) (end 82.8 44.193998) (width 0.4) (layer B.Cu) (net 13))
(segment (start 71.5 43.5) (end 72.55 43.5) (width 0.4) (layer B.Cu) (net 13))
(segment (start 72.55 43.5) (end 76.605 47.555) (width 0.4) (layer B.Cu) (net 13))
(segment (start 76.605 47.555) (end 80.865 47.555) (width 0.4) (layer B.Cu) (net 13))
(segment (start 82.8 44.193998) (end 82.8 45.155) (width 0.4) (layer B.Cu) (net 13))
(segment (start 82.8 45.155) (end 82.8 47.555) (width 0.4) (layer B.Cu) (net 13))
(segment (start 93.14 56.44) (end 93.14 55.39) (width 0.4) (layer B.Cu) (net 13))
(segment (start 93.14 55.39) (end 90.84 53.09) (width 0.4) (layer B.Cu) (net 13))
(segment (start 90.84 53.09) (end 90.415736 53.09) (width 0.4) (layer B.Cu) (net 13))
(segment (start 90.415736 53.09) (end 89.915736 52.59) (width 0.4) (layer B.Cu) (net 13))
(segment (start 89.915736 52.59) (end 89.91 52.59) (width 0.4) (layer B.Cu) (net 13))
(segment (start 92 52.45) (end 91.48 52.45) (width 0.4) (layer F.Cu) (net 13))
(segment (start 91.48 52.45) (end 90.84 53.09) (width 0.4) (layer F.Cu) (net 13))
(via (at 90.84 53.09) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 101.31 58.81) (end 102.7 57.42) (width 0.4) (layer B.Cu) (net 13))
(segment (start 86.99 55.51) (end 89.91 52.59) (width 0.4) (layer B.Cu) (net 13))
(segment (start 89.91 52.59) (end 89.91 51.41) (width 0.4) (layer B.Cu) (net 13))
(segment (start 86.9 56.5) (end 86.9 55.6) (width 0.4) (layer F.Cu) (net 13))
(segment (start 86.9 55.6) (end 86.99 55.51) (width 0.4) (layer F.Cu) (net 13))
(via (at 86.99 55.51) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 75.155 54.01) (end 74.41 54.01) (width 0.4) (layer B.Cu) (net 13))
(segment (start 74.41 54.01) (end 75.82 52.6) (width 1.5) (layer B.Cu) (net 13))
(segment (start 75.82 52.6) (end 80.865 47.555) (width 1.5) (layer B.Cu) (net 13))
(segment (start 102.92 56.18) (end 102.92 55.32) (width 0.6) (layer F.Cu) (net 13))
(segment (start 102.92 55.32) (end 102.7 55.1) (width 0.6) (layer F.Cu) (net 13))
(via (at 102.7 55.1) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 97.4 48.5) (end 97.4 46.4) (width 0.25) (layer B.Cu) (net 13))
(segment (start 97.4 46.4) (end 96 45) (width 0.25) (layer B.Cu) (net 13))
(segment (start 98.7 50.5) (end 97.4 49.2) (width 0.25) (layer B.Cu) (net 13))
(segment (start 97.4 49.2) (end 97.4 48.5) (width 0.25) (layer B.Cu) (net 13))
(segment (start 80.865 47.555) (end 82.8 47.555) (width 1.5) (layer B.Cu) (net 13))
(segment (start 90.07 47.555) (end 93.445 47.555) (width 1.5) (layer B.Cu) (net 13))
(segment (start 90.07 50.825736) (end 90.07 47.555) (width 0.4) (layer B.Cu) (net 13))
(segment (start 89.91 51.41) (end 89.91 50.985736) (width 0.4) (layer B.Cu) (net 13))
(segment (start 89.91 50.985736) (end 90.07 50.825736) (width 0.4) (layer B.Cu) (net 13))
(segment (start 90 50.1) (end 90 51.32) (width 0.4) (layer F.Cu) (net 13))
(segment (start 90 51.32) (end 89.91 51.41) (width 0.4) (layer F.Cu) (net 13))
(via (at 89.91 51.41) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 13))
(segment (start 64.5 29) (end 64.5 25.06) (width 0.8) (layer F.Cu) (net 13))
(segment (start 64.5 25.06) (end 64.36 24.92) (width 0.8) (layer F.Cu) (net 13))
(segment (start 96 45) (end 96.649999 44.350001) (width 1.5) (layer B.Cu) (net 13))
(segment (start 96.649999 44.350001) (end 97.160001 44.350001) (width 1.5) (layer B.Cu) (net 13))
(via (at 82.8 47.555) (size 2.5) (drill 2) (layers F.Cu B.Cu) (net 13))
(segment (start 58.5 34.19) (end 57.26 32.95) (width 0.25) (layer B.Cu) (net 13))
(segment (start 57.26 32.95) (end 56 32.95) (width 0.25) (layer B.Cu) (net 13))
(segment (start 54.5 31.65) (end 63.23 22.92) (width 0.8) (layer F.Cu) (net 14))
(segment (start 63.23 22.92) (end 64.36 22.92) (width 0.8) (layer F.Cu) (net 14))
(segment (start 56 31.05) (end 55.1 31.05) (width 0.4) (layer B.Cu) (net 14))
(segment (start 55.1 31.05) (end 54.5 31.65) (width 0.4) (layer B.Cu) (net 14))
(segment (start 66.71 22.92) (end 68.29 24.5) (width 0.8) (layer F.Cu) (net 14))
(segment (start 68.29 24.5) (end 70.17 24.5) (width 0.8) (layer F.Cu) (net 14))
(segment (start 67.15 19.5) (end 67.15 20.35) (width 0.4) (layer F.Cu) (net 14))
(segment (start 67.15 20.35) (end 67.22 20.42) (width 0.4) (layer F.Cu) (net 14))
(segment (start 67.22 20.42) (end 67.22 22.41) (width 0.4) (layer F.Cu) (net 14))
(segment (start 66.71 22.92) (end 67.22 22.41) (width 0.4) (layer F.Cu) (net 14))
(segment (start 67.22 22.41) (end 67.22 19.81) (width 0.4) (layer F.Cu) (net 14))
(segment (start 64.36 22.92) (end 66.71 22.92) (width 0.8) (layer F.Cu) (net 14))
(segment (start 56 37.45) (end 55.22 37.45) (width 0.4) (layer B.Cu) (net 15))
(segment (start 55.22 37.45) (end 54.5 36.73) (width 0.4) (layer B.Cu) (net 15))
(segment (start 68.75 29.4) (end 67.1 29.4) (width 0.4) (layer F.Cu) (net 15))
(segment (start 67.1 29.4) (end 65.5 31) (width 0.4) (layer F.Cu) (net 15))
(segment (start 65.5 31) (end 64.5 31) (width 0.4) (layer F.Cu) (net 15))
(segment (start 41.56 34.62) (end 40.57 34.62) (width 0.25) (layer B.Cu) (net 16))
(segment (start 40.57 34.62) (end 40.45 34.5) (width 0.25) (layer B.Cu) (net 16))
(segment (start 43.1 34.575) (end 41.605 34.575) (width 0.25) (layer F.Cu) (net 16))
(segment (start 41.605 34.575) (end 41.56 34.62) (width 0.25) (layer F.Cu) (net 16))
(via (at 41.56 34.62) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 16))
(segment (start 46 33.05) (end 45.375 33.05) (width 0.25) (layer F.Cu) (net 17))
(segment (start 45.375 33.05) (end 45.15 33.275) (width 0.25) (layer F.Cu) (net 17))
(segment (start 45.15 33.275) (end 44.225 33.275) (width 0.25) (layer F.Cu) (net 17))
(segment (start 44.225 33.275) (end 43.1 33.275) (width 0.25) (layer F.Cu) (net 17))
(segment (start 44.88 31.64) (end 44.545 31.975) (width 0.25) (layer F.Cu) (net 18))
(segment (start 44.545 31.975) (end 43.1 31.975) (width 0.25) (layer F.Cu) (net 18))
(segment (start 42.5 31.55) (end 44.79 31.55) (width 0.25) (layer B.Cu) (net 18))
(segment (start 44.79 31.55) (end 44.88 31.64) (width 0.25) (layer B.Cu) (net 18))
(via (at 44.88 31.64) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 18))
(segment (start 83 22.5) (end 81.55 22.5) (width 0.8) (layer F.Cu) (net 19))
(segment (start 81.55 22.5) (end 79.55 24.5) (width 0.8) (layer F.Cu) (net 19))
(segment (start 79.55 24.5) (end 77.5 24.5) (width 0.8) (layer F.Cu) (net 19))
(segment (start 75.25 24.5) (end 77.5 24.5) (width 0.8) (layer F.Cu) (net 19))
(segment (start 77.5 21.95) (end 77.5 23.35) (width 0.8) (layer F.Cu) (net 19))
(segment (start 77.5 23.35) (end 77.5 24.5) (width 0.8) (layer F.Cu) (net 19))
(segment (start 73.95 28) (end 73.95 25.8) (width 0.8) (layer F.Cu) (net 19))
(segment (start 73.95 25.8) (end 75.25 24.5) (width 0.8) (layer F.Cu) (net 19))
(segment (start 85.95 31.5) (end 85.95 30.3) (width 0.4) (layer F.Cu) (net 19))
(segment (start 85.95 30.3) (end 86 30.25) (width 0.4) (layer F.Cu) (net 19))
(segment (start 86 34.5) (end 86 30.25) (width 0.8) (layer F.Cu) (net 19))
(segment (start 85.95 29.75) (end 85.95 30.2) (width 0.4) (layer F.Cu) (net 19))
(segment (start 86 30.25) (end 86 24.05) (width 0.8) (layer F.Cu) (net 19))
(segment (start 85.95 30.2) (end 86 30.25) (width 0.4) (layer F.Cu) (net 19))
(segment (start 88.09 34.54) (end 86.04 34.54) (width 0.4) (layer F.Cu) (net 19))
(segment (start 86.04 34.54) (end 86 34.5) (width 0.4) (layer F.Cu) (net 19))
(segment (start 90.86 36.52) (end 90.07 36.52) (width 0.4) (layer B.Cu) (net 19))
(via (at 88.09 34.54) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 19))
(segment (start 90.07 36.52) (end 88.09 34.54) (width 0.4) (layer B.Cu) (net 19))
(segment (start 86 24.05) (end 84.45 22.5) (width 0.8) (layer F.Cu) (net 19))
(segment (start 84.45 22.5) (end 83 22.5) (width 0.8) (layer F.Cu) (net 19))
(segment (start 98.044 54.78) (end 96.994 54.78) (width 0.6) (layer B.Cu) (net 20))
(segment (start 96.994 54.78) (end 96.78 54.994) (width 0.6) (layer B.Cu) (net 20))
(segment (start 96.78 54.994) (end 96.78 57.398) (width 0.6) (layer B.Cu) (net 20))
(segment (start 96.78 57.398) (end 96.318 57.86) (width 0.6) (layer B.Cu) (net 20))
(segment (start 96.318 57.86) (end 80.062 57.86) (width 0.6) (layer B.Cu) (net 20))
(segment (start 80.062 57.86) (end 78.74 59.182) (width 0.6) (layer B.Cu) (net 20))
(segment (start 78.74 59.182) (end 72.39 59.182) (width 0.6) (layer B.Cu) (net 20))
(segment (start 72.39 59.182) (end 69.342 56.134) (width 0.6) (layer B.Cu) (net 20))
(segment (start 73 36.2) (end 72.924 36.2) (width 0.4) (layer F.Cu) (net 20))
(segment (start 72.924 36.2) (end 72.644 36.48) (width 0.4) (layer F.Cu) (net 20))
(segment (start 72.644 36.48) (end 71.25 36.48) (width 0.8) (layer F.Cu) (net 20))
(segment (start 71.25 36.48) (end 70.4236 36.48) (width 0.8) (layer F.Cu) (net 20))
(segment (start 71.25 36.2) (end 71.25 36.48) (width 0.4) (layer F.Cu) (net 20))
(segment (start 69.5 36.2) (end 69.5 36.5364) (width 0.4) (layer F.Cu) (net 20))
(segment (start 98.044 54.78) (end 98.044 53.244) (width 0.4) (layer B.Cu) (net 20))
(segment (start 98.044 53.244) (end 97.55 52.75) (width 0.4) (layer B.Cu) (net 20))
(segment (start 78 36.48) (end 75.946 36.48) (width 0.8) (layer F.Cu) (net 20))
(segment (start 75.946 36.48) (end 72.644 36.48) (width 0.8) (layer F.Cu) (net 20))
(segment (start 75.41 38.95) (end 75.41 37.1) (width 0.6) (layer F.Cu) (net 20))
(segment (start 75.41 37.1) (end 75.946 36.564) (width 0.6) (layer F.Cu) (net 20))
(segment (start 75.946 36.564) (end 75.946 36.48) (width 0.6) (layer F.Cu) (net 20))
(via (at 69.342 56.134) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 20))
(segment (start 78.5 34.5) (end 78.5 35.98) (width 0.8) (layer F.Cu) (net 20))
(segment (start 78.5 35.98) (end 78 36.48) (width 0.8) (layer F.Cu) (net 20))
(segment (start 70.4236 36.48) (end 70.4036 36.5) (width 0.8) (layer F.Cu) (net 20))
(segment (start 70.5 36.4036) (end 70.4036 36.5) (width 0.4) (layer F.Cu) (net 20))
(segment (start 90.86 38.87) (end 94 42.01) (width 0.4) (layer B.Cu) (net 21))
(segment (start 94 42.01) (end 94 42.25) (width 0.4) (layer B.Cu) (net 21))
(segment (start 90.86 38.72) (end 90.86 38.87) (width 0.4) (layer B.Cu) (net 21))
(segment (start 93.700001 42.549999) (end 94 42.25) (width 0.4) (layer F.Cu) (net 21))
(segment (start 93.05 48.5) (end 93.05 43.2) (width 0.4) (layer F.Cu) (net 21))
(segment (start 93.05 43.2) (end 93.700001 42.549999) (width 0.4) (layer F.Cu) (net 21))
(via (at 94 42.25) (size 0.8) (drill 0.4) (layers F.Cu B.Cu) (net 21))
(segment (start 94.095 50.8) (end 94.095 49.545) (width 0.4) (layer F.Cu) (net 21))
(segment (start 94.095 49.545) (end 93.05 48.5) (width 0.4) (layer F.Cu) (net 21))
(segment (start 92 50.55) (end 93.845 50.55) (width 0.4) (layer F.Cu) (net 21))
(segment (start 93.845 50.55) (end 94.095 50.8) (width 0.4) (layer F.Cu) (net 21))
(segment (start 77.39 56.86) (end 76.48 55.95) (width 0.4) (layer F.Cu) (net 22))
(segment (start 76.48 55.95) (end 75.5 55.95) (width 0.4) (layer F.Cu) (net 22))
(segment (start 79.82 54.43) (end 77.39 56.86) (width 0.4) (layer F.Cu) (net 22))
(segment (start 76.5 59) (end 76.5 57.75) (width 0.4) (layer F.Cu) (net 22))
(segment (start 76.5 57.75) (end 77.39 56.86) (width 0.4) (layer F.Cu) (net 22))
(segment (start 78.1 45.65) (end 79.475 45.65) (width 0.4) (layer F.Cu) (net 22))
(segment (start 79.475 45.65) (end 79.82 45.995) (width 0.4) (layer F.Cu) (net 22))
(segment (start 79.82 45.995) (end 79.82 54.43) (width 0.4) (layer F.Cu) (net 22))
(segment (start 85 59) (end 85 56.5) (width 0.4) (layer F.Cu) (net 23))
(segment (start 87.5 45.65) (end 86.125 45.65) (width 0.4) (layer F.Cu) (net 23))
(segment (start 85.92 52.66) (end 85.46 53.12) (width 0.4) (layer F.Cu) (net 23))
(segment (start 86.125 45.65) (end 85.92 45.855) (width 0.4) (layer F.Cu) (net 23))
(segment (start 85.46 53.12) (end 85.46 56.04) (width 0.4) (layer F.Cu) (net 23))
(segment (start 85.92 45.855) (end 85.92 52.66) (width 0.4) (layer F.Cu) (net 23))
(segment (start 85.46 56.04) (end 85 56.5) (width 0.4) (layer F.Cu) (net 23))
(segment (start 83.75 39.25) (end 85.25 39.25) (width 0.8) (layer F.Cu) (net 24))
(segment (start 85.25 39.25) (end 86 38.5) (width 0.8) (layer F.Cu) (net 24))
(segment (start 83.75 38.5) (end 83.75 39.25) (width 0.8) (layer B.Cu) (net 24))
(via (at 83.75 39.25) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 24))
(segment (start 83.75 37.75) (end 85.25 37.75) (width 0.8) (layer F.Cu) (net 24))
(segment (start 85.25 37.75) (end 86 38.5) (width 0.8) (layer F.Cu) (net 24))
(segment (start 83.75 38.5) (end 83.75 37.75) (width 0.8) (layer B.Cu) (net 24))
(via (at 83.75 37.75) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 24))
(segment (start 86 38.5) (end 83.75 38.5) (width 0.8) (layer F.Cu) (net 24))
(via (at 83.75 38.5) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 24))
(segment (start 98.044 56.98) (end 98.98 56.98) (width 0.6) (layer B.Cu) (net 25))
(segment (start 98.98 56.98) (end 99.75 56.21) (width 0.6) (layer B.Cu) (net 25))
(segment (start 98.044 56.98) (end 98.044 59.444) (width 0.6) (layer B.Cu) (net 25))
(segment (start 98.044 59.444) (end 98.1 59.5) (width 0.6) (layer B.Cu) (net 25))
(segment (start 99.75 56.21) (end 100.99 56.21) (width 0.6) (layer F.Cu) (net 25))
(segment (start 100.99 56.21) (end 101.02 56.18) (width 0.6) (layer F.Cu) (net 25))
(segment (start 99.75 56.21) (end 97.915 56.21) (width 0.6) (layer F.Cu) (net 25))
(segment (start 97.915 56.21) (end 97.905 56.2) (width 0.6) (layer F.Cu) (net 25))
(via (at 99.75 56.21) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 25))
(segment (start 72.33 41.83) (end 75.25 41.83) (width 0.4) (layer B.Cu) (net 26))
(segment (start 75.25 41.83) (end 81.235738 41.83) (width 0.4) (layer B.Cu) (net 26))
(segment (start 75.5 42.25) (end 75.200001 41.950001) (width 0.4) (layer B.Cu) (net 26))
(segment (start 75.200001 41.950001) (end 75.200001 41.879999) (width 0.4) (layer B.Cu) (net 26))
(segment (start 75.200001 41.879999) (end 75.25 41.83) (width 0.4) (layer B.Cu) (net 26))
(segment (start 75 41.84) (end 78.1 41.84) (width 0.4) (layer F.Cu) (net 26))
(segment (start 72.34 41.84) (end 75 41.84) (width 0.4) (layer F.Cu) (net 26))
(segment (start 75 41.84) (end 75.09 41.84) (width 0.4) (layer F.Cu) (net 26))
(segment (start 75.09 41.84) (end 75.5 42.25) (width 0.4) (layer F.Cu) (net 26))
(via (at 75.5 42.25) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 26))
(segment (start 79.41 38.95) (end 79.41 40.53) (width 0.6) (layer F.Cu) (net 26))
(segment (start 79.41 40.53) (end 78.1 41.84) (width 0.6) (layer F.Cu) (net 26))
(segment (start 81.245738 41.84) (end 81.3 41.84) (width 0.4) (layer B.Cu) (net 26))
(segment (start 81.235738 41.83) (end 81.245738 41.84) (width 0.4) (layer B.Cu) (net 26))
(via (at 81.3 41.84) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 26))
(segment (start 80.935 41.83) (end 81.235738 41.83) (width 0.4) (layer B.Cu) (net 26))
(segment (start 79.71 43.055) (end 80.935 41.83) (width 0.4) (layer B.Cu) (net 26))
(segment (start 71.5 41) (end 72.33 41.83) (width 0.4) (layer B.Cu) (net 26))
(segment (start 79.71 43.28) (end 79.71 43.055) (width 0.4) (layer B.Cu) (net 26))
(segment (start 72.34 41.84) (end 71.5 41) (width 0.4) (layer F.Cu) (net 26))
(segment (start 38.5 56.5) (end 32.85 56.5) (width 0.6) (layer F.Cu) (net 27))
(segment (start 32.85 56.5) (end 32.71 56.36) (width 0.6) (layer F.Cu) (net 27))
(segment (start 36 56.5) (end 38.5 56.5) (width 0.6) (layer F.Cu) (net 27))
(segment (start 22.52 29.04) (end 22.52 28.54) (width 0.25) (layer F.Cu) (net 29))
(segment (start 22.52 28.54) (end 22.56 28.5) (width 0.25) (layer F.Cu) (net 29))
(segment (start 22.56 28.5) (end 22.58 28.5) (width 0.25) (layer F.Cu) (net 29))
(segment (start 20.44932 28.5) (end 22.58 28.5) (width 0.25) (layer F.Cu) (net 29))
(segment (start 22.58 28.5) (end 23.9 28.5) (width 0.25) (layer F.Cu) (net 29))
(segment (start 23.9 29.5) (end 22.98 29.5) (width 0.25) (layer B.Cu) (net 29))
(segment (start 22.98 29.5) (end 22.52 29.04) (width 0.25) (layer B.Cu) (net 29))
(via (at 22.52 29.04) (size 0.5) (drill 0.3) (layers F.Cu B.Cu) (net 29))
(segment (start 20.44932 27.6999) (end 22.5501 27.6999) (width 0.25) (layer F.Cu) (net 30))
(segment (start 22.5501 27.6999) (end 23.75 26.5) (width 0.25) (layer F.Cu) (net 30))
(segment (start 23.75 26.5) (end 23.9 26.5) (width 0.25) (layer F.Cu) (net 30))
(segment (start 52.17 55.92) (end 48.45 52.2) (width 0.4) (layer B.Cu) (net 37))
(segment (start 48.45 52.2) (end 42.63934 52.2) (width 0.4) (layer B.Cu) (net 37))
(segment (start 42.63934 52.2) (end 41.7 51.26066) (width 0.4) (layer B.Cu) (net 37))
(segment (start 41.7 51.26066) (end 41.7 50.2) (width 0.4) (layer B.Cu) (net 37))
(segment (start 52.1 55.92) (end 52.17 55.92) (width 0.4) (layer B.Cu) (net 37))
(via (at 52.17 55.92) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 37))
(via (at 53.58 53.91) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 38))
(segment (start 26.1 28.5) (end 27.37 28.5) (width 0.25) (layer F.Cu) (net 39))
(segment (start 27.37 28.5) (end 30.81 31.94) (width 0.25) (layer F.Cu) (net 39))
(segment (start 30.81 31.94) (end 35.865 31.94) (width 0.25) (layer F.Cu) (net 39))
(segment (start 35.865 31.94) (end 35.9 31.975) (width 0.25) (layer F.Cu) (net 39))
(segment (start 26.1 26.5) (end 26.25 26.5) (width 0.25) (layer F.Cu) (net 40))
(segment (start 26.25 26.5) (end 31.075 31.325) (width 0.25) (layer F.Cu) (net 40))
(segment (start 31.075 31.325) (end 35.9 31.325) (width 0.25) (layer F.Cu) (net 40))
(segment (start 95.55 54.54) (end 95.37 54.72) (width 0.4) (layer F.Cu) (net 41))
(segment (start 95.37 54.72) (end 95.37 56.195) (width 0.4) (layer F.Cu) (net 41))
(segment (start 95.37 56.195) (end 95.365 56.2) (width 0.4) (layer F.Cu) (net 41))
(segment (start 95.34 56.44) (end 95.34 54.75) (width 0.4) (layer B.Cu) (net 41))
(segment (start 95.34 54.75) (end 95.55 54.54) (width 0.4) (layer B.Cu) (net 41))
(via (at 95.55 54.54) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 41))
(segment (start 95.365 56.2) (end 95.365 58.265) (width 0.4) (layer F.Cu) (net 41))
(segment (start 95.365 58.265) (end 95.6 58.5) (width 0.4) (layer F.Cu) (net 41))
(segment (start 92.264262 59.38) (end 91.839998 59.38) (width 0.4) (layer F.Cu) (net 42))
(segment (start 92.37 59.38) (end 92.264262 59.38) (width 0.4) (layer F.Cu) (net 42))
(segment (start 93.25 58.5) (end 92.37 59.38) (width 0.4) (layer F.Cu) (net 42))
(segment (start 93.4 58.5) (end 93.25 58.5) (width 0.4) (layer F.Cu) (net 42))
(segment (start 91.809998 59.35) (end 91.839998 59.38) (width 0.4) (layer B.Cu) (net 42))
(segment (start 82.31 59.35) (end 91.809998 59.35) (width 0.4) (layer B.Cu) (net 42))
(via (at 91.839998 59.38) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 42))
(segment (start 81.885736 59.35) (end 82.31 59.35) (width 0.4) (layer F.Cu) (net 42))
(segment (start 80.85 59.35) (end 81.885736 59.35) (width 0.4) (layer F.Cu) (net 42))
(segment (start 80.5 59) (end 80.85 59.35) (width 0.4) (layer F.Cu) (net 42))
(via (at 82.31 59.35) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 42))
(segment (start 94.095 56.2) (end 94.095 57.805) (width 0.4) (layer F.Cu) (net 42))
(segment (start 94.095 57.805) (end 93.4 58.5) (width 0.4) (layer F.Cu) (net 42))
(segment (start 99.6 48.5) (end 99.6 46.65) (width 0.4) (layer B.Cu) (net 43))
(segment (start 99.6 46.65) (end 99.75 46.5) (width 0.4) (layer F.Cu) (net 43))
(segment (start 99.6 46.65) (end 99.75 46.5) (width 0.4) (layer B.Cu) (net 43))
(segment (start 99.6 48) (end 99.6 46.65) (width 0.4) (layer F.Cu) (net 43))
(via (at 99.75 46.5) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 43))
(segment (start 96.635 50.8) (end 96.635 49.895) (width 0.4) (layer F.Cu) (net 43))
(segment (start 96.635 49.895) (end 97.27 49.26) (width 0.4) (layer F.Cu) (net 43))
(segment (start 97.27 49.26) (end 99.02 49.26) (width 0.4) (layer F.Cu) (net 43))
(segment (start 99.02 49.26) (end 99.6 48.68) (width 0.4) (layer F.Cu) (net 43))
(segment (start 99.6 48.68) (end 99.6 48) (width 0.4) (layer F.Cu) (net 43))
(segment (start 95.365 50.8) (end 95.365 52.595) (width 0.4) (layer F.Cu) (net 44))
(segment (start 95.365 52.595) (end 93.91 54.05) (width 0.4) (layer F.Cu) (net 44))
(segment (start 93.91 54.05) (end 90.61 54.05) (width 0.4) (layer F.Cu) (net 44))
(segment (start 90.61 54.05) (end 88.96 55.7) (width 0.4) (layer F.Cu) (net 44))
(segment (start 88.96 55.7) (end 88.96 58.78) (width 0.4) (layer F.Cu) (net 44))
(segment (start 97.4 48) (end 95.365 50.035) (width 0.4) (layer F.Cu) (net 44))
(segment (start 95.365 50.035) (end 95.365 50.8) (width 0.4) (layer F.Cu) (net 44))
(segment (start 91 45.6) (end 91 46.9) (width 0.4) (layer F.Cu) (net 45))
(segment (start 91 46.9) (end 90 47.9) (width 0.4) (layer F.Cu) (net 45))
(segment (start 90 47.9) (end 89.02 46.92) (width 0.4) (layer F.Cu) (net 45))
(segment (start 89.02 46.92) (end 87.5 46.92) (width 0.4) (layer F.Cu) (net 45))
(segment (start 72.65 48.6) (end 72.25 49) (width 0.4) (layer F.Cu) (net 46))
(segment (start 72.25 49) (end 72.25 50.65) (width 0.4) (layer F.Cu) (net 46))
(segment (start 74 48.6) (end 72.65 48.6) (width 0.4) (layer F.Cu) (net 46))
(segment (start 78.1 46.92) (end 76.62 46.92) (width 0.4) (layer F.Cu) (net 46))
(segment (start 76.62 46.92) (end 74.94 48.6) (width 0.4) (layer F.Cu) (net 46))
(segment (start 74.94 48.6) (end 74 48.6) (width 0.4) (layer F.Cu) (net 46))
(segment (start 74.05 48.65) (end 74 48.6) (width 0.4) (layer F.Cu) (net 46))
(segment (start 78.1 43.11) (end 79.675 43.11) (width 0.6) (layer F.Cu) (net 47))
(segment (start 79.675 43.11) (end 79.97 42.815) (width 0.6) (layer F.Cu) (net 47))
(segment (start 79.97 42.815) (end 79.97 41.78) (width 0.6) (layer F.Cu) (net 47))
(segment (start 79.97 41.78) (end 81.25 40.5) (width 0.6) (layer F.Cu) (net 47))
(segment (start 81.25 40.5) (end 90.75 40.5) (width 0.6) (layer F.Cu) (net 47))
(segment (start 78.1 43.11) (end 75.49 43.11) (width 0.4) (layer F.Cu) (net 47))
(segment (start 75.49 43.11) (end 74 44.6) (width 0.4) (layer F.Cu) (net 47))
(segment (start 74 44.6) (end 74 46.4) (width 0.4) (layer F.Cu) (net 47))
(segment (start 96.19 37.09) (end 96.19 38.31) (width 0.6) (layer F.Cu) (net 48))
(segment (start 96.19 38.31) (end 91.1 43.4) (width 0.6) (layer F.Cu) (net 48))
(segment (start 91.1 43.4) (end 91 43.4) (width 0.6) (layer F.Cu) (net 48))
(segment (start 87.5 43.11) (end 90.71 43.11) (width 0.6) (layer F.Cu) (net 48))
(segment (start 90.71 43.11) (end 91 43.4) (width 0.6) (layer F.Cu) (net 48))
(segment (start 50.5 25) (end 50.5 25.51) (width 0.25) (layer F.Cu) (net 49))
(segment (start 50.5 25.51) (end 46.635 29.375) (width 0.25) (layer F.Cu) (net 49))
(segment (start 46.635 29.375) (end 44.225 29.375) (width 0.25) (layer F.Cu) (net 49))
(segment (start 44.225 29.375) (end 43.1 29.375) (width 0.25) (layer F.Cu) (net 49))
(segment (start 43.1 30.025) (end 50.475 30.025) (width 0.25) (layer F.Cu) (net 50))
(segment (start 50.475 30.025) (end 50.5 30) (width 0.25) (layer F.Cu) (net 50))
(segment (start 43.1 30.675) (end 47.275 30.675) (width 0.25) (layer F.Cu) (net 51))
(segment (start 50.5 33.9) (end 50.5 35) (width 0.25) (layer F.Cu) (net 51))
(segment (start 47.275 30.675) (end 50.5 33.9) (width 0.25) (layer F.Cu) (net 51))
(segment (start 21.65 21) (end 19.04 21) (width 0.25) (layer F.Cu) (net 65))
(segment (start 19.04 21) (end 19 21.04) (width 0.25) (layer F.Cu) (net 65))
(segment (start 37.75 46.25) (end 37.75 44.1) (width 0.4) (layer B.Cu) (net 66))
(segment (start 37.75 47.75) (end 37.75 46.25) (width 0.4) (layer B.Cu) (net 66))
(segment (start 38.5 48.5) (end 37.75 47.75) (width 0.4) (layer B.Cu) (net 66))
(segment (start 45.25 48.5) (end 38.5 48.5) (width 0.4) (layer B.Cu) (net 66))
(segment (start 46.200001 49.450001) (end 45.25 48.5) (width 0.4) (layer B.Cu) (net 66))
(segment (start 47.1 50.2) (end 46.350001 49.450001) (width 0.4) (layer B.Cu) (net 66))
(segment (start 46.350001 49.450001) (end 46.200001 49.450001) (width 0.4) (layer B.Cu) (net 66))
(segment (start 27.75 43.75) (end 27.75 42.85) (width 0.6) (layer B.Cu) (net 67))
(segment (start 27.75 47.05) (end 27.75 43.75) (width 0.6) (layer B.Cu) (net 67))
(segment (start 33.35 25.5) (end 33.49 25.64) (width 0.25) (layer F.Cu) (net 68))
(segment (start 33.49 25.64) (end 33.49 26.79) (width 0.25) (layer F.Cu) (net 68))
(segment (start 33.49 26.79) (end 34.775 28.075) (width 0.25) (layer F.Cu) (net 68))
(segment (start 34.775 28.075) (end 35.9 28.075) (width 0.25) (layer F.Cu) (net 68))
(segment (start 50.5 20) (end 50.5 21.22) (width 0.25) (layer F.Cu) (net 69))
(segment (start 50.5 21.22) (end 44.295 27.425) (width 0.25) (layer F.Cu) (net 69))
(segment (start 44.295 27.425) (end 43.1 27.425) (width 0.25) (layer F.Cu) (net 69))
(segment (start 71.06892 19.5) (end 69.35 19.5) (width 0.4) (layer F.Cu) (net 54))
(segment (start 72.71 21.96) (end 72.71 19.84) (width 0.4) (layer F.Cu) (net 54))
(segment (start 72.71 19.84) (end 73.05 19.5) (width 0.4) (layer F.Cu) (net 54))
(segment (start 71.06892 19.5) (end 73.05 19.5) (width 0.4) (layer F.Cu) (net 54))
(segment (start 70.9 31.62) (end 68.77 31.62) (width 0.4) (layer F.Cu) (net 55))
(segment (start 68.77 31.62) (end 68.75 31.6) (width 0.4) (layer F.Cu) (net 55))
(segment (start 68.9 31.45) (end 68.75 31.6) (width 0.4) (layer F.Cu) (net 55))
(segment (start 96.635 56.2) (end 96.635 57.135) (width 0.4) (layer F.Cu) (net 57))
(segment (start 96.635 57.135) (end 97.25 57.75) (width 0.4) (layer F.Cu) (net 57))
(segment (start 97.25 57.75) (end 103.325736 57.75) (width 0.4) (layer F.Cu) (net 57))
(segment (start 103.325736 57.75) (end 105.575736 55.5) (width 0.4) (layer F.Cu) (net 57))
(segment (start 105.575736 55.5) (end 106 55.5) (width 0.4) (layer F.Cu) (net 57))
(segment (start 106 54.9) (end 106 55.5) (width 0.4) (layer B.Cu) (net 57))
(segment (start 107.15 53.75) (end 106 54.9) (width 0.4) (layer B.Cu) (net 57))
(segment (start 107.3 53.75) (end 107.15 53.75) (width 0.4) (layer B.Cu) (net 57))
(via (at 106 55.5) (size 0.6) (drill 0.4) (layers F.Cu B.Cu) (net 57))
(segment (start 100.65 49.75) (end 101 49.75) (width 0.4) (layer F.Cu) (net 59))
(segment (start 99.75 44.25) (end 99.75 41.75) (width 0.4) (layer F.Cu) (net 59))
(segment (start 101 49.75) (end 101 45.5) (width 0.4) (layer F.Cu) (net 59))
(segment (start 101 45.5) (end 99.75 44.25) (width 0.4) (layer F.Cu) (net 59))
(segment (start 99.75 41.75) (end 103.238001 38.261999) (width 0.4) (layer F.Cu) (net 59))
(segment (start 103.238001 38.261999) (end 104 37.5) (width 0.4) (layer F.Cu) (net 59))
(segment (start 100.65 49.75) (end 99.6 50.8) (width 0.4) (layer F.Cu) (net 59))
(segment (start 99.6 50.8) (end 98.605 50.8) (width 0.4) (layer F.Cu) (net 59))
(segment (start 98.605 50.8) (end 97.905 50.8) (width 0.4) (layer F.Cu) (net 59))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(zone (net 1) (net_name Earth) (layer B.Cu) (tstamp 0) (hatch edge 0.508)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(connect_pads (clearance 0.3))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(min_thickness 0.25)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 13 13.5) (xy 51.75 13.5) (xy 51.75 40.4) (xy 60 40.4) (xy 60 46)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(xy 50.5 46) (xy 50.5 48.5) (xy 13 48.5)
)
)
(filled_polygon
(pts
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 51.625 18.822606) (xy 51.515827 18.749659) (xy 51.35 18.716674) (xy 49.65 18.716674) (xy 49.484173 18.749659)
(xy 49.343592 18.843592) (xy 49.249659 18.984173) (xy 49.216674 19.15) (xy 49.216674 20.85) (xy 49.249659 21.015827)
(xy 49.343592 21.156408) (xy 49.484173 21.250341) (xy 49.65 21.283326) (xy 51.35 21.283326) (xy 51.515827 21.250341)
(xy 51.625 21.177394) (xy 51.625 23.822606) (xy 51.515827 23.749659) (xy 51.35 23.716674) (xy 49.65 23.716674)
(xy 49.484173 23.749659) (xy 49.343592 23.843592) (xy 49.249659 23.984173) (xy 49.216674 24.15) (xy 49.216674 25.85)
(xy 49.249659 26.015827) (xy 49.343592 26.156408) (xy 49.484173 26.250341) (xy 49.65 26.283326) (xy 51.35 26.283326)
(xy 51.515827 26.250341) (xy 51.625 26.177394) (xy 51.625 28.822606) (xy 51.515827 28.749659) (xy 51.35 28.716674)
(xy 49.65 28.716674) (xy 49.484173 28.749659) (xy 49.343592 28.843592) (xy 49.249659 28.984173) (xy 49.216674 29.15)
(xy 49.216674 30.85) (xy 49.249659 31.015827) (xy 49.343592 31.156408) (xy 49.484173 31.250341) (xy 49.65 31.283326)
(xy 51.35 31.283326) (xy 51.515827 31.250341) (xy 51.625 31.177394) (xy 51.625 33.822606) (xy 51.515827 33.749659)
(xy 51.35 33.716674) (xy 49.65 33.716674) (xy 49.484173 33.749659) (xy 49.343592 33.843592) (xy 49.249659 33.984173)
(xy 49.216674 34.15) (xy 49.216674 35.85) (xy 49.249659 36.015827) (xy 49.343592 36.156408) (xy 49.484173 36.250341)
(xy 49.65 36.283326) (xy 51.35 36.283326) (xy 51.515827 36.250341) (xy 51.625 36.177394) (xy 51.625 40.4)
(xy 51.634515 40.447835) (xy 51.661612 40.488388) (xy 51.702165 40.515485) (xy 51.75 40.525) (xy 54.085755 40.525)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 53.809102 40.639593) (xy 53.746991 40.874557) (xy 54.5 41.627566) (xy 55.253009 40.874557) (xy 55.190898 40.639593)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 54.863737 40.525) (xy 59.875 40.525) (xy 59.875 45.875) (xy 50.5 45.875) (xy 50.452165 45.884515)
(xy 50.411612 45.911612) (xy 50.384515 45.952165) (xy 50.375 46) (xy 50.375 48.375) (xy 48.928884 48.375)
(xy 48.861942 48.308058) (xy 48.659177 48.172575) (xy 48.42 48.125) (xy 47.4542 48.125) (xy 47.764715 47.996698)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 48.095536 47.666453) (xy 48.274796 47.234747) (xy 48.275204 46.767303) (xy 48.096698 46.335285) (xy 47.766453 46.004464)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 47.334747 45.825204) (xy 46.867303 45.824796) (xy 46.435285 46.003302) (xy 46.344046 46.094382) (xy 46.340673 46.077425)
(xy 46.327425 46.010822) (xy 46.191942 45.808058) (xy 45.441942 45.058058) (xy 45.239177 44.922575) (xy 45 44.875)
(xy 43.2 44.875) (xy 42.960822 44.922575) (xy 42.879606 44.976842) (xy 42.758058 45.058058) (xy 42.758056 45.058061)
(xy 41.974433 45.841683) (xy 41.934747 45.825204) (xy 41.467303 45.824796) (xy 41.035285 46.003302) (xy 40.704464 46.333547)
(xy 40.599965 46.58521) (xy 40.496698 46.335285) (xy 40.166453 46.004464) (xy 39.734747 45.825204) (xy 39.267303 45.824796)
(xy 38.835285 46.003302) (xy 38.504464 46.333547) (xy 38.375 46.645331) (xy 38.375 45.094212) (xy 38.506408 45.006408)
(xy 38.600341 44.865827) (xy 38.633326 44.7) (xy 38.633326 44.572795) (xy 53.374805 44.572795) (xy 53.545715 44.986429)
(xy 53.861907 45.303172) (xy 54.275242 45.474804) (xy 54.722795 45.475195) (xy 55.136429 45.304285) (xy 55.265939 45.175)
(xy 56.15 45.175) (xy 56.465714 45.112201) (xy 56.583758 45.033326) (xy 56.875 45.033326) (xy 57.040827 45.000341)
(xy 57.181408 44.906408) (xy 57.275341 44.765827) (xy 57.308326 44.6) (xy 57.308326 44.083826) (xy 57.325 44)
(xy 57.308326 43.916174) (xy 57.308326 43.4) (xy 57.275341 43.234173) (xy 57.259593 43.210604) (xy 57.411632 43.058565)
(xy 57.508 42.825911) (xy 57.508 42.38725) (xy 57.34975 42.229) (xy 56.629 42.229) (xy 56.629 42.249)
(xy 56.371 42.249) (xy 56.371 42.229) (xy 56.351 42.229) (xy 56.351 41.971) (xy 56.371 41.971)
(xy 56.371 41.02525) (xy 56.629 41.02525) (xy 56.629 41.971) (xy 57.34975 41.971) (xy 57.508 41.81275)
(xy 57.508 41.374089) (xy 57.411632 41.141435) (xy 57.233566 40.963369) (xy 57.000912 40.867) (xy 56.78725 40.867)
(xy 56.629 41.02525) (xy 56.371 41.02525) (xy 56.21275 40.867) (xy 55.999088 40.867) (xy 55.766434 40.963369)
(xy 55.623184 41.106619) (xy 55.435443 41.056991) (xy 54.682434 41.81) (xy 55.435443 42.563009) (xy 55.492 42.548059)
(xy 55.492 42.825911) (xy 55.588368 43.058565) (xy 55.740407 43.210604) (xy 55.724659 43.234173) (xy 55.691674 43.4)
(xy 55.691674 43.525) (xy 55.266042 43.525) (xy 55.138093 43.396828) (xy 54.724758 43.225196) (xy 54.277205 43.224805)
(xy 53.863571 43.395715) (xy 53.546828 43.711907) (xy 53.375196 44.125242) (xy 53.374805 44.572795) (xy 38.633326 44.572795)
(xy 38.633326 43.5) (xy 38.600341 43.334173) (xy 38.506408 43.193592) (xy 38.381355 43.110035) (xy 38.558566 43.036631)
(xy 38.736632 42.858565) (xy 38.783488 42.745443) (xy 53.746991 42.745443) (xy 53.809102 42.980407) (xy 54.309589 43.15571)
(xy 54.839064 43.126141) (xy 55.190898 42.980407) (xy 55.253009 42.745443) (xy 54.5 41.992434) (xy 53.746991 42.745443)
(xy 38.783488 42.745443) (xy 38.833 42.625911) (xy 38.833 42.18725) (xy 38.67475 42.029) (xy 37.879 42.029)
(xy 37.879 42.049) (xy 37.621 42.049) (xy 37.621 42.029) (xy 36.82525 42.029) (xy 36.667 42.18725)
(xy 36.667 42.625911) (xy 36.763368 42.858565) (xy 36.941434 43.036631) (xy 37.118645 43.110035) (xy 36.993592 43.193592)
(xy 36.899659 43.334173) (xy 36.866674 43.5) (xy 36.866674 44.7) (xy 36.899659 44.865827) (xy 36.993592 45.006408)
(xy 37.125 45.094212) (xy 37.125 47.75) (xy 37.172575 47.989177) (xy 37.308058 48.191942) (xy 37.491116 48.375)
(xy 36.075 48.375) (xy 36.075 47.986518) (xy 36.345536 47.716453) (xy 36.524796 47.284747) (xy 36.525204 46.817303)
(xy 36.346698 46.385285) (xy 36.016453 46.054464) (xy 35.584747 45.875204) (xy 35.117303 45.874796) (xy 34.685285 46.053302)
(xy 34.354464 46.383547) (xy 34.249965 46.63521) (xy 34.146698 46.385285) (xy 33.816453 46.054464) (xy 33.384747 45.875204)
(xy 32.917303 45.874796) (xy 32.485285 46.053302) (xy 32.175659 46.362389) (xy 32.161831 46.329006) (xy 31.921693 46.260741)
(xy 31.132434 47.05) (xy 31.921693 47.839259) (xy 32.161831 47.770994) (xy 32.174309 47.735759) (xy 32.325 47.886712)
(xy 32.325 48.375) (xy 31.39778 48.375) (xy 31.670994 48.261831) (xy 31.739259 48.021693) (xy 30.95 47.232434)
(xy 30.160741 48.021693) (xy 30.229006 48.261831) (xy 30.548565 48.375) (xy 26.925 48.375) (xy 26.925 47.886712)
(xy 27.083547 48.045536) (xy 27.515253 48.224796) (xy 27.982697 48.225204) (xy 28.414715 48.046698) (xy 28.745536 47.716453)
(xy 28.924796 47.284747) (xy 28.925177 46.847635) (xy 29.554501 46.847635) (xy 29.583286 47.397073) (xy 29.738169 47.770994)
(xy 29.978307 47.839259) (xy 30.767566 47.05) (xy 29.978307 46.260741) (xy 29.738169 46.329006) (xy 29.554501 46.847635)
(xy 28.925177 46.847635) (xy 28.925204 46.817303) (xy 28.746698 46.385285) (xy 28.475 46.113113) (xy 28.475 46.078307)
(xy 30.160741 46.078307) (xy 30.95 46.867566) (xy 31.739259 46.078307) (xy 31.670994 45.838169) (xy 31.152365 45.654501)
(xy 30.602927 45.683286) (xy 30.229006 45.838169) (xy 30.160741 46.078307) (xy 28.475 46.078307) (xy 28.475 43.777394)
(xy 28.506408 43.756408) (xy 28.600341 43.615827) (xy 28.633326 43.45) (xy 28.633326 42.25) (xy 28.600341 42.084173)
(xy 28.506408 41.943592) (xy 28.381355 41.860035) (xy 28.558566 41.786631) (xy 28.736632 41.608565) (xy 28.833 41.375911)
(xy 28.833 41.174089) (xy 36.667 41.174089) (xy 36.667 41.61275) (xy 36.82525 41.771) (xy 37.621 41.771)
(xy 37.621 40.82525) (xy 37.879 40.82525) (xy 37.879 41.771) (xy 38.67475 41.771) (xy 38.826161 41.619589)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 53.15429 41.619589) (xy 53.183859 42.149064) (xy 53.329593 42.500898) (xy 53.564557 42.563009) (xy 54.317566 41.81)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 53.564557 41.056991) (xy 53.329593 41.119102) (xy 53.15429 41.619589) (xy 38.826161 41.619589) (xy 38.833 41.61275)
(xy 38.833 41.174089) (xy 38.736632 40.941435) (xy 38.558566 40.763369) (xy 38.325912 40.667) (xy 38.03725 40.667)
(xy 37.879 40.82525) (xy 37.621 40.82525) (xy 37.46275 40.667) (xy 37.174088 40.667) (xy 36.941434 40.763369)
(xy 36.763368 40.941435) (xy 36.667 41.174089) (xy 28.833 41.174089) (xy 28.833 40.93725) (xy 28.67475 40.779)
(xy 27.879 40.779) (xy 27.879 40.799) (xy 27.621 40.799) (xy 27.621 40.779) (xy 26.82525 40.779)
(xy 26.667 40.93725) (xy 26.667 41.375911) (xy 26.763368 41.608565) (xy 26.941434 41.786631) (xy 27.118645 41.860035)
(xy 26.993592 41.943592) (xy 26.899659 42.084173) (xy 26.866674 42.25) (xy 26.866674 43.45) (xy 26.899659 43.615827)
(xy 26.993592 43.756408) (xy 27.025 43.777394) (xy 27.025 46.113482) (xy 26.925 46.213308) (xy 26.925 44.5)
(xy 26.892649 44.33736) (xy 26.80052 44.19948) (xy 26.66264 44.107351) (xy 26.5 44.075) (xy 26.045057 44.075)
(xy 26.045117 44.006323) (xy 25.942571 43.758143) (xy 25.752856 43.568097) (xy 25.504855 43.465117) (xy 25.236323 43.464883)
(xy 25.115031 43.515) (xy 23.344299 43.515) (xy 23.30052 43.44948) (xy 23.16264 43.357351) (xy 23 43.325)
(xy 14.5 43.325) (xy 14.33736 43.357351) (xy 14.19948 43.44948) (xy 14.107351 43.58736) (xy 14.075 43.75)
(xy 14.075 44.066674) (xy 13.95 44.066674) (xy 13.784173 44.099659) (xy 13.643592 44.193592) (xy 13.549659 44.334173)
(xy 13.516674 44.5) (xy 13.516674 46.5) (xy 13.549659 46.665827) (xy 13.643592 46.806408) (xy 13.784173 46.900341)
(xy 13.95 46.933326) (xy 14.075 46.933326) (xy 14.075 48.375) (xy 13.5 48.375) (xy 13.5 39.924089)
(xy 26.667 39.924089) (xy 26.667 40.36275) (xy 26.82525 40.521) (xy 27.621 40.521) (xy 27.621 39.57525)
(xy 27.879 39.57525) (xy 27.879 40.521) (xy 28.67475 40.521) (xy 28.833 40.36275) (xy 28.833 39.924089)
(xy 28.736632 39.691435) (xy 28.558566 39.513369) (xy 28.325912 39.417) (xy 28.03725 39.417) (xy 27.879 39.57525)
(xy 27.621 39.57525) (xy 27.46275 39.417) (xy 27.174088 39.417) (xy 26.941434 39.513369) (xy 26.763368 39.691435)
(xy 26.667 39.924089) (xy 13.5 39.924089) (xy 13.5 39.119175) (xy 31.263258 39.119175) (xy 31.319209 39.34897)
(xy 31.801547 39.515905) (xy 32.311052 39.485551) (xy 32.640791 39.34897) (xy 32.696742 39.119175) (xy 31.98 38.402434)
(xy 31.263258 39.119175) (xy 13.5 39.119175) (xy 13.5 38.041547) (xy 30.684095 38.041547) (xy 30.714449 38.551052)
(xy 30.85103 38.880791) (xy 31.080825 38.936742) (xy 31.797566 38.22) (xy 32.162434 38.22) (xy 32.879175 38.936742)
(xy 33.10897 38.880791) (xy 33.275905 38.398453) (xy 33.245551 37.888948) (xy 33.10897 37.559209) (xy 32.879175 37.503258)
(xy 32.162434 38.22) (xy 31.797566 38.22) (xy 31.080825 37.503258) (xy 30.85103 37.559209) (xy 30.684095 38.041547)
(xy 13.5 38.041547) (xy 13.5 35.57) (xy 30.896674 35.57) (xy 30.896674 36.87) (xy 30.929659 37.035827)
(xy 31.023592 37.176408) (xy 31.164173 37.270341) (xy 31.270405 37.291472) (xy 31.263258 37.320825) (xy 31.98 38.037566)
(xy 32.696742 37.320825) (xy 32.689595 37.291472) (xy 32.795827 37.270341) (xy 32.936408 37.176408) (xy 33.030341 37.035827)
(xy 33.063326 36.87) (xy 33.063326 35.57) (xy 33.030341 35.404173) (xy 32.936408 35.263592) (xy 32.795827 35.169659)
(xy 32.63 35.136674) (xy 31.33 35.136674) (xy 31.164173 35.169659) (xy 31.023592 35.263592) (xy 30.929659 35.404173)
(xy 30.896674 35.57) (xy 13.5 35.57) (xy 13.5 32.92725) (xy 34.742 32.92725) (xy 34.742 33.365911)
(xy 34.838368 33.598565) (xy 34.990407 33.750604) (xy 34.974659 33.774173) (xy 34.941674 33.94) (xy 34.941674 35.14)
(xy 34.974659 35.305827) (xy 35.068592 35.446408) (xy 35.209173 35.540341) (xy 35.375 35.573326) (xy 35.809442 35.573326)
(xy 36.585562 36.349446) (xy 36.685016 36.590143) (xy 36.888784 36.794267) (xy 37.155156 36.904874) (xy 37.443579 36.905126)
(xy 37.710143 36.794984) (xy 37.914267 36.591216) (xy 38.024874 36.324844) (xy 38.025126 36.036421) (xy 37.914984 35.769857)
(xy 37.711216 35.565733) (xy 37.469069 35.465185) (xy 36.791134 34.78725) (xy 37.317 34.78725) (xy 37.317 35.000912)
(xy 37.413369 35.233566) (xy 37.591435 35.411632) (xy 37.824089 35.508) (xy 38.26275 35.508) (xy 38.421 35.34975)
(xy 38.421 34.629) (xy 37.47525 34.629) (xy 37.317 34.78725) (xy 36.791134 34.78725) (xy 36.558326 34.554442)
(xy 36.558326 33.999088) (xy 37.317 33.999088) (xy 37.317 34.21275) (xy 37.47525 34.371) (xy 38.421 34.371)
(xy 38.421 33.65025) (xy 38.679 33.65025) (xy 38.679 34.371) (xy 38.699 34.371) (xy 38.699 34.629)
(xy 38.679 34.629) (xy 38.679 35.34975) (xy 38.83725 35.508) (xy 39.275911 35.508) (xy 39.508565 35.411632)
(xy 39.660604 35.259593) (xy 39.684173 35.275341) (xy 39.85 35.308326) (xy 41.05 35.308326) (xy 41.215827 35.275341)
(xy 41.278015 35.233789) (xy 41.425145 35.294883) (xy 41.693677 35.295117) (xy 41.941857 35.192571) (xy 42.131903 35.002856)
(xy 42.234883 34.754855) (xy 42.234965 34.660785) (xy 42.371 34.52475) (xy 42.371 33.579) (xy 42.629 33.579)
(xy 42.629 34.52475) (xy 42.78725 34.683) (xy 43.000912 34.683) (xy 43.233566 34.586631) (xy 43.411632 34.408565)
(xy 43.508 34.175911) (xy 43.508 33.73725) (xy 43.34975 33.579) (xy 42.629 33.579) (xy 42.371 33.579)
(xy 41.65025 33.579) (xy 41.492 33.73725) (xy 41.492 33.94494) (xy 41.440801 33.944896) (xy 41.356408 33.818592)
(xy 41.215827 33.724659) (xy 41.05 33.691674) (xy 39.85 33.691674) (xy 39.684173 33.724659) (xy 39.660604 33.740407)
(xy 39.508565 33.588368) (xy 39.275911 33.492) (xy 38.83725 33.492) (xy 38.679 33.65025) (xy 38.421 33.65025)
(xy 38.26275 33.492) (xy 37.824089 33.492) (xy 37.591435 33.588368) (xy 37.413369 33.766434) (xy 37.317 33.999088)
(xy 36.558326 33.999088) (xy 36.558326 33.94) (xy 36.525341 33.774173) (xy 36.509593 33.750604) (xy 36.661632 33.598565)
(xy 36.758 33.365911) (xy 36.758 32.92725) (xy 36.59975 32.769) (xy 35.879 32.769) (xy 35.879 32.789)
(xy 35.621 32.789) (xy 35.621 32.769) (xy 34.90025 32.769) (xy 34.742 32.92725) (xy 13.5 32.92725)
(xy 13.5 32.724089) (xy 41.492 32.724089) (xy 41.492 33.16275) (xy 41.65025 33.321) (xy 42.371 33.321)
(xy 42.371 33.301) (xy 42.629 33.301) (xy 42.629 33.321) (xy 43.34975 33.321) (xy 43.508 33.16275)
(xy 43.508 32.724089) (xy 43.411632 32.491435) (xy 43.259593 32.339396) (xy 43.275341 32.315827) (xy 43.308326 32.15)
(xy 43.308326 32.1) (xy 44.385436 32.1) (xy 44.497144 32.211903) (xy 44.745145 32.314883) (xy 45.013677 32.315117)
(xy 45.261857 32.212571) (xy 45.451903 32.022856) (xy 45.554883 31.774855) (xy 45.555117 31.506323) (xy 45.452571 31.258143)
(xy 45.262856 31.068097) (xy 45.014855 30.965117) (xy 44.746323 30.964883) (xy 44.661333 31) (xy 43.308326 31)
(xy 43.308326 30.95) (xy 43.275341 30.784173) (xy 43.181408 30.643592) (xy 43.040827 30.549659) (xy 42.875 30.516674)
(xy 42.125 30.516674) (xy 41.959173 30.549659) (xy 41.818592 30.643592) (xy 41.724659 30.784173) (xy 41.691674 30.95)
(xy 41.691674 32.15) (xy 41.724659 32.315827) (xy 41.740407 32.339396) (xy 41.588368 32.491435) (xy 41.492 32.724089)
(xy 13.5 32.724089) (xy 13.5 31.914089) (xy 34.742 31.914089) (xy 34.742 32.35275) (xy 34.90025 32.511)
(xy 35.621 32.511) (xy 35.621 31.56525) (xy 35.879 31.56525) (xy 35.879 32.511) (xy 36.59975 32.511)
(xy 36.758 32.35275) (xy 36.758 31.914089) (xy 36.661632 31.681435) (xy 36.483566 31.503369) (xy 36.250912 31.407)
(xy 36.03725 31.407) (xy 35.879 31.56525) (xy 35.621 31.56525) (xy 35.46275 31.407) (xy 35.249088 31.407)
(xy 35.016434 31.503369) (xy 34.838368 31.681435) (xy 34.742 31.914089) (xy 13.5 31.914089) (xy 13.5 30.872841)
(xy 15.976169 30.872841) (xy 16.109035 31.194403) (xy 16.354843 31.44064) (xy 16.676172 31.574068) (xy 17.024101 31.574371)
(xy 17.345663 31.441505) (xy 17.5919 31.195697) (xy 17.725328 30.874368) (xy 17.725631 30.526439) (xy 17.592765 30.204877)
(xy 17.346957 29.95864) (xy 17.025628 29.825212) (xy 16.677699 29.824909) (xy 16.356137 29.957775) (xy 16.1099 30.203583)
(xy 15.976472 30.524912) (xy 15.976169 30.872841) (xy 13.5 30.872841) (xy 13.5 29.173677) (xy 21.844883 29.173677)
(xy 21.947429 29.421857) (xy 22.137144 29.611903) (xy 22.385145 29.714883) (xy 22.417093 29.714911) (xy 22.591091 29.888909)
(xy 22.769524 30.008134) (xy 22.882716 30.030649) (xy 22.899659 30.115827) (xy 22.993592 30.256408) (xy 23.134173 30.350341)
(xy 23.3 30.383326) (xy 24.5 30.383326) (xy 24.665827 30.350341) (xy 24.806408 30.256408) (xy 24.900341 30.115827)
(xy 24.933326 29.95) (xy 24.933326 29.05) (xy 25.066674 29.05) (xy 25.066674 29.95) (xy 25.099659 30.115827)
(xy 25.193592 30.256408) (xy 25.334173 30.350341) (xy 25.5 30.383326) (xy 26.7 30.383326) (xy 26.865827 30.350341)
(xy 27.006408 30.256408) (xy 27.100341 30.115827) (xy 27.113435 30.05) (xy 27.15 30.05) (xy 27.360476 30.008134)
(xy 27.538909 29.888909) (xy 28.922727 28.50509) (xy 28.953677 28.505117) (xy 29.201857 28.402571) (xy 29.391903 28.212856)
(xy 29.494883 27.964855) (xy 29.495117 27.696323) (xy 29.392571 27.448143) (xy 29.202856 27.258097) (xy 28.954855 27.155117)
(xy 28.686323 27.154883) (xy 28.438143 27.257429) (xy 28.248097 27.447144) (xy 28.145117 27.695145) (xy 28.145089 27.727094)
(xy 27.055347 28.816835) (xy 27.006408 28.743592) (xy 26.865827 28.649659) (xy 26.7 28.616674) (xy 25.5 28.616674)
(xy 25.334173 28.649659) (xy 25.193592 28.743592) (xy 25.099659 28.884173) (xy 25.066674 29.05) (xy 24.933326 29.05)
(xy 24.900341 28.884173) (xy 24.806408 28.743592) (xy 24.665827 28.649659) (xy 24.5 28.616674) (xy 23.3 28.616674)
(xy 23.134173 28.649659) (xy 23.098825 28.673278) (xy 23.092571 28.658143) (xy 22.902856 28.468097) (xy 22.654855 28.365117)
(xy 22.386323 28.364883) (xy 22.138143 28.467429) (xy 21.948097 28.657144) (xy 21.845117 28.905145) (xy 21.844883 29.173677)
(xy 13.5 29.173677) (xy 13.5 26.473561) (xy 15.976169 26.473561) (xy 16.109035 26.795123) (xy 16.354843 27.04136)
(xy 16.676172 27.174788) (xy 17.024101 27.175091) (xy 17.345663 27.042225) (xy 17.5919 26.796417) (xy 17.725328 26.475088)
(xy 17.725631 26.127159) (xy 17.592765 25.805597) (xy 17.346957 25.55936) (xy 17.025628 25.425932) (xy 16.677699 25.425629)
(xy 16.356137 25.558495) (xy 16.1099 25.804303) (xy 15.976472 26.125632) (xy 15.976169 26.473561) (xy 13.5 26.473561)
(xy 13.5 18.78725) (xy 17.467 18.78725) (xy 17.467 19.525911) (xy 17.563368 19.758565) (xy 17.741434 19.936631)
(xy 17.974088 20.033) (xy 18.133289 20.033) (xy 17.877375 20.288468) (xy 17.675231 20.775285) (xy 17.674771 21.302402)
(xy 17.876065 21.789572) (xy 18.248468 22.162625) (xy 18.735285 22.364769) (xy 19.262402 22.365229) (xy 19.749572 22.163935)
(xy 20.122625 21.791532) (xy 20.324769 21.304715) (xy 20.325229 20.777598) (xy 20.123935 20.290428) (xy 19.866956 20.033)
(xy 20.025912 20.033) (xy 20.258566 19.936631) (xy 20.436632 19.758565) (xy 20.533 19.525911) (xy 20.533 18.78725)
(xy 20.37475 18.629) (xy 19.129 18.629) (xy 19.129 18.649) (xy 18.871 18.649) (xy 18.871 18.629)
(xy 17.62525 18.629) (xy 17.467 18.78725) (xy 13.5 18.78725) (xy 13.5 17.474089) (xy 17.467 17.474089)
(xy 17.467 18.21275) (xy 17.62525 18.371) (xy 18.871 18.371) (xy 18.871 17.12525) (xy 19.129 17.12525)
(xy 19.129 18.371) (xy 20.37475 18.371) (xy 20.533 18.21275) (xy 20.533 17.474089) (xy 20.436632 17.241435)
(xy 20.258566 17.063369) (xy 20.025912 16.967) (xy 19.28725 16.967) (xy 19.129 17.12525) (xy 18.871 17.12525)
(xy 18.71275 16.967) (xy 17.974088 16.967) (xy 17.741434 17.063369) (xy 17.563368 17.241435) (xy 17.467 17.474089)
(xy 13.5 17.474089) (xy 13.5 14) (xy 51.625 14)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
)
)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(zone (net 13) (net_name GNDPWR) (layer B.Cu) (tstamp 0) (hatch edge 0.508)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(connect_pads (clearance 0.3))
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(min_thickness 0.25)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 29.5 49) (xy 29.5 51) (xy 29.5 51.5) (xy 14.5 51.5) (xy 14.5 61.5)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 112 61.5) (xy 112 16) (xy 53 16) (xy 53 39.5) (xy 61.5 39.5)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
(xy 61.5 47.5) (xy 52 47.5) (xy 52 50) (xy 32 50) (xy 32 49)
)
)
(filled_polygon
(pts
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(xy 111.875 20.167287) (xy 111.83354 20.148894) (xy 110.682434 21.3) (xy 111.83354 22.451106) (xy 111.875 22.432713)
(xy 111.875 31.706524) (xy 111.45005 31.280832) (xy 110.83464 31.025292) (xy 110.168284 31.02471) (xy 109.552428 31.279176)
(xy 109.080832 31.74995) (xy 108.825292 32.36536) (xy 108.82471 33.031716) (xy 109.079176 33.647572) (xy 109.54995 34.119168)
(xy 110.16536 34.374708) (xy 110.831716 34.37529) (xy 111.447572 34.120824) (xy 111.875 33.694141) (xy 111.875 43.241116)
(xy 109.705 41.071116) (xy 109.705 38.526092) (xy 109.751503 38.506877) (xy 110.085703 38.17326) (xy 110.266794 37.737145)
(xy 110.267206 37.264927) (xy 110.086877 36.828497) (xy 109.75326 36.494297) (xy 109.317145 36.313206) (xy 108.844927 36.312794)
(xy 108.408497 36.493123) (xy 108.074297 36.82674) (xy 107.893206 37.262855) (xy 107.892794 37.735073) (xy 108.073123 38.171503)
(xy 108.40674 38.505703) (xy 108.455 38.525742) (xy 108.455 41.33) (xy 108.502575 41.569177) (xy 108.638058 41.771942)
(xy 111.685 44.818884) (xy 111.685 48.801117) (xy 111.341941 48.458057) (xy 111.27308 48.389196) (xy 111.324769 48.264715)
(xy 111.325229 47.737598) (xy 111.123935 47.250428) (xy 110.751532 46.877375) (xy 110.444625 46.749936) (xy 110.749572 46.623935)
(xy 111.122625 46.251532) (xy 111.324769 45.764715) (xy 111.325229 45.237598) (xy 111.123935 44.750428) (xy 110.751532 44.377375)
(xy 110.264715 44.175231) (xy 109.737598 44.174771) (xy 109.250428 44.376065) (xy 108.877375 44.748468) (xy 108.749936 45.055375)
(xy 108.623935 44.750428) (xy 108.251532 44.377375) (xy 107.764715 44.175231) (xy 107.237598 44.174771) (xy 106.750428 44.376065)
(xy 106.377375 44.748468) (xy 106.175231 45.235285) (xy 106.174771 45.762402) (xy 106.376065 46.249572) (xy 106.748468 46.622625)
(xy 107.055375 46.750064) (xy 106.750428 46.876065) (xy 106.377375 47.248468) (xy 106.175231 47.735285) (xy 106.174771 48.262402)
(xy 106.376065 48.749572) (xy 106.748468 49.122625) (xy 106.768501 49.130943) (xy 106.68877 49.163969) (xy 106.602083 49.419649)
(xy 107.5 50.317566) (xy 108.397917 49.419649) (xy 108.31123 49.163969) (xy 108.226969 49.133274) (xy 108.249572 49.123935)
(xy 108.622625 48.751532) (xy 108.750064 48.444625) (xy 108.876065 48.749572) (xy 109.248468 49.122625) (xy 109.268501 49.130943)
(xy 109.18877 49.163969) (xy 109.102083 49.419649) (xy 110 50.317566) (xy 110.014142 50.303424) (xy 110.196576 50.485858)
(xy 110.182434 50.5) (xy 110.196576 50.514142) (xy 110.014142 50.696576) (xy 110 50.682434) (xy 109.102083 51.580351)
(xy 109.18877 51.836031) (xy 109.761798 52.044776) (xy 110.37109 52.018343) (xy 110.805 51.838612) (xy 110.805 52.561117)
(xy 110.386096 52.98002) (xy 110.265827 52.899659) (xy 110.1 52.866674) (xy 108.9 52.866674) (xy 108.734173 52.899659)
(xy 108.593592 52.993592) (xy 108.499659 53.134173) (xy 108.466674 53.3) (xy 108.466674 54.2) (xy 108.499659 54.365827)
(xy 108.505788 54.375) (xy 108.294212 54.375) (xy 108.300341 54.365827) (xy 108.333326 54.2) (xy 108.333326 53.3)
(xy 108.300341 53.134173) (xy 108.206408 52.993592) (xy 108.065827 52.899659) (xy 107.9 52.866674) (xy 106.7 52.866674)
(xy 106.534173 52.899659) (xy 106.393592 52.993592) (xy 106.299659 53.134173) (xy 106.266674 53.3) (xy 106.266674 53.749443)
(xy 105.735 54.281116) (xy 105.735 51.580351) (xy 106.602083 51.580351) (xy 106.68877 51.836031) (xy 107.261798 52.044776)
(xy 107.87109 52.018343) (xy 108.31123 51.836031) (xy 108.397917 51.580351) (xy 107.5 50.682434) (xy 106.602083 51.580351)
(xy 105.735 51.580351) (xy 105.735 51.04) (xy 105.725485 50.992165) (xy 105.698388 50.951612) (xy 105.657835 50.924515)
(xy 105.61 50.915) (xy 102.19 50.915) (xy 102.142165 50.924515) (xy 102.101612 50.951612) (xy 102.074515 50.992165)
(xy 102.065 51.04) (xy 102.065 54.54) (xy 102.074515 54.587835) (xy 102.101612 54.628388) (xy 102.142165 54.655485)
(xy 102.19 54.665) (xy 105.421744 54.665) (xy 105.375 54.9) (xy 105.375 55.114632) (xy 105.275126 55.355156)
(xy 105.274874 55.643579) (xy 105.385016 55.910143) (xy 105.588784 56.114267) (xy 105.855156 56.224874) (xy 106.143579 56.225126)
(xy 106.410143 56.114984) (xy 106.614267 55.911216) (xy 106.724874 55.644844) (xy 106.725126 55.356421) (xy 106.638095 55.145789)
(xy 106.95 54.833884) (xy 107.558056 55.441939) (xy 107.558058 55.441942) (xy 107.760823 55.577425) (xy 108 55.625)
(xy 110.5 55.625) (xy 110.739177 55.577425) (xy 110.941942 55.441942) (xy 110.941943 55.441941) (xy 111.875 54.508883)
(xy 111.875 61.375) (xy 14.625 61.375) (xy 14.625 55.65) (xy 37.216674 55.65) (xy 37.216674 57.35)
(xy 37.249659 57.515827) (xy 37.343592 57.656408) (xy 37.484173 57.750341) (xy 37.65 57.783326) (xy 39.35 57.783326)
(xy 39.515827 57.750341) (xy 39.656408 57.656408) (xy 39.750341 57.515827) (xy 39.77 57.416994) (xy 39.789659 57.515827)
(xy 39.883592 57.656408) (xy 40.024173 57.750341) (xy 40.19 57.783326) (xy 41.89 57.783326) (xy 42.055827 57.750341)
(xy 42.196408 57.656408) (xy 42.290341 57.515827) (xy 42.323326 57.35) (xy 42.323326 56.72725) (xy 46.707 56.72725)
(xy 46.707 57.015912) (xy 46.803369 57.248566) (xy 46.981435 57.426632) (xy 47.214089 57.523) (xy 47.65275 57.523)
(xy 47.811 57.36475) (xy 47.811 56.569) (xy 46.86525 56.569) (xy 46.707 56.72725) (xy 42.323326 56.72725)
(xy 42.323326 55.864088) (xy 46.707 55.864088) (xy 46.707 56.15275) (xy 46.86525 56.311) (xy 47.811 56.311)
(xy 47.811 55.51525) (xy 47.65275 55.357) (xy 47.214089 55.357) (xy 46.981435 55.453368) (xy 46.803369 55.631434)
(xy 46.707 55.864088) (xy 42.323326 55.864088) (xy 42.323326 55.65) (xy 42.290341 55.484173) (xy 42.196408 55.343592)
(xy 42.055827 55.249659) (xy 41.89 55.216674) (xy 40.19 55.216674) (xy 40.024173 55.249659) (xy 39.883592 55.343592)
(xy 39.789659 55.484173) (xy 39.77 55.583006) (xy 39.750341 55.484173) (xy 39.656408 55.343592) (xy 39.515827 55.249659)
(xy 39.35 55.216674) (xy 37.65 55.216674) (xy 37.484173 55.249659) (xy 37.343592 55.343592) (xy 37.249659 55.484173)
(xy 37.216674 55.65) (xy 14.625 55.65) (xy 14.625 53.675) (xy 26.5 53.675) (xy 26.66264 53.642649)
(xy 26.80052 53.55052) (xy 26.892649 53.41264) (xy 26.925 53.25) (xy 26.925 51.625) (xy 29.5 51.625)
(xy 29.547835 51.615485) (xy 29.588388 51.588388) (xy 29.615485 51.547835) (xy 29.625 51.5) (xy 29.625 49.125)
(xy 30.225 49.125) (xy 30.225 49.313482) (xy 29.954464 49.583547) (xy 29.775204 50.015253) (xy 29.774796 50.482697)
(xy 29.953302 50.914715) (xy 30.283547 51.245536) (xy 30.715253 51.424796) (xy 31.182697 51.425204) (xy 31.614715 51.246698)
(xy 31.639763 51.221693) (xy 32.360741 51.221693) (xy 32.429006 51.461831) (xy 32.947635 51.645499) (xy 33.497073 51.616714)
(xy 33.870994 51.461831) (xy 33.939259 51.221693) (xy 33.15 50.432434) (xy 32.360741 51.221693) (xy 31.639763 51.221693)
(xy 31.924341 50.937611) (xy 31.938169 50.970994) (xy 32.178307 51.039259) (xy 32.967566 50.25) (xy 32.953424 50.235858)
(xy 33.064282 50.125) (xy 33.235718 50.125) (xy 33.346576 50.235858) (xy 33.332434 50.25) (xy 34.121693 51.039259)
(xy 34.361831 50.970994) (xy 34.374309 50.935759) (xy 34.683547 51.245536) (xy 35.115253 51.424796) (xy 35.582697 51.425204)
(xy 36.014715 51.246698) (xy 36.345536 50.916453) (xy 36.524796 50.484747) (xy 36.52511 50.125) (xy 38.325065 50.125)
(xy 38.324796 50.432697) (xy 38.503302 50.864715) (xy 38.833547 51.195536) (xy 39.265253 51.374796) (xy 39.732697 51.375204)
(xy 40.164715 51.196698) (xy 40.495536 50.866453) (xy 40.600035 50.61479) (xy 40.703302 50.864715) (xy 41.033547 51.195536)
(xy 41.075 51.212749) (xy 41.075 51.26066) (xy 41.122575 51.499837) (xy 41.258058 51.702602) (xy 42.197396 52.641939)
(xy 42.197398 52.641942) (xy 42.318946 52.723158) (xy 42.400162 52.777425) (xy 42.63934 52.825) (xy 48.191116 52.825)
(xy 51.256117 55.89) (xy 51.153435 55.89) (xy 51.140341 55.824173) (xy 51.046408 55.683592) (xy 50.905827 55.589659)
(xy 50.74 55.556674) (xy 49.54 55.556674) (xy 49.374173 55.589659) (xy 49.233592 55.683592) (xy 49.150035 55.808645)
(xy 49.076631 55.631434) (xy 48.898565 55.453368) (xy 48.665911 55.357) (xy 48.22725 55.357) (xy 48.069 55.51525)
(xy 48.069 56.311) (xy 48.089 56.311) (xy 48.089 56.569) (xy 48.069 56.569) (xy 48.069 57.36475)
(xy 48.22725 57.523) (xy 48.665911 57.523) (xy 48.898565 57.426632) (xy 49.076631 57.248566) (xy 49.150035 57.071355)
(xy 49.233592 57.196408) (xy 49.374173 57.290341) (xy 49.54 57.323326) (xy 50.74 57.323326) (xy 50.905827 57.290341)
(xy 51.046408 57.196408) (xy 51.140341 57.055827) (xy 51.153435 56.99) (xy 51.65 56.99) (xy 51.860476 56.948134)
(xy 52.038909 56.828909) (xy 52.222771 56.645047) (xy 52.313579 56.645126) (xy 52.580143 56.534984) (xy 52.784267 56.331216)
(xy 52.806538 56.277579) (xy 68.616874 56.277579) (xy 68.727016 56.544143) (xy 68.930784 56.748267) (xy 68.93109 56.748394)
(xy 71.877348 59.694652) (xy 72.112554 59.851813) (xy 72.158585 59.860969) (xy 72.39 59.907) (xy 78.74 59.907)
(xy 78.971415 59.860969) (xy 79.017446 59.851813) (xy 79.252652 59.694652) (xy 79.453725 59.493579) (xy 81.584874 59.493579)
(xy 81.695016 59.760143) (xy 81.898784 59.964267) (xy 82.165156 60.074874) (xy 82.453579 60.075126) (xy 82.695902 59.975)
(xy 91.409549 59.975) (xy 91.428782 59.994267) (xy 91.695154 60.104874) (xy 91.983577 60.105126) (xy 92.250141 59.994984)
(xy 92.454265 59.791216) (xy 92.564872 59.524844) (xy 92.565124 59.236421) (xy 92.454982 58.969857) (xy 92.251214 58.765733)
(xy 91.984842 58.655126) (xy 91.696419 58.654874) (xy 91.526701 58.725) (xy 82.695368 58.725) (xy 82.454844 58.625126)
(xy 82.166421 58.624874) (xy 81.899857 58.735016) (xy 81.695733 58.938784) (xy 81.585126 59.205156) (xy 81.584874 59.493579)
(xy 79.453725 59.493579) (xy 80.362305 58.585) (xy 96.318 58.585) (xy 96.549415 58.538969) (xy 96.595446 58.529813)
(xy 96.830652 58.372652) (xy 97.292653 57.910652) (xy 97.30229 57.896229) (xy 97.319 57.907394) (xy 97.319 58.734797)
(xy 97.193592 58.818592) (xy 97.099659 58.959173) (xy 97.066674 59.125) (xy 97.066674 59.875) (xy 97.099659 60.040827)
(xy 97.193592 60.181408) (xy 97.334173 60.275341) (xy 97.5 60.308326) (xy 98.7 60.308326) (xy 98.865827 60.275341)
(xy 98.889396 60.259593) (xy 99.041435 60.411632) (xy 99.274089 60.508) (xy 99.71275 60.508) (xy 99.871 60.34975)
(xy 99.871 59.629) (xy 100.129 59.629) (xy 100.129 60.34975) (xy 100.28725 60.508) (xy 100.725911 60.508)
(xy 100.958565 60.411632) (xy 101.136631 60.233566) (xy 101.233 60.000912) (xy 101.233 59.78725) (xy 101.07475 59.629)
(xy 100.129 59.629) (xy 99.871 59.629) (xy 99.851 59.629) (xy 99.851 59.371) (xy 99.871 59.371)
(xy 99.871 58.65025) (xy 100.129 58.65025) (xy 100.129 59.371) (xy 101.07475 59.371) (xy 101.233 59.21275)
(xy 101.233 58.999088) (xy 101.136631 58.766434) (xy 100.958565 58.588368) (xy 100.725911 58.492) (xy 100.28725 58.492)
(xy 100.129 58.65025) (xy 99.871 58.65025) (xy 99.71275 58.492) (xy 99.274089 58.492) (xy 99.041435 58.588368)
(xy 98.889396 58.740407) (xy 98.865827 58.724659) (xy 98.769 58.705399) (xy 98.769 57.907394) (xy 98.800408 57.886408)
(xy 98.894341 57.745827) (xy 98.902462 57.705) (xy 98.98 57.705) (xy 99.22429 57.656408) (xy 99.257446 57.649813)
(xy 99.492652 57.492652) (xy 100.262205 56.7231) (xy 100.364267 56.621216) (xy 100.474874 56.354844) (xy 100.475126 56.066421)
(xy 100.364984 55.799857) (xy 100.161216 55.595733) (xy 99.894844 55.485126) (xy 99.606421 55.484874) (xy 99.339857 55.595016)
(xy 99.135733 55.798784) (xy 99.135607 55.799089) (xy 98.824719 56.109976) (xy 98.800408 56.073592) (xy 98.659827 55.979659)
(xy 98.494 55.946674) (xy 97.594 55.946674) (xy 97.505 55.964377) (xy 97.505 55.795623) (xy 97.594 55.813326)
(xy 98.494 55.813326) (xy 98.659827 55.780341) (xy 98.800408 55.686408) (xy 98.894341 55.545827) (xy 98.927326 55.38)
(xy 98.927326 54.18) (xy 98.894341 54.014173) (xy 98.800408 53.873592) (xy 98.669 53.785788) (xy 98.669 53.735181)
(xy 98.724089 53.758) (xy 99.16275 53.758) (xy 99.321 53.59975) (xy 99.321 52.879) (xy 99.579 52.879)
(xy 99.579 53.59975) (xy 99.73725 53.758) (xy 100.175911 53.758) (xy 100.408565 53.661632) (xy 100.586631 53.483566)
(xy 100.683 53.250912) (xy 100.683 53.03725) (xy 100.52475 52.879) (xy 99.579 52.879) (xy 99.321 52.879)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 99.301 52.879) (xy 99.301 52.621) (xy 99.321 52.621) (xy 99.321 51.90025) (xy 99.579 51.90025)
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(xy 99.579 52.621) (xy 100.52475 52.621) (xy 100.683 52.46275) (xy 100.683 52.249088) (xy 100.586631 52.016434)
(xy 100.408565 51.838368) (xy 100.175911 51.742) (xy 99.73725 51.742) (xy 99.579 51.90025) (xy 99.321 51.90025)
(xy 99.16275 51.742) (xy 98.724089 51.742) (xy 98.491435 51.838368) (xy 98.339396 51.990407) (xy 98.315827 51.974659)
(xy 98.15 51.941674) (xy 96.95 51.941674) (xy 96.784173 51.974659) (xy 96.643592 52.068592) (xy 96.549659 52.209173)
(xy 96.516674 52.375) (xy 96.516674 53.125) (xy 96.549659 53.290827) (xy 96.643592 53.431408) (xy 96.784173 53.525341)
(xy 96.95 53.558326) (xy 97.419 53.558326) (xy 97.419 53.785788) (xy 97.287592 53.873592) (xy 97.193659 54.014173)
(xy 97.185538 54.055) (xy 96.994 54.055) (xy 96.716554 54.110187) (xy 96.481348 54.267347) (xy 96.275059 54.473637)
(xy 96.275126 54.396421) (xy 96.164984 54.129857) (xy 95.961216 53.925733) (xy 95.694844 53.815126) (xy 95.406421 53.814874)
(xy 95.139857 53.925016) (xy 94.935733 54.128784) (xy 94.825126 54.395156) (xy 94.825107 54.417238) (xy 94.762575 54.510823)
(xy 94.715 54.75) (xy 94.715 55.561647) (xy 94.574173 55.589659) (xy 94.433592 55.683592) (xy 94.350035 55.808645)
(xy 94.276631 55.631434) (xy 94.098565 55.453368) (xy 93.865911 55.357) (xy 93.42725 55.357) (xy 93.269 55.51525)
(xy 93.269 56.311) (xy 93.289 56.311) (xy 93.289 56.569) (xy 93.269 56.569) (xy 93.269 56.589)
(xy 93.011 56.589) (xy 93.011 56.569) (xy 92.06525 56.569) (xy 91.907 56.72725) (xy 91.907 57.015912)
(xy 91.956328 57.135) (xy 80.062 57.135) (xy 79.784555 57.190187) (xy 79.784553 57.190188) (xy 79.784554 57.190188)
(xy 79.549347 57.347348) (xy 78.439696 58.457) (xy 72.690304 58.457) (xy 70.097392 55.864088) (xy 91.907 55.864088)
(xy 91.907 56.15275) (xy 92.06525 56.311) (xy 93.011 56.311) (xy 93.011 55.51525) (xy 92.85275 55.357)
(xy 92.414089 55.357) (xy 92.181435 55.453368) (xy 92.003369 55.631434) (xy 91.907 55.864088) (xy 70.097392 55.864088)
(xy 69.855672 55.622368) (xy 69.753216 55.519733) (xy 69.486844 55.409126) (xy 69.198421 55.408874) (xy 68.931857 55.519016)
(xy 68.727733 55.722784) (xy 68.617126 55.989156) (xy 68.616874 56.277579) (xy 52.806538 56.277579) (xy 52.894874 56.064844)
(xy 52.895126 55.776421) (xy 52.784984 55.509857) (xy 52.581216 55.305733) (xy 52.339068 55.205184) (xy 48.891942 51.758058)
(xy 48.689177 51.622575) (xy 48.45 51.575) (xy 42.898223 51.575) (xy 42.442386 51.119162) (xy 42.695536 50.866453)
(xy 42.800035 50.61479) (xy 42.903302 50.864715) (xy 43.233547 51.195536) (xy 43.665253 51.374796) (xy 44.132697 51.375204)
(xy 44.564715 51.196698) (xy 44.895536 50.866453) (xy 45.074796 50.434747) (xy 45.075066 50.125) (xy 45.925065 50.125)
(xy 45.924796 50.432697) (xy 46.103302 50.864715) (xy 46.433547 51.195536) (xy 46.865253 51.374796) (xy 47.332697 51.375204)
(xy 47.764715 51.196698) (xy 48.095536 50.866453) (xy 48.274796 50.434747) (xy 48.275066 50.125) (xy 48.911116 50.125)
(xy 52.865562 54.079446) (xy 52.965016 54.320143) (xy 53.168784 54.524267) (xy 53.435156 54.634874) (xy 53.723579 54.635126)
(xy 53.990143 54.524984) (xy 54.194267 54.321216) (xy 54.304874 54.054844) (xy 54.305126 53.766421) (xy 54.194984 53.499857)
(xy 54.13 53.434759) (xy 54.13 53.107467) (xy 54.26 53.133326) (xy 55.16 53.133326) (xy 55.325827 53.100341)
(xy 55.466408 53.006408) (xy 55.560341 52.865827) (xy 55.593326 52.7) (xy 55.593326 51.5) (xy 55.560341 51.334173)
(xy 55.466408 51.193592) (xy 55.341355 51.110035) (xy 55.518566 51.036631) (xy 55.696632 50.858565) (xy 55.793 50.625911)
(xy 55.793 50.261798) (xy 105.955224 50.261798) (xy 105.981657 50.87109) (xy 106.163969 51.31123) (xy 106.419649 51.397917)
(xy 107.317566 50.5) (xy 107.682434 50.5) (xy 108.580351 51.397917) (xy 108.75 51.340398) (xy 108.919649 51.397917)
(xy 109.817566 50.5) (xy 108.919649 49.602083) (xy 108.75 49.659602) (xy 108.580351 49.602083) (xy 107.682434 50.5)
(xy 107.317566 50.5) (xy 106.419649 49.602083) (xy 106.163969 49.68877) (xy 105.955224 50.261798) (xy 55.793 50.261798)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 55.793 50.18725) (xy 55.63475 50.029) (xy 54.839 50.029) (xy 54.839 50.049) (xy 54.581 50.049)
(xy 54.581 50.029) (xy 53.78525 50.029) (xy 53.627 50.18725) (xy 53.627 50.625911) (xy 53.723368 50.858565)
(xy 53.901434 51.036631) (xy 54.078645 51.110035) (xy 53.953592 51.193592) (xy 53.859659 51.334173) (xy 53.826674 51.5)
(xy 53.826674 51.586465) (xy 53.799524 51.591866) (xy 53.621091 51.711091) (xy 53.191091 52.141091) (xy 53.071866 52.319524)
(xy 53.03894 52.485056) (xy 50.678884 50.125) (xy 52 50.125) (xy 52.047835 50.115485) (xy 52.088388 50.088388)
(xy 52.115485 50.047835) (xy 52.125 50) (xy 52.125 49.174089) (xy 53.627 49.174089) (xy 53.627 49.61275)
(xy 53.78525 49.771) (xy 54.581 49.771) (xy 54.581 48.82525) (xy 54.839 48.82525) (xy 54.839 49.771)
(xy 55.63475 49.771) (xy 55.793 49.61275) (xy 55.793 49.174089) (xy 55.696632 48.941435) (xy 55.542447 48.78725)
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(xy 96.167 48.78725) (xy 96.167 49.075912) (xy 96.263369 49.308566) (xy 96.441435 49.486632) (xy 96.674089 49.583)
(xy 97.11275 49.583) (xy 97.271 49.42475) (xy 97.271 48.629) (xy 96.32525 48.629) (xy 96.167 48.78725)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 55.542447 48.78725) (xy 55.518566 48.763369) (xy 55.285912 48.667) (xy 54.99725 48.667) (xy 54.839 48.82525)
(xy 54.581 48.82525) (xy 54.42275 48.667) (xy 54.134088 48.667) (xy 53.901434 48.763369) (xy 53.723368 48.941435)
(xy 53.627 49.174089) (xy 52.125 49.174089) (xy 52.125 47.924088) (xy 96.167 47.924088) (xy 96.167 48.21275)
(xy 96.32525 48.371) (xy 97.271 48.371) (xy 97.271 47.57525) (xy 97.529 47.57525) (xy 97.529 48.371)
(xy 97.549 48.371) (xy 97.549 48.629) (xy 97.529 48.629) (xy 97.529 49.42475) (xy 97.68725 49.583)
(xy 98.125911 49.583) (xy 98.358565 49.486632) (xy 98.536631 49.308566) (xy 98.610035 49.131355) (xy 98.693592 49.256408)
(xy 98.834173 49.350341) (xy 99 49.383326) (xy 100.2 49.383326) (xy 100.365827 49.350341) (xy 100.506408 49.256408)
(xy 100.600341 49.115827) (xy 100.633326 48.95) (xy 100.633326 48.05) (xy 100.600341 47.884173) (xy 100.506408 47.743592)
(xy 100.365827 47.649659) (xy 100.225 47.621647) (xy 100.225 47.05024) (xy 100.364267 46.911216) (xy 100.474874 46.644844)
(xy 100.475126 46.356421) (xy 100.364984 46.089857) (xy 100.161216 45.885733) (xy 99.894844 45.775126) (xy 99.606421 45.774874)
(xy 99.339857 45.885016) (xy 99.135733 46.088784) (xy 99.025126 46.355156) (xy 99.025081 46.407073) (xy 99.022575 46.410823)
(xy 98.975 46.65) (xy 98.975 47.621647) (xy 98.834173 47.649659) (xy 98.693592 47.743592) (xy 98.610035 47.868645)
(xy 98.536631 47.691434) (xy 98.358565 47.513368) (xy 98.125911 47.417) (xy 97.68725 47.417) (xy 97.529 47.57525)
(xy 97.271 47.57525) (xy 97.11275 47.417) (xy 96.674089 47.417) (xy 96.441435 47.513368) (xy 96.263369 47.691434)
(xy 96.167 47.924088) (xy 52.125 47.924088) (xy 52.125 47.625) (xy 61.5 47.625) (xy 61.547835 47.615485)
(xy 61.588388 47.588388) (xy 61.615485 47.547835) (xy 61.625 47.5) (xy 61.625 45.46725) (xy 78.702 45.46725)
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(xy 78.702 45.905911) (xy 78.798368 46.138565) (xy 78.976434 46.316631) (xy 79.209088 46.413) (xy 79.42275 46.413)
(xy 79.581 46.25475) (xy 79.581 45.309) (xy 79.839 45.309) (xy 79.839 46.25475) (xy 79.99725 46.413)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 80.210912 46.413) (xy 80.443566 46.316631) (xy 80.621632 46.138565) (xy 80.718 45.905911) (xy 80.718 45.899175)
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(xy 95.283258 45.899175) (xy 95.339209 46.12897) (xy 95.821547 46.295905) (xy 96.331052 46.265551) (xy 96.660791 46.12897)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 96.716742 45.899175) (xy 96 45.182434) (xy 95.283258 45.899175) (xy 80.718 45.899175) (xy 80.718 45.46725)
(xy 80.55975 45.309) (xy 79.839 45.309) (xy 79.581 45.309) (xy 78.86025 45.309) (xy 78.702 45.46725)
(xy 61.625 45.46725) (xy 61.625 43.78725) (xy 70.217 43.78725) (xy 70.217 44.275911) (xy 70.313368 44.508565)
(xy 70.491434 44.686631) (xy 70.724088 44.783) (xy 71.21275 44.783) (xy 71.371 44.62475) (xy 71.371 43.629)
(xy 71.629 43.629) (xy 71.629 44.62475) (xy 71.78725 44.783) (xy 72.275912 44.783) (xy 72.508566 44.686631)
(xy 72.686632 44.508565) (xy 72.783 44.275911) (xy 72.783 43.78725) (xy 72.62475 43.629) (xy 71.629 43.629)
(xy 71.371 43.629) (xy 70.37525 43.629) (xy 70.217 43.78725) (xy 61.625 43.78725) (xy 61.625 42.724089)
(xy 70.217 42.724089) (xy 70.217 43.21275) (xy 70.37525 43.371) (xy 71.371 43.371) (xy 71.371 42.37525)
(xy 71.21275 42.217) (xy 70.724088 42.217) (xy 70.491434 42.313369) (xy 70.313368 42.491435) (xy 70.217 42.724089)
(xy 61.625 42.724089) (xy 61.625 41.212893) (xy 70.424814 41.212893) (xy 70.588128 41.608143) (xy 70.890267 41.910809)
(xy 71.285231 42.074813) (xy 71.691283 42.075167) (xy 71.833116 42.217) (xy 71.78725 42.217) (xy 71.629 42.37525)
(xy 71.629 43.371) (xy 72.62475 43.371) (xy 72.783 43.21275) (xy 72.783 42.724089) (xy 72.686632 42.491435)
(xy 72.650197 42.455) (xy 74.800253 42.455) (xy 74.885016 42.660143) (xy 75.088784 42.864267) (xy 75.355156 42.974874)
(xy 75.643579 42.975126) (xy 75.910143 42.864984) (xy 76.114267 42.661216) (xy 76.199895 42.455) (xy 78.974197 42.455)
(xy 78.934659 42.514173) (xy 78.901674 42.68) (xy 78.901674 43.88) (xy 78.934659 44.045827) (xy 78.950407 44.069396)
(xy 78.798368 44.221435) (xy 78.702 44.454089) (xy 78.702 44.89275) (xy 78.86025 45.051) (xy 79.581 45.051)
(xy 79.581 45.031) (xy 79.839 45.031) (xy 79.839 45.051) (xy 80.55975 45.051) (xy 80.718 44.89275)
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(xy 80.718 44.454089) (xy 80.621632 44.221435) (xy 80.469593 44.069396) (xy 80.480292 44.053383) (xy 81.224857 44.053383)
(xy 81.350191 44.356715) (xy 81.582065 44.588993) (xy 81.885177 44.714857) (xy 82.213383 44.715143) (xy 82.516715 44.589809)
(xy 82.748993 44.357935) (xy 82.84956 44.115744) (xy 83.210675 43.75463) (xy 83.091529 44.041563) (xy 83.091243 44.369769)
(xy 83.216577 44.673101) (xy 83.448451 44.905379) (xy 83.751563 45.031243) (xy 84.079769 45.031529) (xy 84.343044 44.922746)
(xy 84.459173 45.000341) (xy 84.625 45.033326) (xy 85.375 45.033326) (xy 85.540827 45.000341) (xy 85.681408 44.906408)
(xy 85.731536 44.831386) (xy 85.836873 44.831386) (xy 85.90394 44.876199) (xy 85.949971 44.885355) (xy 86.181386 44.931386)
(xy 94.173614 44.931386) (xy 94.405029 44.885355) (xy 94.45106 44.876199) (xy 94.686266 44.719038) (xy 94.767787 44.637517)
(xy 94.704095 44.821547) (xy 94.734449 45.331052) (xy 94.87103 45.660791) (xy 95.100825 45.716742) (xy 95.817566 45)
(xy 96.182434 45) (xy 96.899175 45.716742) (xy 97.12897 45.660791) (xy 97.295905 45.178453) (xy 97.265551 44.668948)
(xy 97.12897 44.339209) (xy 96.899175 44.283258) (xy 96.182434 45) (xy 95.817566 45) (xy 95.803424 44.985858)
(xy 95.985858 44.803424) (xy 96 44.817566) (xy 96.716742 44.100825) (xy 96.660791 43.87103) (xy 96.178453 43.704095)
(xy 95.670976 43.734328) (xy 95.821979 43.583326) (xy 96.65 43.583326) (xy 96.815827 43.550341) (xy 96.956408 43.456408)
(xy 97.050341 43.315827) (xy 97.083326 43.15) (xy 97.083326 41.85) (xy 97.050341 41.684173) (xy 96.956408 41.543592)
(xy 96.876202 41.49) (xy 101.275 41.49) (xy 101.275 44.99) (xy 101.284409 45.037579) (xy 101.311415 45.078192)
(xy 101.351908 45.105378) (xy 101.399722 45.115) (xy 105.899722 45.125) (xy 105.947835 45.115485) (xy 105.988388 45.088388)
(xy 106.015485 45.047835) (xy 106.025 45) (xy 106.025 41.5) (xy 106.015591 41.452421) (xy 105.988585 41.411808)
(xy 105.948092 41.384622) (xy 105.900278 41.375) (xy 101.400278 41.365) (xy 101.352165 41.374515) (xy 101.311612 41.401612)
(xy 101.284515 41.442165) (xy 101.275 41.49) (xy 96.876202 41.49) (xy 96.815827 41.449659) (xy 96.65 41.416674)
(xy 95.35 41.416674) (xy 95.184173 41.449659) (xy 95.043592 41.543592) (xy 94.949659 41.684173) (xy 94.916674 41.85)
(xy 94.916674 42.438021) (xy 94.743184 42.611511) (xy 94.824857 42.414823) (xy 94.825143 42.086617) (xy 94.699809 41.783285)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 94.467935 41.551007) (xy 94.394324 41.520441) (xy 93.894274 41.02039) (xy 105.742043 41.02039) (xy 105.811784 41.261771)
(xy 106.334768 41.447445) (xy 106.888996 41.418849) (xy 107.268216 41.261771) (xy 107.337957 41.02039) (xy 106.54 40.222434)
(xy 105.742043 41.02039) (xy 93.894274 41.02039) (xy 92.708652 39.834768) (xy 105.132555 39.834768) (xy 105.161151 40.388996)
(xy 105.318229 40.768216) (xy 105.55961 40.837957) (xy 106.357566 40.04) (xy 106.722434 40.04) (xy 107.52039 40.837957)
(xy 107.761771 40.768216) (xy 107.947445 40.245232) (xy 107.918849 39.691004) (xy 107.761771 39.311784) (xy 107.52039 39.242043)
(xy 106.722434 40.04) (xy 106.357566 40.04) (xy 105.55961 39.242043) (xy 105.318229 39.311784) (xy 105.132555 39.834768)
(xy 92.708652 39.834768) (xy 91.933494 39.05961) (xy 105.742043 39.05961) (xy 106.54 39.857566) (xy 107.337957 39.05961)
(xy 107.268216 38.818229) (xy 106.745232 38.632555) (xy 106.191004 38.661151) (xy 105.811784 38.818229) (xy 105.742043 39.05961)
(xy 91.933494 39.05961) (xy 91.743326 38.869442) (xy 91.743326 38.12) (xy 91.710341 37.954173) (xy 91.616408 37.813592)
(xy 91.498896 37.735073) (xy 102.812794 37.735073) (xy 102.993123 38.171503) (xy 103.32674 38.505703) (xy 103.762855 38.686794)
(xy 104.235073 38.687206) (xy 104.671503 38.506877) (xy 105.005703 38.17326) (xy 105.186794 37.737145) (xy 105.187206 37.264927)
(xy 105.006877 36.828497) (xy 104.67326 36.494297) (xy 104.237145 36.313206) (xy 103.764927 36.312794) (xy 103.328497 36.493123)
(xy 102.994297 36.82674) (xy 102.813206 37.262855) (xy 102.812794 37.735073) (xy 91.498896 37.735073) (xy 91.475827 37.719659)
(xy 91.31 37.686674) (xy 90.41 37.686674) (xy 90.244173 37.719659) (xy 90.103592 37.813592) (xy 90.009659 37.954173)
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(xy 89.976674 38.12) (xy 89.976674 39.32) (xy 90.009659 39.485827) (xy 90.103592 39.626408) (xy 90.244173 39.720341)
(xy 90.41 39.753326) (xy 90.859442 39.753326) (xy 93.179882 42.073765) (xy 93.175143 42.085177) (xy 93.174857 42.413383)
(xy 93.300191 42.716715) (xy 93.532065 42.948993) (xy 93.835177 43.074857) (xy 94.163383 43.075143) (xy 94.361351 42.993344)
(xy 93.87331 43.481386) (xy 86.478729 43.481386) (xy 86.252446 43.330187) (xy 86.180252 43.315827) (xy 85.975 43.275)
(xy 85.783462 43.275) (xy 85.775341 43.234173) (xy 85.759593 43.210604) (xy 85.911632 43.058565) (xy 86.008 42.825911)
(xy 86.008 42.38725) (xy 85.84975 42.229) (xy 85.129 42.229) (xy 85.129 42.249) (xy 84.871 42.249)
(xy 84.871 42.229) (xy 84.851 42.229) (xy 84.851 41.971) (xy 84.871 41.971) (xy 84.871 41.02525)
(xy 85.129 41.02525) (xy 85.129 41.971) (xy 85.84975 41.971) (xy 86.008 41.81275) (xy 86.008 41.374089)
(xy 85.911632 41.141435) (xy 85.733566 40.963369) (xy 85.500912 40.867) (xy 85.28725 40.867) (xy 85.129 41.02525)
(xy 84.871 41.02525) (xy 84.71275 40.867) (xy 84.575 40.867) (xy 84.575 37.75) (xy 84.512201 37.434286)
(xy 84.333363 37.166637) (xy 84.065714 36.987799) (xy 83.75 36.925) (xy 83.434286 36.987799) (xy 83.166637 37.166637)
(xy 82.987799 37.434286) (xy 82.925 37.75) (xy 82.925 41.368274) (xy 82.337146 41.956128) (xy 82.221007 42.072065)
(xy 82.095143 42.375177) (xy 82.094857 42.703383) (xy 82.128906 42.785789) (xy 81.823942 43.090754) (xy 81.583285 43.190191)
(xy 81.351007 43.422065) (xy 81.225143 43.725177) (xy 81.224857 44.053383) (xy 80.480292 44.053383) (xy 80.485341 44.045827)
(xy 80.518326 43.88) (xy 80.518326 43.130558) (xy 81.104884 42.543999) (xy 81.155156 42.564874) (xy 81.443579 42.565126)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 81.710143 42.454984) (xy 81.914267 42.251216) (xy 82.024874 41.984844) (xy 82.025126 41.696421) (xy 81.914984 41.429857)
(xy 81.711216 41.225733) (xy 81.444844 41.115126) (xy 81.156421 41.114874) (xy 80.938299 41.205) (xy 80.935005 41.205)
(xy 80.935 41.204999) (xy 80.934995 41.205) (xy 72.588884 41.205) (xy 72.574834 41.19095) (xy 72.575186 40.787107)
(xy 72.411872 40.391857) (xy 72.109733 40.089191) (xy 71.714769 39.925187) (xy 71.287107 39.924814) (xy 70.891857 40.088128)
(xy 70.589191 40.390267) (xy 70.425187 40.785231) (xy 70.424814 41.212893) (xy 61.625 41.212893) (xy 61.625 39.5)
(xy 61.615485 39.452165) (xy 61.588388 39.411612) (xy 61.547835 39.384515) (xy 61.5 39.375) (xy 61.125 39.375)
(xy 61.125 37.613173) (xy 63.49443 37.613173) (xy 63.49443 38.166827) (xy 63.583915 38.616698) (xy 63.838746 38.998081)
(xy 64.220129 39.252912) (xy 64.67 39.342397) (xy 65.119871 39.252912) (xy 65.501254 38.998081) (xy 65.756085 38.616698)
(xy 65.84557 38.166827) (xy 65.84557 37.613173) (xy 65.756085 37.163302) (xy 65.501254 36.781919) (xy 65.119871 36.527088)
(xy 64.67 36.437603) (xy 64.220129 36.527088) (xy 63.838746 36.781919) (xy 63.583915 37.163302) (xy 63.49443 37.613173)
(xy 61.125 37.613173) (xy 61.125 36.25013) (xy 61.403302 36.436085) (xy 61.853173 36.52557) (xy 62.406827 36.52557)
(xy 62.856698 36.436085) (xy 63.238081 36.181254) (xy 63.492912 35.799871) (xy 63.582397 35.35) (xy 63.492912 34.900129)
(xy 63.291993 34.59943) (xy 65.777184 34.59943) (xy 65.777184 36.10057) (xy 65.810169 36.266397) (xy 65.904102 36.406978)
(xy 66.044683 36.500911) (xy 66.21051 36.533896) (xy 68.20949 36.533896) (xy 68.375317 36.500911) (xy 68.515898 36.406978)
(xy 68.609831 36.266397) (xy 68.642816 36.10057) (xy 68.642816 34.712893) (xy 77.424814 34.712893) (xy 77.588128 35.108143)
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(xy 77.890267 35.410809) (xy 78.285231 35.574813) (xy 78.712893 35.575186) (xy 79.108143 35.411872) (xy 79.410809 35.109733)
(xy 79.574813 34.714769) (xy 79.574822 34.703383) (xy 87.264857 34.703383) (xy 87.390191 35.006715) (xy 87.622065 35.238993)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 87.925177 35.364857) (xy 88.031065 35.364949) (xy 89.628058 36.961942) (xy 89.830823 37.097425) (xy 89.978007 37.126702)
(xy 90.009659 37.285827) (xy 90.103592 37.426408) (xy 90.244173 37.520341) (xy 90.41 37.553326) (xy 91.31 37.553326)
(xy 91.475827 37.520341) (xy 91.616408 37.426408) (xy 91.710341 37.285827) (xy 91.743326 37.12) (xy 91.743326 35.92)
(xy 91.710341 35.754173) (xy 91.616408 35.613592) (xy 91.475827 35.519659) (xy 91.31 35.486674) (xy 90.41 35.486674)
(xy 90.244173 35.519659) (xy 90.103592 35.613592) (xy 90.081115 35.647231) (xy 88.915052 34.481168) (xy 88.915143 34.376617)
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(xy 88.789809 34.073285) (xy 88.557935 33.841007) (xy 88.254823 33.715143) (xy 87.926617 33.714857) (xy 87.623285 33.840191)
(xy 87.391007 34.072065) (xy 87.265143 34.375177) (xy 87.264857 34.703383) (xy 79.574822 34.703383) (xy 79.575186 34.287107)
(xy 79.411872 33.891857) (xy 79.109733 33.589191) (xy 78.714769 33.425187) (xy 78.287107 33.424814) (xy 77.891857 33.588128)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 77.589191 33.890267) (xy 77.425187 34.285231) (xy 77.424814 34.712893) (xy 68.642816 34.712893) (xy 68.642816 34.59943)
(xy 68.609831 34.433603) (xy 68.515898 34.293022) (xy 68.375317 34.199089) (xy 68.20949 34.166104) (xy 66.21051 34.166104)
(xy 66.044683 34.199089) (xy 65.904102 34.293022) (xy 65.810169 34.433603) (xy 65.777184 34.59943) (xy 63.291993 34.59943)
(xy 63.238081 34.518746) (xy 62.856698 34.263915) (xy 62.406827 34.17443) (xy 61.853173 34.17443) (xy 61.403302 34.263915)
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(xy 61.125 34.44987) (xy 61.125 33.031716) (xy 96.12471 33.031716) (xy 96.379176 33.647572) (xy 96.84995 34.119168)
(xy 97.46536 34.374708) (xy 98.131716 34.37529) (xy 98.747572 34.120824) (xy 99.219168 33.65005) (xy 99.474708 33.03464)
(xy 99.47471 33.031716) (xy 102.47471 33.031716) (xy 102.729176 33.647572) (xy 103.19995 34.119168) (xy 103.81536 34.374708)
(xy 104.481716 34.37529) (xy 105.097572 34.120824) (xy 105.569168 33.65005) (xy 105.824708 33.03464) (xy 105.82529 32.368284)
(xy 105.570824 31.752428) (xy 105.10005 31.280832) (xy 104.48464 31.025292) (xy 103.818284 31.02471) (xy 103.202428 31.279176)
(xy 102.730832 31.74995) (xy 102.475292 32.36536) (xy 102.47471 33.031716) (xy 99.47471 33.031716) (xy 99.47529 32.368284)
(xy 99.220824 31.752428) (xy 98.75005 31.280832) (xy 98.13464 31.025292) (xy 97.468284 31.02471) (xy 96.852428 31.279176)
(xy 96.380832 31.74995) (xy 96.125292 32.36536) (xy 96.12471 33.031716) (xy 61.125 33.031716) (xy 61.125 29.25)
(xy 61.115485 29.202165) (xy 61.088388 29.161612) (xy 61.047835 29.134515) (xy 61 29.125) (xy 53.125 29.125)
(xy 53.125 27.75) (xy 63.125 27.75) (xy 63.125 32) (xy 63.134515 32.047835) (xy 63.161612 32.088388)
(xy 63.202165 32.115485) (xy 63.25 32.125) (xy 65.75 32.125) (xy 65.797835 32.115485) (xy 65.838388 32.088388)
(xy 65.865485 32.047835) (xy 65.875 32) (xy 65.875 31.28725) (xy 77.217 31.28725) (xy 77.217 31.775911)
(xy 77.313368 32.008565) (xy 77.491434 32.186631) (xy 77.724088 32.283) (xy 78.21275 32.283) (xy 78.371 32.12475)
(xy 78.371 31.129) (xy 78.629 31.129) (xy 78.629 32.12475) (xy 78.78725 32.283) (xy 79.275912 32.283)
(xy 79.508566 32.186631) (xy 79.686632 32.008565) (xy 79.783 31.775911) (xy 79.783 31.28725) (xy 79.62475 31.129)
(xy 78.629 31.129) (xy 78.371 31.129) (xy 77.37525 31.129) (xy 77.217 31.28725) (xy 65.875 31.28725)
(xy 65.875 30.224089) (xy 77.217 30.224089) (xy 77.217 30.71275) (xy 77.37525 30.871) (xy 78.371 30.871)
(xy 78.371 29.87525) (xy 78.629 29.87525) (xy 78.629 30.871) (xy 79.62475 30.871) (xy 79.783 30.71275)
(xy 79.783 30.224089) (xy 79.686632 29.991435) (xy 79.508566 29.813369) (xy 79.275912 29.717) (xy 78.78725 29.717)
(xy 78.629 29.87525) (xy 78.371 29.87525) (xy 78.21275 29.717) (xy 77.724088 29.717) (xy 77.491434 29.813369)
(xy 77.313368 29.991435) (xy 77.217 30.224089) (xy 65.875 30.224089) (xy 65.875 27.75) (xy 65.865485 27.702165)
(xy 65.838388 27.661612) (xy 65.797835 27.634515) (xy 65.75 27.625) (xy 63.25 27.625) (xy 63.202165 27.634515)
(xy 63.161612 27.661612) (xy 63.134515 27.702165) (xy 63.125 27.75) (xy 53.125 27.75) (xy 53.125 24.741547)
(xy 63.064095 24.741547) (xy 63.094449 25.251052) (xy 63.125 25.324809) (xy 63.125 26.055494) (xy 63.134515 26.103329)
(xy 63.161612 26.143882) (xy 63.202165 26.170979) (xy 63.25 26.180494) (xy 64.079231 26.180494) (xy 64.181547 26.215905)
(xy 64.691052 26.185551) (xy 64.703261 26.180494) (xy 65.5 26.180494) (xy 65.547835 26.170979) (xy 65.588388 26.143882)
(xy 65.615485 26.103329) (xy 65.625 26.055494) (xy 65.625 25.187749) (xy 65.655905 25.098453) (xy 65.625551 24.588948)
(xy 65.625 24.587618) (xy 65.625 23.74943) (xy 68.737184 23.74943) (xy 68.737184 25.25057) (xy 68.770169 25.416397)
(xy 68.864102 25.556978) (xy 69.004683 25.650911) (xy 69.17051 25.683896) (xy 71.16949 25.683896) (xy 71.335317 25.650911)
(xy 71.475898 25.556978) (xy 71.569831 25.416397) (xy 71.602816 25.25057) (xy 71.602816 24.5) (xy 73.797603 24.5)
(xy 73.887088 24.949871) (xy 74.141919 25.331254) (xy 74.523302 25.586085) (xy 74.973173 25.67557) (xy 75.526827 25.67557)
(xy 75.976698 25.586085) (xy 76.358081 25.331254) (xy 76.612912 24.949871) (xy 76.652668 24.75) (xy 81.625 24.75)
(xy 81.625 27.25) (xy 81.634515 27.297835) (xy 81.661612 27.338388) (xy 81.702165 27.365485) (xy 81.75 27.375)
(xy 84.25 27.375) (xy 84.297835 27.365485) (xy 84.338388 27.338388) (xy 84.365485 27.297835) (xy 84.375 27.25)
(xy 84.375 24.75) (xy 84.365485 24.702165) (xy 84.338388 24.661612) (xy 84.297835 24.634515) (xy 84.25 24.625)
(xy 81.75 24.625) (xy 81.702165 24.634515) (xy 81.661612 24.661612) (xy 81.634515 24.702165) (xy 81.625 24.75)
(xy 76.652668 24.75) (xy 76.702397 24.5) (xy 76.612912 24.050129) (xy 76.358081 23.668746) (xy 75.976698 23.413915)
(xy 75.526827 23.32443) (xy 74.973173 23.32443) (xy 74.523302 23.413915) (xy 74.141919 23.668746) (xy 73.887088 24.050129)
(xy 73.797603 24.5) (xy 71.602816 24.5) (xy 71.602816 23.74943) (xy 71.569831 23.583603) (xy 71.475898 23.443022)
(xy 71.335317 23.349089) (xy 71.16949 23.316104) (xy 69.17051 23.316104) (xy 69.004683 23.349089) (xy 68.864102 23.443022)
(xy 68.770169 23.583603) (xy 68.737184 23.74943) (xy 65.625 23.74943) (xy 65.625 21.75) (xy 65.615485 21.702165)
(xy 65.602795 21.683173) (xy 71.53443 21.683173) (xy 71.53443 22.236827) (xy 71.623915 22.686698) (xy 71.878746 23.068081)
(xy 72.260129 23.322912) (xy 72.71 23.412397) (xy 73.159871 23.322912) (xy 73.541254 23.068081) (xy 73.796085 22.686698)
(xy 73.88557 22.236827) (xy 73.88557 21.85) (xy 81.916674 21.85) (xy 81.916674 23.15) (xy 81.949659 23.315827)
(xy 82.043592 23.456408) (xy 82.184173 23.550341) (xy 82.35 23.583326) (xy 83.65 23.583326) (xy 83.815827 23.550341)
(xy 83.956408 23.456408) (xy 84.050341 23.315827) (xy 84.083326 23.15) (xy 84.083326 21.85) (xy 84.050341 21.684173)
(xy 84.015291 21.631716) (xy 96.12471 21.631716) (xy 96.379176 22.247572) (xy 96.84995 22.719168) (xy 97.46536 22.974708)
(xy 98.131716 22.97529) (xy 98.747572 22.720824) (xy 99.219168 22.25005) (xy 99.474708 21.63464) (xy 99.47471 21.631716)
(xy 102.47471 21.631716) (xy 102.729176 22.247572) (xy 103.19995 22.719168) (xy 103.81536 22.974708) (xy 104.481716 22.97529)
(xy 105.097572 22.720824) (xy 105.185008 22.63354) (xy 109.348894 22.63354) (xy 109.478431 22.925537) (xy 110.178259 23.192738)
(xy 110.92707 23.171787) (xy 111.521569 22.925537) (xy 111.651106 22.63354) (xy 110.5 21.482434) (xy 109.348894 22.63354)
(xy 105.185008 22.63354) (xy 105.569168 22.25005) (xy 105.824708 21.63464) (xy 105.825281 20.978259) (xy 108.607262 20.978259)
(xy 108.628213 21.72707) (xy 108.874463 22.321569) (xy 109.16646 22.451106) (xy 110.317566 21.3) (xy 109.16646 20.148894)
(xy 108.874463 20.278431) (xy 108.607262 20.978259) (xy 105.825281 20.978259) (xy 105.82529 20.968284) (xy 105.570824 20.352428)
(xy 105.185529 19.96646) (xy 109.348894 19.96646) (xy 110.5 21.117566) (xy 111.651106 19.96646) (xy 111.521569 19.674463)
(xy 110.821741 19.407262) (xy 110.07293 19.428213) (xy 109.478431 19.674463) (xy 109.348894 19.96646) (xy 105.185529 19.96646)
(xy 105.10005 19.880832) (xy 104.48464 19.625292) (xy 103.818284 19.62471) (xy 103.202428 19.879176) (xy 102.730832 20.34995)
(xy 102.475292 20.96536) (xy 102.47471 21.631716) (xy 99.47471 21.631716) (xy 99.47529 20.968284) (xy 99.220824 20.352428)
(xy 98.75005 19.880832) (xy 98.13464 19.625292) (xy 97.468284 19.62471) (xy 96.852428 19.879176) (xy 96.380832 20.34995)
(xy 96.125292 20.96536) (xy 96.12471 21.631716) (xy 84.015291 21.631716) (xy 83.956408 21.543592) (xy 83.815827 21.449659)
(xy 83.65 21.416674) (xy 82.35 21.416674) (xy 82.184173 21.449659) (xy 82.043592 21.543592) (xy 81.949659 21.684173)
(xy 81.916674 21.85) (xy 73.88557 21.85) (xy 73.88557 21.683173) (xy 73.796085 21.233302) (xy 73.541254 20.851919)
(xy 73.159871 20.597088) (xy 72.71 20.507603) (xy 72.260129 20.597088) (xy 71.878746 20.851919) (xy 71.623915 21.233302)
(xy 71.53443 21.683173) (xy 65.602795 21.683173) (xy 65.588388 21.661612) (xy 65.547835 21.634515) (xy 65.5 21.625)
(xy 63.25 21.625) (xy 63.202165 21.634515) (xy 63.161612 21.661612) (xy 63.134515 21.702165) (xy 63.125 21.75)
(xy 63.125 24.56557) (xy 63.064095 24.741547) (xy 53.125 24.741547) (xy 53.125 16.125) (xy 111.875 16.125)
)
)
(filled_polygon
(pts
(xy 83.992 42.825911) (xy 84.088368 43.058565) (xy 84.240407 43.210604) (xy 84.224659 43.234173) (xy 84.196647 43.375)
(xy 84.122772 43.375) (xy 84.084039 43.382704) (xy 84.081209 43.381529) (xy 83.753003 43.381243) (xy 83.45023 43.506346)
(xy 83.589813 43.297446) (xy 83.645 43.02) (xy 83.645 42.981726) (xy 83.992 42.634726)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
(filled_polygon
(pts
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 60.125 30.051776) (xy 60.125 39.198224) (xy 59.948224 39.375) (xy 53.125 39.375) (xy 53.125 36.952795)
(xy 53.374805 36.952795) (xy 53.545715 37.366429) (xy 53.861907 37.683172) (xy 54.275242 37.854804) (xy 54.722795 37.855195)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 54.735897 37.849781) (xy 54.778058 37.891942) (xy 54.980823 38.027425) (xy 55.195685 38.070164) (xy 55.224659 38.215827)
(xy 55.318592 38.356408) (xy 55.459173 38.450341) (xy 55.625 38.483326) (xy 56.375 38.483326) (xy 56.540827 38.450341)
(xy 56.681408 38.356408) (xy 56.775341 38.215827) (xy 56.808326 38.05) (xy 56.808326 36.85) (xy 56.775341 36.684173)
(xy 56.759593 36.660604) (xy 56.911632 36.508565) (xy 57.008 36.275911) (xy 57.008 35.83725) (xy 56.84975 35.679)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 56.129 35.679) (xy 56.129 35.699) (xy 55.871 35.699) (xy 55.871 35.679) (xy 55.15025 35.679)
(xy 55.077558 35.751692) (xy 54.724758 35.605196) (xy 54.277205 35.604805) (xy 53.863571 35.775715) (xy 53.546828 36.091907)
(xy 53.375196 36.505242) (xy 53.374805 36.952795) (xy 53.125 36.952795) (xy 53.125 33.999589) (xy 53.15429 33.999589)
(xy 53.183859 34.529064) (xy 53.329593 34.880898) (xy 53.564557 34.943009) (xy 54.317566 34.19) (xy 53.564557 33.436991)
(xy 53.329593 33.499102) (xy 53.15429 33.999589) (xy 53.125 33.999589) (xy 53.125 31.872795) (xy 53.374805 31.872795)
(xy 53.545715 32.286429) (xy 53.861907 32.603172) (xy 54.275242 32.774804) (xy 54.722795 32.775195) (xy 54.992858 32.663608)
(xy 55.150248 32.820998) (xy 54.992 32.820998) (xy 54.992 32.949926) (xy 54.690411 32.84429) (xy 54.160936 32.873859)
(xy 53.809102 33.019593) (xy 53.746991 33.254557) (xy 54.5 34.007566) (xy 54.514142 33.993424) (xy 54.696576 34.175858)
(xy 54.682434 34.19) (xy 54.696576 34.204142) (xy 54.514142 34.386576) (xy 54.5 34.372434) (xy 53.746991 35.125443)
(xy 53.809102 35.360407) (xy 54.309589 35.53571) (xy 54.839064 35.506141) (xy 55.11931 35.39006) (xy 55.15025 35.421)
(xy 55.871 35.421) (xy 55.871 34.47525) (xy 56.129 34.47525) (xy 56.129 35.421) (xy 56.84975 35.421)
(xy 57.008 35.26275) (xy 57.008 34.824089) (xy 56.911632 34.591435) (xy 56.733566 34.413369) (xy 56.500912 34.317)
(xy 56.28725 34.317) (xy 56.129 34.47525) (xy 55.871 34.47525) (xy 55.827669 34.431919) (xy 55.84571 34.380411)
(xy 55.828236 34.067514) (xy 55.871 34.02475) (xy 55.871 33.079) (xy 56.129 33.079) (xy 56.129 34.02475)
(xy 56.28725 34.183) (xy 56.500912 34.183) (xy 56.733566 34.086631) (xy 56.911632 33.908565) (xy 57.008 33.675911)
(xy 57.008 33.23725) (xy 56.84975 33.079) (xy 56.129 33.079) (xy 55.871 33.079) (xy 55.851 33.079)
(xy 55.851 32.821) (xy 55.871 32.821) (xy 55.871 32.801) (xy 56.129 32.801) (xy 56.129 32.821)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 56.84975 32.821) (xy 57.008 32.66275) (xy 57.008 32.224089) (xy 56.911632 31.991435) (xy 56.759593 31.839396)
(xy 56.775341 31.815827) (xy 56.808326 31.65) (xy 56.808326 30.45) (xy 56.775341 30.284173) (xy 56.681408 30.143592)
(xy 56.540827 30.049659) (xy 56.375 30.016674) (xy 55.625 30.016674) (xy 55.459173 30.049659) (xy 55.318592 30.143592)
(xy 55.224659 30.284173) (xy 55.196647 30.425) (xy 55.1 30.425) (xy 54.860822 30.472575) (xy 54.760104 30.539873)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 54.724758 30.525196) (xy 54.277205 30.524805) (xy 53.863571 30.695715) (xy 53.546828 31.011907) (xy 53.375196 31.425242)
(xy 53.374805 31.872795) (xy 53.125 31.872795) (xy 53.125 29.875) (xy 59.948224 29.875)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
)
)
)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(zone (net 31) (net_name GNDA) (layer B.Cu) (tstamp 0) (hatch edge 0.508)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(priority 1)
(connect_pads (clearance 0.3))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 14.5 43.75) (xy 14.5 53.25) (xy 26.5 53.25) (xy 26.5 44.5) (xy 23 44.5)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 23 44.25) (xy 23 43.75)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
)
)
(filled_polygon
(pts
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 16.199635 47.92) (xy 16.232775 48.086607) (xy 16.32715 48.22785) (xy 16.390232 48.27) (xy 16.32715 48.31215)
(xy 16.232775 48.453393) (xy 16.199635 48.62) (xy 16.199635 49.82) (xy 16.232775 49.986607) (xy 16.32715 50.12785)
(xy 16.468393 50.222225) (xy 16.635 50.255365) (xy 17.385 50.255365) (xy 17.551607 50.222225) (xy 17.69285 50.12785)
(xy 17.787225 49.986607) (xy 17.820365 49.82) (xy 17.820365 49.777) (xy 19.255006 49.777) (xy 19.282775 49.916607)
(xy 19.37715 50.05785) (xy 19.518393 50.152225) (xy 19.685 50.185365) (xy 20.435 50.185365) (xy 20.601607 50.152225)
(xy 20.74285 50.05785) (xy 20.815 49.949869) (xy 20.815 50.41425) (xy 20.97375 50.573) (xy 22.323 50.573)
(xy 22.323 50.553) (xy 22.577 50.553) (xy 22.577 50.573) (xy 23.92625 50.573) (xy 24.085 50.41425)
(xy 24.085 49.82369) (xy 24.06566 49.777) (xy 25.37 49.777) (xy 25.609943 49.729272) (xy 25.813356 49.593356)
(xy 26.312773 49.093939) (xy 26.373 49.069054) (xy 26.373 53.123) (xy 14.627 53.123) (xy 14.627 52.935365)
(xy 15.95 52.935365) (xy 16.116607 52.902225) (xy 16.25785 52.80785) (xy 16.352225 52.666607) (xy 16.385365 52.5)
(xy 16.385365 51.188534) (xy 17.497835 51.188534) (xy 17.642463 51.53856) (xy 17.910031 51.806596) (xy 18.259805 51.951835)
(xy 18.638534 51.952165) (xy 18.98856 51.807537) (xy 19.256596 51.539969) (xy 19.401835 51.190195) (xy 19.402013 50.98575)
(xy 20.815 50.98575) (xy 20.815 51.57631) (xy 20.911673 51.809699) (xy 21.090302 51.988327) (xy 21.323691 52.085)
(xy 22.16425 52.085) (xy 22.323 51.92625) (xy 22.323 50.827) (xy 22.577 50.827) (xy 22.577 51.92625)
(xy 22.73575 52.085) (xy 23.576309 52.085) (xy 23.809698 51.988327) (xy 23.988327 51.809699) (xy 24.085 51.57631)
(xy 24.085 50.98575) (xy 23.92625 50.827) (xy 22.577 50.827) (xy 22.323 50.827) (xy 20.97375 50.827)
(xy 20.815 50.98575) (xy 19.402013 50.98575) (xy 19.402165 50.811466) (xy 19.257537 50.46144) (xy 18.989969 50.193404)
(xy 18.640195 50.048165) (xy 18.261466 50.047835) (xy 17.91144 50.192463) (xy 17.643404 50.460031) (xy 17.498165 50.809805)
(xy 17.497835 51.188534) (xy 16.385365 51.188534) (xy 16.385365 50.5) (xy 16.352225 50.333393) (xy 16.25785 50.19215)
(xy 16.116607 50.097775) (xy 15.95 50.064635) (xy 14.627 50.064635) (xy 14.627 46.935365) (xy 15.95 46.935365)
(xy 16.116607 46.902225) (xy 16.199635 46.846748)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(zone (net 13) (net_name GNDPWR) (layer F.Cu) (tstamp 0) (hatch edge 0.508)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(priority 1)
(connect_pads (clearance 0.3))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 53 31.25) (xy 53 39.25) (xy 61.75 39.25) (xy 67.25 39.25) (xy 67.25 37.25)
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(xy 84 37.25) (xy 84 33) (xy 84.75 33) (xy 84.75 17.75) (xy 67.75 17.75)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 65.25 17.75) (xy 64.5 18.5) (xy 53 30)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
(filled_polygon
(pts
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 84.623 21.707412) (xy 84.45 21.673) (xy 84.045281 21.673) (xy 83.95785 21.54215) (xy 83.816607 21.447775)
(xy 83.65 21.414635) (xy 82.35 21.414635) (xy 82.183393 21.447775) (xy 82.04215 21.54215) (xy 81.954719 21.673)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 81.55 21.673) (xy 81.233521 21.735952) (xy 80.965223 21.915223) (xy 79.207446 23.673) (xy 78.327 23.673)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 78.327 21.95) (xy 78.310365 21.866371) (xy 78.310365 21.35) (xy 78.277225 21.183393) (xy 78.262168 21.160858)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 78.413327 21.009698) (xy 78.51 20.776309) (xy 78.51 20.33575) (xy 78.35125 20.177) (xy 77.627 20.177)
(xy 77.627 20.197) (xy 77.373 20.197) (xy 77.373 20.177) (xy 76.64875 20.177) (xy 76.49 20.33575)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 76.49 20.776309) (xy 76.586673 21.009698) (xy 76.737832 21.160858) (xy 76.722775 21.183393) (xy 76.689635 21.35)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 76.689635 21.866371) (xy 76.673 21.95) (xy 76.673 23.673) (xy 76.363322 23.673) (xy 76.359535 23.667332)
(xy 75.977504 23.412067) (xy 75.526867 23.32243) (xy 74.973133 23.32243) (xy 74.522496 23.412067) (xy 74.140465 23.667332)
(xy 73.8852 24.049363) (xy 73.795563 24.5) (xy 73.842828 24.737618) (xy 73.365223 25.215223) (xy 73.185952 25.483521)
(xy 73.123 25.8) (xy 73.123 27.199974) (xy 73.009698 27.086673) (xy 72.776309 26.99) (xy 72.33575 26.99)
(xy 72.177 27.14875) (xy 72.177 27.873) (xy 72.197 27.873) (xy 72.197 28.127) (xy 72.177 28.127)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 72.177 28.85125) (xy 72.33575 29.01) (xy 72.776309 29.01) (xy 73.009698 28.913327) (xy 73.160858 28.762168)
(xy 73.183393 28.777225) (xy 73.35 28.810365) (xy 73.866371 28.810365) (xy 73.95 28.827) (xy 74.033629 28.810365)
(xy 74.55 28.810365) (xy 74.716607 28.777225) (xy 74.85785 28.68285) (xy 74.952225 28.541607) (xy 74.985365 28.375)
(xy 74.985365 27.625) (xy 74.952225 27.458393) (xy 74.85785 27.31715) (xy 74.777 27.263128) (xy 74.777 26.899016)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 82.28059 26.899016) (xy 82.336271 27.129611) (xy 82.819078 27.297622) (xy 83.329428 27.268083) (xy 83.663729 27.129611)
(xy 83.71941 26.899016) (xy 83 26.179605) (xy 82.28059 26.899016) (xy 74.777 26.899016) (xy 74.777 26.142554)
(xy 75.100476 25.819078) (xy 81.702378 25.819078) (xy 81.731917 26.329428) (xy 81.870389 26.663729) (xy 82.100984 26.71941)
(xy 82.820395 26) (xy 83.179605 26) (xy 83.899016 26.71941) (xy 84.129611 26.663729) (xy 84.297622 26.180922)
(xy 84.268083 25.670572) (xy 84.129611 25.336271) (xy 83.899016 25.28059) (xy 83.179605 26) (xy 82.820395 26)
(xy 82.100984 25.28059) (xy 81.870389 25.336271) (xy 81.702378 25.819078) (xy 75.100476 25.819078) (xy 75.241985 25.67757)
(xy 75.526867 25.67757) (xy 75.977504 25.587933) (xy 76.359535 25.332668) (xy 76.363322 25.327) (xy 79.55 25.327)
(xy 79.866479 25.264048) (xy 80.110521 25.100984) (xy 82.28059 25.100984) (xy 83 25.820395) (xy 83.71941 25.100984)
(xy 83.663729 24.870389) (xy 83.180922 24.702378) (xy 82.670572 24.731917) (xy 82.336271 24.870389) (xy 82.28059 25.100984)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 80.110521 25.100984) (xy 80.134777 25.084777) (xy 81.892554 23.327) (xy 81.954719 23.327) (xy 82.04215 23.45785)
(xy 82.183393 23.552225) (xy 82.35 23.585365) (xy 83.65 23.585365) (xy 83.816607 23.552225) (xy 83.95785 23.45785)
(xy 84.045281 23.327) (xy 84.107446 23.327) (xy 84.623 23.842554) (xy 84.623 28.74) (xy 84.33575 28.74)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 84.177 28.89875) (xy 84.177 29.623) (xy 84.197 29.623) (xy 84.197 29.877) (xy 84.177 29.877)
(xy 84.177 30.60125) (xy 84.20075 30.625) (xy 84.177 30.64875) (xy 84.177 31.373) (xy 84.197 31.373)
(xy 84.197 31.627) (xy 84.177 31.627) (xy 84.177 32.35125) (xy 84.33575 32.51) (xy 84.623 32.51)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 84.623 32.873) (xy 84 32.873) (xy 83.951399 32.882667) (xy 83.910197 32.910197) (xy 83.882667 32.951399)
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(xy 83.873 33) (xy 83.873 36.923) (xy 83.75 36.923) (xy 83.433521 36.985952) (xy 83.228414 37.123)
(xy 78.49764 37.123) (xy 78.584777 37.064777) (xy 79.084777 36.564777) (xy 79.264048 36.296479) (xy 79.327 35.98)
(xy 79.327 35.196223) (xy 79.412504 35.110868) (xy 79.576813 34.715168) (xy 79.577187 34.286711) (xy 79.413569 33.890725)
(xy 79.110868 33.587496) (xy 78.715168 33.423187) (xy 78.286711 33.422813) (xy 77.890725 33.586431) (xy 77.587496 33.889132)
(xy 77.423187 34.284832) (xy 77.422813 34.713289) (xy 77.586431 35.109275) (xy 77.673 35.195995) (xy 77.673 35.637446)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 77.657446 35.653) (xy 73.810365 35.653) (xy 73.810365 35.6) (xy 73.777225 35.433393) (xy 73.762168 35.410858)
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(xy 73.913327 35.259698) (xy 74.01 35.026309) (xy 74.01 34.58575) (xy 73.85125 34.427) (xy 73.127 34.427)
(xy 73.127 34.447) (xy 72.873 34.447) (xy 72.873 34.427) (xy 72.14875 34.427) (xy 72.125 34.45075)
(xy 72.10125 34.427) (xy 71.377 34.427) (xy 71.377 34.447) (xy 71.123 34.447) (xy 71.123 34.427)
(xy 70.39875 34.427) (xy 70.375 34.45075) (xy 70.35125 34.427) (xy 69.627 34.427) (xy 69.627 34.447)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 69.373 34.447) (xy 69.373 34.427) (xy 69.353 34.427) (xy 69.353 34.173) (xy 69.373 34.173)
(xy 69.373 33.22375) (xy 69.627 33.22375) (xy 69.627 34.173) (xy 70.35125 34.173) (xy 70.375 34.14925)
(xy 70.39875 34.173) (xy 71.123 34.173) (xy 71.123 33.22375) (xy 71.377 33.22375) (xy 71.377 34.173)
(xy 72.10125 34.173) (xy 72.125 34.14925) (xy 72.14875 34.173) (xy 72.873 34.173) (xy 72.873 33.22375)
(xy 73.127 33.22375) (xy 73.127 34.173) (xy 73.85125 34.173) (xy 74.01 34.01425) (xy 74.01 33.573691)
(xy 73.913327 33.340302) (xy 73.734699 33.161673) (xy 73.50131 33.065) (xy 73.28575 33.065) (xy 73.127 33.22375)
(xy 72.873 33.22375) (xy 72.71425 33.065) (xy 72.49869 33.065) (xy 72.265301 33.161673) (xy 72.125 33.301975)
(xy 71.984699 33.161673) (xy 71.75131 33.065) (xy 71.53575 33.065) (xy 71.377 33.22375) (xy 71.123 33.22375)
(xy 70.96425 33.065) (xy 70.74869 33.065) (xy 70.515301 33.161673) (xy 70.375 33.301975) (xy 70.234699 33.161673)
(xy 70.00131 33.065) (xy 69.78575 33.065) (xy 69.627 33.22375) (xy 69.373 33.22375) (xy 69.21425 33.065)
(xy 68.99869 33.065) (xy 68.765301 33.161673) (xy 68.586673 33.340302) (xy 68.49 33.573691) (xy 68.49 34.01425)
(xy 68.648748 34.172998) (xy 68.49 34.172998) (xy 68.49 34.273312) (xy 68.376097 34.197205) (xy 68.20949 34.164065)
(xy 66.21051 34.164065) (xy 66.043903 34.197205) (xy 65.90266 34.29158) (xy 65.808285 34.432823) (xy 65.775145 34.59943)
(xy 65.775145 36.10057) (xy 65.808285 36.267177) (xy 65.90266 36.40842) (xy 66.043903 36.502795) (xy 66.21051 36.535935)
(xy 66.383 36.535935) (xy 66.383 39.123) (xy 65.31789 39.123) (xy 65.502668 38.999535) (xy 65.757933 38.617504)
(xy 65.84757 38.166867) (xy 65.84757 37.613133) (xy 65.757933 37.162496) (xy 65.502668 36.780465) (xy 65.297 36.643042)
(xy 65.297 34.360792) (xy 67.430792 32.227) (xy 67.870006 32.227) (xy 67.897775 32.366607) (xy 67.99215 32.50785)
(xy 68.133393 32.602225) (xy 68.3 32.635365) (xy 69.2 32.635365) (xy 69.366607 32.602225) (xy 69.50785 32.50785)
(xy 69.602225 32.366607) (xy 69.626016 32.247) (xy 69.954832 32.247) (xy 69.99215 32.30285) (xy 70.133393 32.397225)
(xy 70.3 32.430365) (xy 71.5 32.430365) (xy 71.666607 32.397225) (xy 71.689142 32.382168) (xy 71.840302 32.533327)
(xy 72.073691 32.63) (xy 72.51425 32.63) (xy 72.673 32.47125) (xy 72.673 31.747) (xy 72.927 31.747)
(xy 72.927 32.47125) (xy 73.08575 32.63) (xy 73.526309 32.63) (xy 73.759698 32.533327) (xy 73.938327 32.354699)
(xy 74.035 32.12131) (xy 74.035 31.90575) (xy 73.87625 31.747) (xy 72.927 31.747) (xy 72.673 31.747)
(xy 72.653 31.747) (xy 72.653 31.493) (xy 72.673 31.493) (xy 72.673 30.76875) (xy 72.927 30.76875)
(xy 72.927 31.493) (xy 73.87625 31.493) (xy 74.035 31.33425) (xy 74.035 31.28575) (xy 77.215 31.28575)
(xy 77.215 31.776309) (xy 77.311673 32.009698) (xy 77.490301 32.188327) (xy 77.72369 32.285) (xy 78.21425 32.285)
(xy 78.373 32.12625) (xy 78.373 31.127) (xy 78.627 31.127) (xy 78.627 32.12625) (xy 78.78575 32.285)
(xy 79.27631 32.285) (xy 79.509699 32.188327) (xy 79.688327 32.009698) (xy 79.781089 31.78575) (xy 82.815 31.78575)
(xy 82.815 32.00131) (xy 82.911673 32.234699) (xy 83.090302 32.413327) (xy 83.323691 32.51) (xy 83.76425 32.51)
(xy 83.923 32.35125) (xy 83.923 31.627) (xy 82.97375 31.627) (xy 82.815 31.78575) (xy 79.781089 31.78575)
(xy 79.785 31.776309) (xy 79.785 31.28575) (xy 79.62625 31.127) (xy 78.627 31.127) (xy 78.373 31.127)
(xy 77.37375 31.127) (xy 77.215 31.28575) (xy 74.035 31.28575) (xy 74.035 31.11869) (xy 73.938327 30.885301)
(xy 73.759698 30.706673) (xy 73.526309 30.61) (xy 73.08575 30.61) (xy 72.927 30.76875) (xy 72.673 30.76875)
(xy 72.51425 30.61) (xy 72.073691 30.61) (xy 71.840302 30.706673) (xy 71.689142 30.857832) (xy 71.666607 30.842775)
(xy 71.5 30.809635) (xy 70.3 30.809635) (xy 70.133393 30.842775) (xy 69.99215 30.93715) (xy 69.954832 30.993)
(xy 69.633973 30.993) (xy 69.602225 30.833393) (xy 69.50785 30.69215) (xy 69.366607 30.597775) (xy 69.2 30.564635)
(xy 68.3 30.564635) (xy 68.133393 30.597775) (xy 67.99215 30.69215) (xy 67.897775 30.833393) (xy 67.870006 30.973)
(xy 67.17108 30.973) (xy 66.931137 31.020728) (xy 66.727724 31.156644) (xy 64.226644 33.657724) (xy 64.090728 33.861137)
(xy 64.043 34.10108) (xy 64.043 36.643042) (xy 63.837332 36.780465) (xy 63.582067 37.162496) (xy 63.49243 37.613133)
(xy 63.49243 38.166867) (xy 63.582067 38.617504) (xy 63.837332 38.999535) (xy 64.02211 39.123) (xy 53.127 39.123)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 53.127 36.953191) (xy 53.372805 36.953191) (xy 53.544019 37.36756) (xy 53.860772 37.684867) (xy 54.274842 37.856804)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 54.723191 37.857195) (xy 55.13756 37.685981) (xy 55.266767 37.557) (xy 60.50108 37.557) (xy 60.817559 37.494048)
(xy 61.085857 37.314777) (xy 61.873065 36.52757) (xy 62.406867 36.52757) (xy 62.857504 36.437933) (xy 63.239535 36.182668)
(xy 63.4948 35.800637) (xy 63.584437 35.35) (xy 63.4948 34.899363) (xy 63.239535 34.517332) (xy 62.957 34.328548)
(xy 62.957 33.712554) (xy 64.592472 32.077082) (xy 64.713289 32.077187) (xy 65.109275 31.913569) (xy 65.396344 31.627)
(xy 65.5 31.627) (xy 65.739943 31.579272) (xy 65.943356 31.443356) (xy 67.359712 30.027) (xy 67.870006 30.027)
(xy 67.897775 30.166607) (xy 67.99215 30.30785) (xy 68.133393 30.402225) (xy 68.3 30.435365) (xy 69.2 30.435365)
(xy 69.366607 30.402225) (xy 69.50785 30.30785) (xy 69.564082 30.223691) (xy 77.215 30.223691) (xy 77.215 30.71425)
(xy 77.37375 30.873) (xy 78.373 30.873) (xy 78.373 29.87375) (xy 78.627 29.87375) (xy 78.627 30.873)
(xy 79.62625 30.873) (xy 79.785 30.71425) (xy 79.785 30.223691) (xy 79.707153 30.03575) (xy 82.815 30.03575)
(xy 82.815 30.25131) (xy 82.911673 30.484699) (xy 83.051975 30.625) (xy 82.911673 30.765301) (xy 82.815 30.99869)
(xy 82.815 31.21425) (xy 82.97375 31.373) (xy 83.923 31.373) (xy 83.923 30.64875) (xy 83.89925 30.625)
(xy 83.923 30.60125) (xy 83.923 29.877) (xy 82.97375 29.877) (xy 82.815 30.03575) (xy 79.707153 30.03575)
(xy 79.688327 29.990302) (xy 79.509699 29.811673) (xy 79.27631 29.715) (xy 78.78575 29.715) (xy 78.627 29.87375)
(xy 78.373 29.87375) (xy 78.21425 29.715) (xy 77.72369 29.715) (xy 77.490301 29.811673) (xy 77.311673 29.990302)
(xy 77.215 30.223691) (xy 69.564082 30.223691) (xy 69.602225 30.166607) (xy 69.635365 30) (xy 69.635365 29.24869)
(xy 82.815 29.24869) (xy 82.815 29.46425) (xy 82.97375 29.623) (xy 83.923 29.623) (xy 83.923 28.89875)
(xy 83.76425 28.74) (xy 83.323691 28.74) (xy 83.090302 28.836673) (xy 82.911673 29.015301) (xy 82.815 29.24869)
(xy 69.635365 29.24869) (xy 69.635365 28.8) (xy 69.602225 28.633393) (xy 69.50785 28.49215) (xy 69.366607 28.397775)
(xy 69.2 28.364635) (xy 68.3 28.364635) (xy 68.133393 28.397775) (xy 67.99215 28.49215) (xy 67.897775 28.633393)
(xy 67.870006 28.773) (xy 67.1 28.773) (xy 66.860058 28.820727) (xy 66.656644 28.956644) (xy 65.748245 29.865043)
(xy 65.785 29.776309) (xy 65.785 29.28575) (xy 65.62625 29.127) (xy 64.627 29.127) (xy 64.627 29.147)
(xy 64.373 29.147) (xy 64.373 29.127) (xy 63.37375 29.127) (xy 63.215 29.28575) (xy 63.215 29.776309)
(xy 63.311673 30.009698) (xy 63.490301 30.188327) (xy 63.701159 30.275667) (xy 63.587496 30.389132) (xy 63.423187 30.784832)
(xy 63.42308 30.907366) (xy 61.545223 32.785223) (xy 61.365952 33.053521) (xy 61.303 33.37) (xy 61.303 34.328548)
(xy 61.020465 34.517332) (xy 60.7652 34.899363) (xy 60.675563 35.35) (xy 60.68153 35.379996) (xy 60.158526 35.903)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 55.266872 35.903) (xy 55.139228 35.775133) (xy 54.725158 35.603196) (xy 54.276809 35.602805) (xy 53.86244 35.774019)
(xy 53.545133 36.090772) (xy 53.373196 36.504842) (xy 53.372805 36.953191) (xy 53.127 36.953191) (xy 53.127 35.125275)
(xy 53.744331 35.125275) (xy 53.806169 35.361042) (xy 54.307122 35.537419) (xy 54.83744 35.508664) (xy 55.193831 35.361042)
(xy 55.255669 35.125275) (xy 54.5 34.369605) (xy 53.744331 35.125275) (xy 53.127 35.125275) (xy 53.127 33.997122)
(xy 53.152581 33.997122) (xy 53.181336 34.52744) (xy 53.328958 34.883831) (xy 53.564725 34.945669) (xy 54.320395 34.19)
(xy 54.679605 34.19) (xy 55.435275 34.945669) (xy 55.671042 34.883831) (xy 55.847419 34.382878) (xy 55.818664 33.85256)
(xy 55.671042 33.496169) (xy 55.435275 33.434331) (xy 54.679605 34.19) (xy 54.320395 34.19) (xy 53.564725 33.434331)
(xy 53.328958 33.496169) (xy 53.152581 33.997122) (xy 53.127 33.997122) (xy 53.127 33.254725) (xy 53.744331 33.254725)
(xy 54.5 34.010395) (xy 55.255669 33.254725) (xy 55.193831 33.018958) (xy 54.692878 32.842581) (xy 54.16256 32.871336)
(xy 53.806169 33.018958) (xy 53.744331 33.254725) (xy 53.127 33.254725) (xy 53.127 31.873191) (xy 53.372805 31.873191)
(xy 53.544019 32.28756) (xy 53.860772 32.604867) (xy 54.274842 32.776804) (xy 54.723191 32.777195) (xy 55.13756 32.605981)
(xy 55.454867 32.289228) (xy 55.626804 31.875158) (xy 55.626963 31.692591) (xy 59.095863 28.223691) (xy 63.215 28.223691)
(xy 63.215 28.71425) (xy 63.37375 28.873) (xy 64.373 28.873) (xy 64.373 27.87375) (xy 64.627 27.87375)
(xy 64.627 28.873) (xy 65.62625 28.873) (xy 65.785 28.71425) (xy 65.785 28.28575) (xy 70.815 28.28575)
(xy 70.815 28.50131) (xy 70.911673 28.734699) (xy 71.090302 28.913327) (xy 71.323691 29.01) (xy 71.76425 29.01)
(xy 71.923 28.85125) (xy 71.923 28.127) (xy 70.97375 28.127) (xy 70.815 28.28575) (xy 65.785 28.28575)
(xy 65.785 28.223691) (xy 65.688327 27.990302) (xy 65.509699 27.811673) (xy 65.27631 27.715) (xy 64.78575 27.715)
(xy 64.627 27.87375) (xy 64.373 27.87375) (xy 64.21425 27.715) (xy 63.72369 27.715) (xy 63.490301 27.811673)
(xy 63.311673 27.990302) (xy 63.215 28.223691) (xy 59.095863 28.223691) (xy 59.820864 27.49869) (xy 70.815 27.49869)
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(xy 70.815 27.71425) (xy 70.97375 27.873) (xy 71.923 27.873) (xy 71.923 27.14875) (xy 71.76425 26.99)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 71.323691 26.99) (xy 71.090302 27.086673) (xy 70.911673 27.265301) (xy 70.815 27.49869) (xy 59.820864 27.49869)
(xy 61.500538 25.819016) (xy 63.64059 25.819016) (xy 63.696271 26.049611) (xy 64.179078 26.217622) (xy 64.689428 26.188083)
(xy 65.023729 26.049611) (xy 65.07941 25.819016) (xy 64.36 25.099605) (xy 63.64059 25.819016) (xy 61.500538 25.819016)
(xy 62.580476 24.739078) (xy 63.062378 24.739078) (xy 63.091917 25.249428) (xy 63.230389 25.583729) (xy 63.460984 25.63941)
Improve layout: Audio output
2017-08-17 04:33:41 +02:00
(xy 64.180395 24.92) (xy 64.539605 24.92) (xy 65.259016 25.63941) (xy 65.489611 25.583729) (xy 65.657622 25.100922)
(xy 65.628083 24.590572) (xy 65.489611 24.256271) (xy 65.259016 24.20059) (xy 64.539605 24.92) (xy 64.180395 24.92)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 63.460984 24.20059) (xy 63.230389 24.256271) (xy 63.062378 24.739078) (xy 62.580476 24.739078) (xy 63.425862 23.893693)
(xy 63.543393 23.972225) (xy 63.64737 23.992907) (xy 63.64059 24.020984) (xy 64.36 24.740395) (xy 65.07941 24.020984)
(xy 65.07263 23.992907) (xy 65.176607 23.972225) (xy 65.31785 23.87785) (xy 65.405281 23.747) (xy 66.367446 23.747)
(xy 67.705222 25.084777) (xy 67.729478 25.100984) (xy 67.973521 25.264048) (xy 68.29 25.327) (xy 68.750348 25.327)
(xy 68.768285 25.417177) (xy 68.86266 25.55842) (xy 69.003903 25.652795) (xy 69.17051 25.685935) (xy 71.16949 25.685935)
(xy 71.336097 25.652795) (xy 71.47734 25.55842) (xy 71.571715 25.417177) (xy 71.604855 25.25057) (xy 71.604855 23.74943)
(xy 71.571715 23.582823) (xy 71.47734 23.44158) (xy 71.336097 23.347205) (xy 71.16949 23.314065) (xy 69.17051 23.314065)
(xy 69.003903 23.347205) (xy 68.86266 23.44158) (xy 68.768285 23.582823) (xy 68.750348 23.673) (xy 68.632555 23.673)
(xy 67.723259 22.763705) (xy 67.799273 22.649942) (xy 67.847 22.41) (xy 67.847 20.366071) (xy 67.916607 20.352225)
(xy 68.05785 20.25785) (xy 68.152225 20.116607) (xy 68.185365 19.95) (xy 68.185365 19.05) (xy 68.314635 19.05)
(xy 68.314635 19.95) (xy 68.347775 20.116607) (xy 68.44215 20.25785) (xy 68.583393 20.352225) (xy 68.75 20.385365)
(xy 69.95 20.385365) (xy 70.116607 20.352225) (xy 70.25785 20.25785) (xy 70.345281 20.127) (xy 72.083 20.127)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 72.083 20.713042) (xy 71.877332 20.850465) (xy 71.622067 21.232496) (xy 71.53243 21.683133) (xy 71.53243 22.236867)
(xy 71.622067 22.687504) (xy 71.877332 23.069535) (xy 72.259363 23.3248) (xy 72.71 23.414437) (xy 73.160637 23.3248)
(xy 73.542668 23.069535) (xy 73.797933 22.687504) (xy 73.88757 22.236867) (xy 73.88757 21.683133) (xy 73.797933 21.232496)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 73.542668 20.850465) (xy 73.337 20.713042) (xy 73.337 20.310365) (xy 73.65 20.310365) (xy 73.816607 20.277225)
(xy 73.839142 20.262168) (xy 73.990302 20.413327) (xy 74.223691 20.51) (xy 74.66425 20.51) (xy 74.823 20.35125)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 74.823 19.627) (xy 75.077 19.627) (xy 75.077 20.35125) (xy 75.23575 20.51) (xy 75.676309 20.51)
(xy 75.909698 20.413327) (xy 76.088327 20.234699) (xy 76.185 20.00131) (xy 76.185 19.78575) (xy 76.02625 19.627)
(xy 75.077 19.627) (xy 74.823 19.627) (xy 74.803 19.627) (xy 74.803 19.373) (xy 74.823 19.373)
(xy 74.823 18.64875) (xy 75.077 18.64875) (xy 75.077 19.373) (xy 76.02625 19.373) (xy 76.075559 19.323691)
(xy 76.49 19.323691) (xy 76.49 19.76425) (xy 76.64875 19.923) (xy 77.373 19.923) (xy 77.373 18.97375)
(xy 77.627 18.97375) (xy 77.627 19.923) (xy 78.35125 19.923) (xy 78.51 19.76425) (xy 78.51 19.323691)
(xy 78.413327 19.090302) (xy 78.234699 18.911673) (xy 78.00131 18.815) (xy 77.78575 18.815) (xy 77.627 18.97375)
(xy 77.373 18.97375) (xy 77.21425 18.815) (xy 76.99869 18.815) (xy 76.765301 18.911673) (xy 76.586673 19.090302)
(xy 76.49 19.323691) (xy 76.075559 19.323691) (xy 76.185 19.21425) (xy 76.185 18.99869) (xy 76.088327 18.765301)
(xy 75.909698 18.586673) (xy 75.676309 18.49) (xy 75.23575 18.49) (xy 75.077 18.64875) (xy 74.823 18.64875)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 74.66425 18.49) (xy 74.223691 18.49) (xy 73.990302 18.586673) (xy 73.839142 18.737832) (xy 73.816607 18.722775)
(xy 73.65 18.689635) (xy 72.45 18.689635) (xy 72.283393 18.722775) (xy 72.14215 18.81715) (xy 72.104832 18.873)
(xy 70.345281 18.873) (xy 70.25785 18.74215) (xy 70.116607 18.647775) (xy 69.95 18.614635) (xy 68.75 18.614635)
(xy 68.583393 18.647775) (xy 68.44215 18.74215) (xy 68.347775 18.883393) (xy 68.314635 19.05) (xy 68.185365 19.05)
(xy 68.152225 18.883393) (xy 68.05785 18.74215) (xy 67.916607 18.647775) (xy 67.75 18.614635) (xy 66.55 18.614635)
(xy 66.383393 18.647775) (xy 66.24215 18.74215) (xy 66.147775 18.883393) (xy 66.114635 19.05) (xy 66.114635 19.95)
(xy 66.147775 20.116607) (xy 66.24215 20.25785) (xy 66.383393 20.352225) (xy 66.529212 20.38123) (xy 66.570728 20.589943)
(xy 66.574241 20.5952) (xy 66.593 20.623275) (xy 66.593 22.093) (xy 65.405281 22.093) (xy 65.31785 21.96215)
(xy 65.176607 21.867775) (xy 65.01 21.834635) (xy 63.71 21.834635) (xy 63.543393 21.867775) (xy 63.40215 21.96215)
(xy 63.314719 22.093) (xy 63.23 22.093) (xy 62.913521 22.155952) (xy 62.645222 22.335223) (xy 54.457483 30.522963)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 54.276809 30.522805) (xy 53.86244 30.694019) (xy 53.545133 31.010772) (xy 53.373196 31.424842) (xy 53.372805 31.873191)
(xy 53.127 31.873191) (xy 53.127 30.052606) (xy 65.302606 17.877) (xy 84.623 17.877)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
)
(zone (net 0) (net_name "") (layer B.Cu) (tstamp 0) (hatch edge 0.508)
(connect_pads (clearance 0.3))
(min_thickness 0.254)
(keepout (tracks allowed) (vias not_allowed) (copperpour not_allowed))
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(fill (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(polygon
(pts
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(xy 101.4 41.49) (xy 105.9 41.5) (xy 105.9 45) (xy 101.4 44.99)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
)
(zone (net 0) (net_name "") (layer B.Cu) (tstamp 0) (hatch edge 0.508)
(connect_pads (clearance 0.3))
(min_thickness 0.254)
(keepout (tracks allowed) (vias not_allowed) (copperpour not_allowed))
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(xy 102.19 51.04) (xy 102.19 54.54) (xy 105.61 54.54) (xy 105.61 51.04)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
)
(zone (net 0) (net_name "") (layer B.Cu) (tstamp 0) (hatch edge 0.508)
(connect_pads (clearance 0.3))
(min_thickness 0.254)
(keepout (tracks allowed) (vias allowed) (copperpour not_allowed))
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 52.75 29.75) (xy 56 29.75) (xy 60 29.75) (xy 60.25 30) (xy 60.25 39.25)
(xy 60 39.5) (xy 61 39.5) (xy 61 29.25) (xy 52.75 29.25)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
)
(zone (net 0) (net_name "") (layer B.Cu) (tstamp 0) (hatch edge 0.508)
(connect_pads (clearance 0.3))
(min_thickness 0.254)
(keepout (tracks allowed) (vias not_allowed) (copperpour not_allowed))
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 65.75 27.75) (xy 63.25 27.75) (xy 63.25 32) (xy 65.75 32)
)
)
)
(zone (net 0) (net_name "") (layer B.Cu) (tstamp 59918F07) (hatch edge 0.508)
(connect_pads (clearance 0.3))
(min_thickness 0.254)
(keepout (tracks allowed) (vias not_allowed) (copperpour not_allowed))
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 65.5 21.75) (xy 63.25 21.75) (xy 63.25 26.055494) (xy 65.5 26.055494)
)
)
)
(zone (net 0) (net_name "") (layer B.Cu) (tstamp 0) (hatch edge 0.508)
(connect_pads (clearance 0.3))
(min_thickness 0.254)
(keepout (tracks allowed) (vias not_allowed) (copperpour not_allowed))
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 82 27.25) (xy 84.25 27.25) (xy 84.25 24.75) (xy 81.75 24.75) (xy 81.75 27.25)
)
)
)
(zone (net 1) (net_name Earth) (layer F.Cu) (tstamp 0) (hatch edge 0.508)
(connect_pads (clearance 0.3))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 30 39.5) (xy 30 25) (xy 46 25) (xy 48.5 25) (xy 48.5 43)
(xy 30 43)
)
)
(filled_polygon
(pts
(xy 34.486673 33.340301) (xy 34.409403 33.526847) (xy 34.39 33.54625) (xy 34.39 33.65375) (xy 34.409403 33.673153)
(xy 34.486673 33.859699) (xy 34.664475 34.0375) (xy 34.54875 34.0375) (xy 34.39 34.19625) (xy 34.39 34.27631)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 34.486673 34.509699) (xy 34.589635 34.61266) (xy 34.589635 34.8) (xy 34.609526 34.9) (xy 34.589635 35)
(xy 34.589635 35.45) (xy 34.622775 35.616607) (xy 34.71715 35.75785) (xy 34.858393 35.852225) (xy 35.025 35.885365)
(xy 35.348 35.885365) (xy 35.348 37.114635) (xy 35.3 37.114635) (xy 35.133393 37.147775) (xy 34.99215 37.24215)
(xy 34.897775 37.383393) (xy 34.864635 37.55) (xy 34.864635 38.45) (xy 34.897775 38.616607) (xy 34.99215 38.75785)
(xy 35.133393 38.852225) (xy 35.273 38.879994) (xy 35.273 39.708226) (xy 35.222775 39.783393) (xy 35.195006 39.923)
(xy 34.804994 39.923) (xy 34.777225 39.783393) (xy 34.68285 39.64215) (xy 34.541607 39.547775) (xy 34.375 39.514635)
(xy 33.625 39.514635) (xy 33.458393 39.547775) (xy 33.31715 39.64215) (xy 33.222775 39.783393) (xy 33.189635 39.95)
(xy 33.189635 41.15) (xy 33.222775 41.316607) (xy 33.31715 41.45785) (xy 33.380232 41.5) (xy 33.31715 41.54215)
(xy 33.222775 41.683393) (xy 33.189635 41.85) (xy 33.189635 42.873) (xy 30.127 42.873) (xy 30.127 39.119016)
(xy 31.26059 39.119016) (xy 31.316271 39.349611) (xy 31.799078 39.517622) (xy 32.309428 39.488083) (xy 32.643729 39.349611)
(xy 32.69941 39.119016) (xy 31.98 38.399605) (xy 31.26059 39.119016) (xy 30.127 39.119016) (xy 30.127 39.072243)
(xy 30.214067 39.014067) (xy 30.7101 38.518034) (xy 30.711917 38.549428) (xy 30.850389 38.883729) (xy 31.080984 38.93941)
(xy 31.800395 38.22) (xy 32.159605 38.22) (xy 32.879016 38.93941) (xy 33.109611 38.883729) (xy 33.277622 38.400922)
(xy 33.248083 37.890572) (xy 33.109611 37.556271) (xy 32.879016 37.50059) (xy 32.159605 38.22) (xy 31.800395 38.22)
(xy 31.786252 38.205858) (xy 31.965858 38.026252) (xy 31.98 38.040395) (xy 32.69941 37.320984) (xy 32.69263 37.292907)
(xy 32.796607 37.272225) (xy 32.93785 37.17785) (xy 33.032225 37.036607) (xy 33.065365 36.87) (xy 33.065365 35.57)
(xy 33.032225 35.403393) (xy 32.93785 35.26215) (xy 32.796607 35.167775) (xy 32.63 35.134635) (xy 32.607 35.134635)
(xy 32.607 33.579712) (xy 33.009712 33.177) (xy 34.649975 33.177)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
(filled_polygon
(pts
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 48.373 32.553646) (xy 48.373 42.873) (xy 45.810365 42.873) (xy 45.810365 41.85) (xy 45.777225 41.683393)
(xy 45.68285 41.54215) (xy 45.619768 41.5) (xy 45.68285 41.45785) (xy 45.777225 41.316607) (xy 45.810365 41.15)
(xy 45.810365 39.95) (xy 45.777225 39.783393) (xy 45.68285 39.64215) (xy 45.541607 39.547775) (xy 45.375 39.514635)
(xy 44.625 39.514635) (xy 44.458393 39.547775) (xy 44.31715 39.64215) (xy 44.222775 39.783393) (xy 44.195006 39.923)
(xy 43.804994 39.923) (xy 43.777225 39.783393) (xy 43.68285 39.64215) (xy 43.652 39.621537) (xy 43.652 38.885365)
(xy 43.7 38.885365) (xy 43.866607 38.852225) (xy 44.00785 38.75785) (xy 44.102225 38.616607) (xy 44.135365 38.45)
(xy 44.135365 37.55) (xy 44.102225 37.383393) (xy 44.00785 37.24215) (xy 43.866607 37.147775) (xy 43.7 37.114635)
(xy 43.652 37.114635) (xy 43.652 35.885365) (xy 43.975 35.885365) (xy 44.141607 35.852225) (xy 44.28285 35.75785)
(xy 44.377225 35.616607) (xy 44.410365 35.45) (xy 44.410365 35.23575) (xy 44.99 35.23575) (xy 44.99 35.676309)
(xy 45.086673 35.909698) (xy 45.265301 36.088327) (xy 45.49869 36.185) (xy 45.71425 36.185) (xy 45.873 36.02625)
(xy 45.873 35.077) (xy 46.127 35.077) (xy 46.127 36.02625) (xy 46.28575 36.185) (xy 46.50131 36.185)
(xy 46.734699 36.088327) (xy 46.913327 35.909698) (xy 47.01 35.676309) (xy 47.01 35.23575) (xy 46.85125 35.077)
(xy 46.127 35.077) (xy 45.873 35.077) (xy 45.14875 35.077) (xy 44.99 35.23575) (xy 44.410365 35.23575)
(xy 44.410365 35) (xy 44.390474 34.9) (xy 44.410365 34.8) (xy 44.410365 34.61266) (xy 44.513327 34.509699)
(xy 44.61 34.27631) (xy 44.61 34.19625) (xy 44.45125 34.0375) (xy 44.275891 34.0375) (xy 44.141607 33.947775)
(xy 44.027109 33.925) (xy 44.141607 33.902225) (xy 44.25419 33.827) (xy 45.15 33.827) (xy 45.221994 33.81268)
(xy 45.222775 33.816607) (xy 45.237832 33.839142) (xy 45.086673 33.990302) (xy 44.99 34.223691) (xy 44.99 34.66425)
(xy 45.14875 34.823) (xy 45.873 34.823) (xy 45.873 34.803) (xy 46.127 34.803) (xy 46.127 34.823)
(xy 46.85125 34.823) (xy 47.01 34.66425) (xy 47.01 34.223691) (xy 46.913327 33.990302) (xy 46.762168 33.839142)
(xy 46.777225 33.816607) (xy 46.810365 33.65) (xy 46.810365 32.45) (xy 46.777225 32.283393) (xy 46.68285 32.14215)
(xy 46.541607 32.047775) (xy 46.375 32.014635) (xy 45.625 32.014635) (xy 45.458393 32.047775) (xy 45.371834 32.105611)
(xy 45.453598 32.02399) (xy 45.556882 31.775254) (xy 45.557117 31.505927) (xy 45.454267 31.257011) (xy 45.424308 31.227)
(xy 47.046354 31.227)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
(filled_polygon
(pts
(xy 38.241644 31.768356) (xy 38.445058 31.904273) (xy 38.685 31.952) (xy 40.97 31.952) (xy 41.209943 31.904272)
(xy 41.250758 31.877) (xy 41.789635 31.877) (xy 41.789635 31.93734) (xy 41.686673 32.040301) (xy 41.59 32.27369)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 41.59 32.35375) (xy 41.74875 32.5125) (xy 41.924109 32.5125) (xy 42.058393 32.602225) (xy 42.172891 32.625)
(xy 42.058393 32.647775) (xy 41.924109 32.7375) (xy 41.74875 32.7375) (xy 41.59 32.89625) (xy 41.59 32.97631)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 41.686673 33.209699) (xy 41.751974 33.275) (xy 41.686673 33.340301) (xy 41.59 33.57369) (xy 41.59 33.65375)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 41.74875 33.8125) (xy 41.924109 33.8125) (xy 42.058393 33.902225) (xy 42.172891 33.925) (xy 42.058393 33.947775)
(xy 41.94581 34.023) (xy 41.887632 34.023) (xy 41.695254 33.943118) (xy 41.425927 33.942883) (xy 41.177011 34.045733)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 40.986402 34.23601) (xy 40.883118 34.484746) (xy 40.882883 34.754073) (xy 40.985733 35.002989) (xy 41.17601 35.193598)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 41.424746 35.296882) (xy 41.694073 35.297117) (xy 41.789635 35.257632) (xy 41.789635 35.45) (xy 41.822775 35.616607)
(xy 41.91715 35.75785) (xy 42.058393 35.852225) (xy 42.225 35.885365) (xy 42.548 35.885365) (xy 42.548 37.114635)
(xy 42.5 37.114635) (xy 42.333393 37.147775) (xy 42.19215 37.24215) (xy 42.097775 37.383393) (xy 42.064635 37.55)
(xy 42.064635 38.45) (xy 42.097775 38.616607) (xy 42.19215 38.75785) (xy 42.333393 38.852225) (xy 42.5 38.885365)
(xy 42.548 38.885365) (xy 42.548 39.529951) (xy 42.458393 39.547775) (xy 42.31715 39.64215) (xy 42.222775 39.783393)
(xy 42.189635 39.95) (xy 42.189635 41.15) (xy 42.222775 41.316607) (xy 42.31715 41.45785) (xy 42.380232 41.5)
(xy 42.31715 41.54215) (xy 42.222775 41.683393) (xy 42.189635 41.85) (xy 42.189635 42.873) (xy 42.01 42.873)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 42.01 42.73575) (xy 41.85125 42.577) (xy 41.127 42.577) (xy 41.127 42.597) (xy 40.873 42.597)
(xy 40.873 42.577) (xy 40.14875 42.577) (xy 39.99 42.73575) (xy 39.99 42.873) (xy 39.51 42.873)
(xy 39.51 42.73575) (xy 39.35125 42.577) (xy 38.627 42.577) (xy 38.627 42.597) (xy 38.373 42.597)
(xy 38.373 42.577) (xy 37.64875 42.577) (xy 37.49 42.73575) (xy 37.49 42.873) (xy 36.810365 42.873)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 36.810365 41.85) (xy 36.777225 41.683393) (xy 36.68285 41.54215) (xy 36.619768 41.5) (xy 36.68285 41.45785)
(xy 36.777225 41.316607) (xy 36.810365 41.15) (xy 36.810365 39.95) (xy 36.777225 39.783393) (xy 36.68285 39.64215)
(xy 36.541607 39.547775) (xy 36.527 39.54487) (xy 36.527 38.879994) (xy 36.666607 38.852225) (xy 36.80785 38.75785)
(xy 36.902225 38.616607) (xy 36.935365 38.45) (xy 36.935365 37.55) (xy 37.064635 37.55) (xy 37.064635 38.45)
(xy 37.097775 38.616607) (xy 37.19215 38.75785) (xy 37.333393 38.852225) (xy 37.5 38.885365) (xy 37.548 38.885365)
(xy 37.548 40.15) (xy 37.590018 40.361242) (xy 37.689635 40.510328) (xy 37.689635 41.15) (xy 37.722775 41.316607)
(xy 37.737832 41.339142) (xy 37.586673 41.490302) (xy 37.49 41.723691) (xy 37.49 42.16425) (xy 37.64875 42.323)
(xy 38.373 42.323) (xy 38.373 42.303) (xy 38.627 42.303) (xy 38.627 42.323) (xy 39.35125 42.323)
(xy 39.51 42.16425) (xy 39.51 41.723691) (xy 39.413327 41.490302) (xy 39.262168 41.339142) (xy 39.277225 41.316607)
(xy 39.310365 41.15) (xy 39.310365 39.95) (xy 39.277225 39.783393) (xy 39.18285 39.64215) (xy 39.041607 39.547775)
(xy 38.875 39.514635) (xy 38.652 39.514635) (xy 38.652 38.885365) (xy 38.7 38.885365) (xy 38.866607 38.852225)
(xy 39.00785 38.75785) (xy 39.102225 38.616607) (xy 39.135365 38.45) (xy 39.135365 37.55) (xy 39.864635 37.55)
(xy 39.864635 38.45) (xy 39.897775 38.616607) (xy 39.99215 38.75785) (xy 40.133393 38.852225) (xy 40.3 38.885365)
(xy 40.348 38.885365) (xy 40.348 39.621537) (xy 40.31715 39.64215) (xy 40.222775 39.783393) (xy 40.189635 39.95)
(xy 40.189635 41.15) (xy 40.222775 41.316607) (xy 40.237832 41.339142) (xy 40.086673 41.490302) (xy 39.99 41.723691)
(xy 39.99 42.16425) (xy 40.14875 42.323) (xy 40.873 42.323) (xy 40.873 42.303) (xy 41.127 42.303)
(xy 41.127 42.323) (xy 41.85125 42.323) (xy 42.01 42.16425) (xy 42.01 41.723691) (xy 41.913327 41.490302)
(xy 41.762168 41.339142) (xy 41.777225 41.316607) (xy 41.810365 41.15) (xy 41.810365 39.95) (xy 41.777225 39.783393)
(xy 41.68285 39.64215) (xy 41.541607 39.547775) (xy 41.452 39.529951) (xy 41.452 38.885365) (xy 41.5 38.885365)
(xy 41.666607 38.852225) (xy 41.80785 38.75785) (xy 41.902225 38.616607) (xy 41.935365 38.45) (xy 41.935365 37.55)
(xy 41.902225 37.383393) (xy 41.80785 37.24215) (xy 41.666607 37.147775) (xy 41.5 37.114635) (xy 40.3 37.114635)
(xy 40.133393 37.147775) (xy 39.99215 37.24215) (xy 39.897775 37.383393) (xy 39.864635 37.55) (xy 39.135365 37.55)
(xy 39.102225 37.383393) (xy 39.00785 37.24215) (xy 38.866607 37.147775) (xy 38.7 37.114635) (xy 37.5 37.114635)
(xy 37.333393 37.147775) (xy 37.19215 37.24215) (xy 37.097775 37.383393) (xy 37.064635 37.55) (xy 36.935365 37.55)
(xy 36.902225 37.383393) (xy 36.80785 37.24215) (xy 36.666607 37.147775) (xy 36.5 37.114635) (xy 36.452 37.114635)
(xy 36.452 35.885365) (xy 36.635159 35.885365) (xy 36.573126 36.034756) (xy 36.572874 36.323975) (xy 36.68332 36.591275)
(xy 36.88765 36.795961) (xy 37.154756 36.906874) (xy 37.443975 36.907126) (xy 37.711275 36.79668) (xy 37.915961 36.59235)
(xy 38.026874 36.325244) (xy 38.027126 36.036025) (xy 37.927 35.793701) (xy 37.927 34.7) (xy 37.900074 34.564635)
(xy 37.879273 34.460058) (xy 37.743356 34.256644) (xy 37.618356 34.131644) (xy 37.549094 34.085365) (xy 37.414943 33.995728)
(xy 37.216726 33.9563) (xy 37.313327 33.859699) (xy 37.390597 33.673153) (xy 37.41 33.65375) (xy 37.41 33.54625)
(xy 37.390597 33.526847) (xy 37.313327 33.340301) (xy 37.135525 33.1625) (xy 37.25125 33.1625) (xy 37.41 33.00375)
(xy 37.41 32.92369) (xy 37.313327 32.690301) (xy 37.210365 32.58734) (xy 37.210365 32.4) (xy 37.190474 32.3)
(xy 37.210365 32.2) (xy 37.210365 31.75) (xy 37.190474 31.65) (xy 37.210365 31.55) (xy 37.210365 31.227)
(xy 37.700288 31.227)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
(filled_polygon
(pts
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 41.789635 27) (xy 41.809526 27.1) (xy 41.789635 27.2) (xy 41.789635 27.523) (xy 41.680758 27.523)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 41.639943 27.495728) (xy 41.4 27.448) (xy 40.315 27.448) (xy 40.075058 27.495727) (xy 39.871644 27.631644)
(xy 39.306644 28.196644) (xy 39.170728 28.400057) (xy 39.123 28.64) (xy 39.123 30.698) (xy 38.944712 30.698)
(xy 38.478356 30.231644) (xy 38.274942 30.095728) (xy 38.035 30.048) (xy 37.795058 30.095728) (xy 37.754242 30.123)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 37.05419 30.123) (xy 36.941607 30.047775) (xy 36.827109 30.025) (xy 36.941607 30.002225) (xy 37.075891 29.9125)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 37.25125 29.9125) (xy 37.41 29.75375) (xy 37.41 29.67369) (xy 37.313327 29.440301) (xy 37.210365 29.33734)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 37.210365 29.15) (xy 37.190474 29.05) (xy 37.210365 28.95) (xy 37.210365 28.5) (xy 37.190474 28.4)
(xy 37.210365 28.3) (xy 37.210365 27.85) (xy 37.190474 27.75) (xy 37.210365 27.65) (xy 37.210365 27.2)
(xy 37.190474 27.1) (xy 37.210365 27) (xy 37.210365 26.627) (xy 41.789635 26.627)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
(filled_polygon
(pts
(xy 34.094677 29.115323) (xy 34.273758 29.234982) (xy 34.485 29.277) (xy 34.589635 29.277) (xy 34.589635 29.33734)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 34.486673 29.440301) (xy 34.39 29.67369) (xy 34.39 29.75375) (xy 34.54875 29.9125) (xy 34.724109 29.9125)
(xy 34.858393 30.002225) (xy 34.972891 30.025) (xy 34.858393 30.047775) (xy 34.74581 30.123) (xy 33.51 30.123)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 33.51 29.73575) (xy 33.35125 29.577) (xy 32.627 29.577) (xy 32.627 29.597) (xy 32.373 29.597)
(xy 32.373 29.577) (xy 32.353 29.577) (xy 32.353 29.323) (xy 32.373 29.323) (xy 32.373 29.303)
(xy 32.627 29.303) (xy 32.627 29.323) (xy 33.35125 29.323) (xy 33.51 29.16425) (xy 33.51 28.723691)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 33.413327 28.490302) (xy 33.262168 28.339142) (xy 33.270281 28.327) (xy 33.306354 28.327)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
)
(zone (net 0) (net_name "") (layer F.Cu) (tstamp 0) (hatch edge 0.508)
(connect_pads (clearance 0.3))
(min_thickness 0.254)
(keepout (tracks allowed) (vias not_allowed) (copperpour not_allowed))
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 37 26.5) (xy 42 26.5) (xy 42 26) (xy 37 26)
)
)
)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(zone (net 13) (net_name GNDPWR) (layer F.Cu) (tstamp 0) (hatch edge 0.508)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(connect_pads (clearance 0.3))
(min_thickness 0.25)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 69 40) (xy 69 61.5) (xy 89.5 61.5) (xy 89.5 52) (xy 91 52)
(xy 91 40.5) (xy 91 39.5) (xy 69 39.5)
)
)
(filled_polygon
(pts
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 73.976674 40.2) (xy 74.009659 40.365827) (xy 74.103592 40.506408) (xy 74.244173 40.600341) (xy 74.41 40.633326)
(xy 76.41 40.633326) (xy 76.575827 40.600341) (xy 76.716408 40.506408) (xy 76.810341 40.365827) (xy 76.843326 40.2)
(xy 76.843326 39.625) (xy 77.976674 39.625) (xy 77.976674 40.2) (xy 78.009659 40.365827) (xy 78.103592 40.506408)
(xy 78.244173 40.600341) (xy 78.302711 40.611985) (xy 77.808022 41.106674) (xy 77.125 41.106674) (xy 76.959173 41.139659)
(xy 76.846417 41.215) (xy 72.598883 41.215) (xy 72.574834 41.190951) (xy 72.575186 40.787107) (xy 72.411872 40.391857)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 72.109733 40.089191) (xy 71.714769 39.925187) (xy 71.287107 39.924814) (xy 70.891857 40.088128) (xy 70.589191 40.390267)
(xy 70.425187 40.785231) (xy 70.424814 41.212893) (xy 70.588128 41.608143) (xy 70.890267 41.910809) (xy 71.285231 42.074813)
(xy 71.691284 42.075167) (xy 71.833117 42.217) (xy 71.78725 42.217) (xy 71.629 42.37525) (xy 71.629 43.371)
(xy 72.62475 43.371) (xy 72.783 43.21275) (xy 72.783 42.724089) (xy 72.686632 42.491435) (xy 72.660197 42.465)
(xy 74.804385 42.465) (xy 74.885016 42.660143) (xy 74.97042 42.745696) (xy 73.558058 44.158058) (xy 73.422575 44.360823)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 73.375 44.6) (xy 73.375 45.405788) (xy 73.243592 45.493592) (xy 73.149659 45.634173) (xy 73.116674 45.8)
(xy 73.116674 47) (xy 73.149659 47.165827) (xy 73.243592 47.306408) (xy 73.384173 47.400341) (xy 73.55 47.433326)
(xy 74.45 47.433326) (xy 74.615827 47.400341) (xy 74.756408 47.306408) (xy 74.850341 47.165827) (xy 74.883326 47)
(xy 74.883326 45.8) (xy 74.850341 45.634173) (xy 74.756408 45.493592) (xy 74.625 45.405788) (xy 74.625 44.858884)
(xy 75.748884 43.735) (xy 76.846417 43.735) (xy 76.861383 43.745) (xy 76.818592 43.773592) (xy 76.724659 43.914173)
(xy 76.691674 44.08) (xy 76.691674 44.68) (xy 76.724659 44.845827) (xy 76.818592 44.986408) (xy 76.861383 45.015)
(xy 76.818592 45.043592) (xy 76.724659 45.184173) (xy 76.691674 45.35) (xy 76.691674 45.95) (xy 76.724659 46.115827)
(xy 76.818592 46.256408) (xy 76.861383 46.285) (xy 76.846417 46.295) (xy 76.620005 46.295) (xy 76.62 46.294999)
(xy 76.380823 46.342575) (xy 76.178058 46.478058) (xy 74.838966 47.81715) (xy 74.756408 47.693592) (xy 74.615827 47.599659)
(xy 74.45 47.566674) (xy 73.55 47.566674) (xy 73.384173 47.599659) (xy 73.243592 47.693592) (xy 73.149659 47.834173)
(xy 73.121647 47.975) (xy 72.65 47.975) (xy 72.410822 48.022575) (xy 72.329606 48.076842) (xy 72.208058 48.158058)
(xy 72.208056 48.158061) (xy 71.808058 48.558058) (xy 71.672575 48.760823) (xy 71.625 49) (xy 71.625 49.655788)
(xy 71.493592 49.743592) (xy 71.399659 49.884173) (xy 71.366674 50.05) (xy 71.366674 51.25) (xy 71.399659 51.415827)
(xy 71.493592 51.556408) (xy 71.618645 51.639965) (xy 71.441434 51.713369) (xy 71.263368 51.891435) (xy 71.167 52.124089)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(xy 71.167 52.56275) (xy 71.32525 52.721) (xy 72.121 52.721) (xy 72.121 52.701) (xy 72.379 52.701)
(xy 72.379 52.721) (xy 73.17475 52.721) (xy 73.333 52.56275) (xy 73.333 52.124089) (xy 73.236632 51.891435)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 73.058566 51.713369) (xy 72.881355 51.639965) (xy 73.006408 51.556408) (xy 73.100341 51.415827) (xy 73.133326 51.25)
(xy 73.133326 50.05) (xy 73.100341 49.884173) (xy 73.006408 49.743592) (xy 72.875 49.655788) (xy 72.875 49.258884)
(xy 72.908883 49.225) (xy 73.121647 49.225) (xy 73.149659 49.365827) (xy 73.243592 49.506408) (xy 73.384173 49.600341)
(xy 73.55 49.633326) (xy 74.45 49.633326) (xy 74.615827 49.600341) (xy 74.756408 49.506408) (xy 74.850341 49.365827)
(xy 74.878353 49.225) (xy 74.94 49.225) (xy 75.179177 49.177425) (xy 75.381942 49.041942) (xy 76.774896 47.648988)
(xy 76.724659 47.724173) (xy 76.691674 47.89) (xy 76.691674 48.49) (xy 76.724659 48.655827) (xy 76.818592 48.796408)
(xy 76.861383 48.825) (xy 76.818592 48.853592) (xy 76.724659 48.994173) (xy 76.691674 49.16) (xy 76.691674 49.76)
(xy 76.724659 49.925827) (xy 76.818592 50.066408) (xy 76.861383 50.095) (xy 76.818592 50.123592) (xy 76.724659 50.264173)
(xy 76.691674 50.43) (xy 76.691674 51.03) (xy 76.724659 51.195827) (xy 76.818592 51.336408) (xy 76.861383 51.365)
(xy 76.818592 51.393592) (xy 76.724659 51.534173) (xy 76.691674 51.7) (xy 76.691674 52.3) (xy 76.724659 52.465827)
(xy 76.818592 52.606408) (xy 76.861383 52.635) (xy 76.818592 52.663592) (xy 76.724659 52.804173) (xy 76.691674 52.97)
(xy 76.691674 53.57) (xy 76.724659 53.735827) (xy 76.818592 53.876408) (xy 76.959173 53.970341) (xy 77.125 54.003326)
(xy 79.075 54.003326) (xy 79.195 53.979457) (xy 79.195 54.171116) (xy 77.39 55.976116) (xy 76.921942 55.508058)
(xy 76.719177 55.372575) (xy 76.48 55.325) (xy 76.303353 55.325) (xy 76.275341 55.184173) (xy 76.259593 55.160604)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(xy 76.411632 55.008565) (xy 76.508 54.775911) (xy 76.508 54.33725) (xy 76.34975 54.179) (xy 75.629 54.179)
(xy 75.629 54.199) (xy 75.371 54.199) (xy 75.371 54.179) (xy 74.65025 54.179) (xy 74.492 54.33725)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 74.492 54.775911) (xy 74.588368 55.008565) (xy 74.740407 55.160604) (xy 74.724659 55.184173) (xy 74.691674 55.35)
(xy 74.691674 56.55) (xy 74.724659 56.715827) (xy 74.818592 56.856408) (xy 74.959173 56.950341) (xy 75.125 56.983326)
(xy 75.875 56.983326) (xy 76.040827 56.950341) (xy 76.181408 56.856408) (xy 76.275341 56.715827) (xy 76.289709 56.643593)
(xy 76.506116 56.86) (xy 76.229442 57.136674) (xy 75.47 57.136674) (xy 75.304173 57.169659) (xy 75.163592 57.263592)
(xy 75.069659 57.404173) (xy 75.036674 57.57) (xy 75.036674 59.27) (xy 75.069659 59.435827) (xy 75.163592 59.576408)
(xy 75.304173 59.670341) (xy 75.47 59.703326) (xy 77.47 59.703326) (xy 77.635827 59.670341) (xy 77.776408 59.576408)
(xy 77.870341 59.435827) (xy 77.903326 59.27) (xy 77.903326 57.57) (xy 79.036674 57.57) (xy 79.036674 59.27)
(xy 79.069659 59.435827) (xy 79.163592 59.576408) (xy 79.304173 59.670341) (xy 79.47 59.703326) (xy 80.319442 59.703326)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(xy 80.408058 59.791942) (xy 80.610823 59.927425) (xy 80.85 59.975001) (xy 80.850005 59.975) (xy 81.924632 59.975)
(xy 82.165156 60.074874) (xy 82.453579 60.075126) (xy 82.720143 59.964984) (xy 82.924267 59.761216) (xy 83.034874 59.494844)
(xy 83.035126 59.206421) (xy 82.924984 58.939857) (xy 82.721216 58.735733) (xy 82.454844 58.625126) (xy 82.166421 58.624874)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 81.924098 58.725) (xy 81.903326 58.725) (xy 81.903326 57.57) (xy 81.870341 57.404173) (xy 81.776408 57.263592)
(xy 81.635827 57.169659) (xy 81.47 57.136674) (xy 79.47 57.136674) (xy 79.304173 57.169659) (xy 79.163592 57.263592)
(xy 79.069659 57.404173) (xy 79.036674 57.57) (xy 77.903326 57.57) (xy 77.870341 57.404173) (xy 77.814013 57.319871)
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(xy 80.261942 54.871942) (xy 80.397425 54.669177) (xy 80.445 54.43) (xy 80.445 45.995005) (xy 80.445001 45.995)
(xy 80.397425 45.755823) (xy 80.261942 45.553058) (xy 79.916942 45.208058) (xy 79.762705 45.105) (xy 81.56 45.105)
(xy 81.791415 45.058969) (xy 81.837446 45.049813) (xy 82.072652 44.892652) (xy 82.276058 44.689246) (xy 82.516715 44.589809)
(xy 82.748993 44.357935) (xy 82.84956 44.115744) (xy 83.16 43.805305) (xy 83.180938 43.826243) (xy 83.091529 44.041563)
(xy 83.091243 44.369769) (xy 83.216577 44.673101) (xy 83.448451 44.905379) (xy 83.751563 45.031243) (xy 83.784807 45.031272)
(xy 83.812555 45.049813) (xy 84.09 45.105) (xy 85.837295 45.105) (xy 85.683058 45.208058) (xy 85.478058 45.413058)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(xy 85.342575 45.615823) (xy 85.295 45.855) (xy 85.295 52.401116) (xy 85.018058 52.678058) (xy 84.882575 52.880823)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 84.835 53.12) (xy 84.835 55.691674) (xy 84.4 55.691674) (xy 84.234173 55.724659) (xy 84.093592 55.818592)
(xy 83.999659 55.959173) (xy 83.966674 56.125) (xy 83.966674 56.875) (xy 83.999659 57.040827) (xy 84.093592 57.181408)
(xy 84.234173 57.275341) (xy 84.375 57.303353) (xy 84.375 57.496674) (xy 83.96 57.496674) (xy 83.794173 57.529659)
(xy 83.653592 57.623592) (xy 83.559659 57.764173) (xy 83.526674 57.93) (xy 83.526674 59.63) (xy 83.559659 59.795827)
(xy 83.653592 59.936408) (xy 83.794173 60.030341) (xy 83.96 60.063326) (xy 85.96 60.063326) (xy 86.125827 60.030341)
(xy 86.266408 59.936408) (xy 86.360341 59.795827) (xy 86.393326 59.63) (xy 86.393326 57.93) (xy 86.360341 57.764173)
(xy 86.266408 57.623592) (xy 86.125827 57.529659) (xy 85.96 57.496674) (xy 85.625 57.496674) (xy 85.625 57.303353)
(xy 85.765827 57.275341) (xy 85.789396 57.259593) (xy 85.941435 57.411632) (xy 86.174089 57.508) (xy 86.61275 57.508)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(xy 86.771 57.34975) (xy 86.771 56.629) (xy 87.029 56.629) (xy 87.029 57.34975) (xy 87.18725 57.508)
(xy 87.625911 57.508) (xy 87.858565 57.411632) (xy 88.036631 57.233566) (xy 88.133 57.000912) (xy 88.133 56.78725)
(xy 87.97475 56.629) (xy 87.029 56.629) (xy 86.771 56.629) (xy 86.751 56.629) (xy 86.751 56.371)
(xy 86.771 56.371) (xy 86.771 55.65025) (xy 87.029 55.65025) (xy 87.029 56.371) (xy 87.97475 56.371)
(xy 88.133 56.21275) (xy 88.133 55.999088) (xy 88.036631 55.766434) (xy 87.858565 55.588368) (xy 87.625911 55.492)
(xy 87.18725 55.492) (xy 87.029 55.65025) (xy 86.771 55.65025) (xy 86.61275 55.492) (xy 86.174089 55.492)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 86.085 55.528902) (xy 86.085 53.378884) (xy 86.091674 53.37221) (xy 86.091674 53.57) (xy 86.124659 53.735827)
(xy 86.218592 53.876408) (xy 86.359173 53.970341) (xy 86.525 54.003326) (xy 88.475 54.003326) (xy 88.640827 53.970341)
(xy 88.781408 53.876408) (xy 88.875341 53.735827) (xy 88.908326 53.57) (xy 88.908326 52.97) (xy 88.875341 52.804173)
(xy 88.781408 52.663592) (xy 88.738617 52.635) (xy 88.781408 52.606408) (xy 88.875341 52.465827) (xy 88.908326 52.3)
(xy 88.908326 51.7) (xy 88.875341 51.534173) (xy 88.781408 51.393592) (xy 88.738617 51.365) (xy 88.781408 51.336408)
(xy 88.875341 51.195827) (xy 88.908326 51.03) (xy 88.908326 50.43) (xy 88.899823 50.38725) (xy 88.917 50.38725)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(xy 88.917 50.825911) (xy 89.013368 51.058565) (xy 89.191434 51.236631) (xy 89.424088 51.333) (xy 89.71275 51.333)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 89.871 51.17475) (xy 89.871 50.229) (xy 89.07525 50.229) (xy 88.917 50.38725) (xy 88.899823 50.38725)
(xy 88.875341 50.264173) (xy 88.781408 50.123592) (xy 88.738617 50.095) (xy 88.781408 50.066408) (xy 88.875341 49.925827)
(xy 88.908326 49.76) (xy 88.908326 49.16) (xy 88.875341 48.994173) (xy 88.781408 48.853592) (xy 88.738617 48.825)
(xy 88.781408 48.796408) (xy 88.875341 48.655827) (xy 88.908326 48.49) (xy 88.908326 47.89) (xy 88.875341 47.724173)
(xy 88.781408 47.583592) (xy 88.738617 47.555) (xy 88.753583 47.545) (xy 88.761116 47.545) (xy 89.116674 47.900558)
(xy 89.116674 48.5) (xy 89.149659 48.665827) (xy 89.243592 48.806408) (xy 89.368645 48.889965) (xy 89.191434 48.963369)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(xy 89.013368 49.141435) (xy 88.917 49.374089) (xy 88.917 49.81275) (xy 89.07525 49.971) (xy 89.871 49.971)
(xy 89.871 49.951) (xy 90.129 49.951) (xy 90.129 49.971) (xy 90.149 49.971) (xy 90.149 50.229)
(xy 90.129 50.229) (xy 90.129 51.17475) (xy 90.28725 51.333) (xy 90.575912 51.333) (xy 90.808566 51.236631)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 90.875 51.170197) (xy 90.875 51.875) (xy 89.5 51.875) (xy 89.452165 51.884515) (xy 89.411612 51.911612)
(xy 89.384515 51.952165) (xy 89.375 52) (xy 89.375 54.401117) (xy 88.518058 55.258058) (xy 88.382575 55.460823)
(xy 88.335 55.7) (xy 88.335 57.496674) (xy 87.96 57.496674) (xy 87.794173 57.529659) (xy 87.653592 57.623592)
(xy 87.559659 57.764173) (xy 87.526674 57.93) (xy 87.526674 59.63) (xy 87.559659 59.795827) (xy 87.653592 59.936408)
(xy 87.794173 60.030341) (xy 87.96 60.063326) (xy 89.375 60.063326) (xy 89.375 60.194989) (xy 69.125 60.194989)
(xy 69.125 56.915836) (xy 69.342 56.959) (xy 69.657714 56.896201) (xy 69.925363 56.717363) (xy 70.104201 56.449714)
(xy 70.167 56.134) (xy 70.104201 55.818286) (xy 69.925363 55.550637) (xy 69.125 54.750274) (xy 69.125 53.13725)
(xy 71.167 53.13725) (xy 71.167 53.575911) (xy 71.263368 53.808565) (xy 71.441434 53.986631) (xy 71.674088 54.083)
(xy 71.96275 54.083) (xy 72.121 53.92475) (xy 72.121 52.979) (xy 72.379 52.979) (xy 72.379 53.92475)
(xy 72.53725 54.083) (xy 72.825912 54.083) (xy 73.058566 53.986631) (xy 73.236632 53.808565) (xy 73.333 53.575911)
(xy 73.333 53.324089) (xy 74.492 53.324089) (xy 74.492 53.76275) (xy 74.65025 53.921) (xy 75.371 53.921)
(xy 75.371 52.97525) (xy 75.629 52.97525) (xy 75.629 53.921) (xy 76.34975 53.921) (xy 76.508 53.76275)
(xy 76.508 53.324089) (xy 76.411632 53.091435) (xy 76.233566 52.913369) (xy 76.000912 52.817) (xy 75.78725 52.817)
(xy 75.629 52.97525) (xy 75.371 52.97525) (xy 75.21275 52.817) (xy 74.999088 52.817) (xy 74.766434 52.913369)
(xy 74.588368 53.091435) (xy 74.492 53.324089) (xy 73.333 53.324089) (xy 73.333 53.13725) (xy 73.17475 52.979)
(xy 72.379 52.979) (xy 72.121 52.979) (xy 71.32525 52.979) (xy 71.167 53.13725) (xy 69.125 53.13725)
(xy 69.125 43.78725) (xy 70.217 43.78725) (xy 70.217 44.275911) (xy 70.313368 44.508565) (xy 70.491434 44.686631)
(xy 70.724088 44.783) (xy 71.21275 44.783) (xy 71.371 44.62475) (xy 71.371 43.629) (xy 71.629 43.629)
(xy 71.629 44.62475) (xy 71.78725 44.783) (xy 72.275912 44.783) (xy 72.508566 44.686631) (xy 72.686632 44.508565)
(xy 72.783 44.275911) (xy 72.783 43.78725) (xy 72.62475 43.629) (xy 71.629 43.629) (xy 71.371 43.629)
(xy 70.37525 43.629) (xy 70.217 43.78725) (xy 69.125 43.78725) (xy 69.125 42.724089) (xy 70.217 42.724089)
(xy 70.217 43.21275) (xy 70.37525 43.371) (xy 71.371 43.371) (xy 71.371 42.37525) (xy 71.21275 42.217)
(xy 70.724088 42.217) (xy 70.491434 42.313369) (xy 70.313368 42.491435) (xy 70.217 42.724089) (xy 69.125 42.724089)
(xy 69.125 39.625) (xy 73.976674 39.625)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(zone (net 13) (net_name GNDPWR) (layer F.Cu) (tstamp 0) (hatch edge 0.508)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(connect_pads (clearance 0.3))
(min_thickness 0.25)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 107.5 61.5) (xy 90 61.5) (xy 90 52.5) (xy 91.5 52.5) (xy 91.5 39.5)
(xy 112 39.5) (xy 112 61.5)
)
)
(filled_polygon
(pts
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(xy 110.625 54.811117) (xy 104.061116 61.375) (xy 102.102733 61.375) (xy 102.271953 61.261931) (xy 110.625 52.908884)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
(filled_polygon
(pts
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(xy 111.875 61.375) (xy 105.828884 61.375) (xy 111.691939 55.511944) (xy 111.691942 55.511942) (xy 111.827425 55.309177)
(xy 111.875 55.07)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
(filled_polygon
(pts
add balance poti
2017-08-28 22:59:34 +02:00
(xy 105.132555 39.834768) (xy 105.161151 40.388996) (xy 105.318229 40.768216) (xy 105.55961 40.837957) (xy 106.357566 40.04)
(xy 106.343424 40.025858) (xy 106.525858 39.843424) (xy 106.54 39.857566) (xy 106.554142 39.843424) (xy 106.736576 40.025858)
(xy 106.722434 40.04) (xy 107.52039 40.837957) (xy 107.761771 40.768216) (xy 107.947445 40.245232) (xy 107.918849 39.691004)
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(xy 107.891509 39.625) (xy 111.875 39.625) (xy 111.875 44.341117) (xy 111.061942 43.528058) (xy 110.859177 43.392575)
(xy 110.62 43.345) (xy 109.030005 43.345) (xy 109.03 43.344999) (xy 108.790823 43.392575) (xy 108.588058 43.528058)
(xy 107.889196 44.22692) (xy 107.764715 44.175231) (xy 107.237598 44.174771) (xy 106.750428 44.376065) (xy 106.377375 44.748468)
(xy 106.175231 45.235285) (xy 106.174771 45.762402) (xy 106.376065 46.249572) (xy 106.748468 46.622625) (xy 107.055375 46.750064)
(xy 106.750428 46.876065) (xy 106.377375 47.248468) (xy 106.324834 47.375) (xy 103.75 47.375) (xy 103.510822 47.422575)
(xy 103.308058 47.558058) (xy 102.408058 48.458058) (xy 102.272575 48.660823) (xy 102.230872 48.870479) (xy 102.084173 48.899659)
(xy 101.943592 48.993592) (xy 101.849659 49.134173) (xy 101.816674 49.3) (xy 101.816674 50.2) (xy 101.849659 50.365827)
(xy 101.943592 50.506408) (xy 102.084173 50.600341) (xy 102.25 50.633326) (xy 103.45 50.633326) (xy 103.615827 50.600341)
(xy 103.756408 50.506408) (xy 103.850341 50.365827) (xy 103.871033 50.261798) (xy 105.955224 50.261798) (xy 105.981657 50.87109)
(xy 106.163969 51.31123) (xy 106.419649 51.397917) (xy 107.317566 50.5) (xy 107.682434 50.5) (xy 108.580351 51.397917)
(xy 108.75 51.340398) (xy 108.919649 51.397917) (xy 109.817566 50.5) (xy 108.919649 49.602083) (xy 108.75 49.659602)
(xy 108.580351 49.602083) (xy 107.682434 50.5) (xy 107.317566 50.5) (xy 106.419649 49.602083) (xy 106.163969 49.68877)
(xy 105.955224 50.261798) (xy 103.871033 50.261798) (xy 103.883326 50.2) (xy 103.883326 49.3) (xy 103.850341 49.134173)
(xy 103.756408 48.993592) (xy 103.686801 48.947083) (xy 104.008884 48.625) (xy 106.324593 48.625) (xy 106.376065 48.749572)
(xy 106.748468 49.122625) (xy 106.768501 49.130943) (xy 106.68877 49.163969) (xy 106.602083 49.419649) (xy 107.5 50.317566)
(xy 108.397917 49.419649) (xy 108.31123 49.163969) (xy 108.226969 49.133274) (xy 108.249572 49.123935) (xy 108.622625 48.751532)
(xy 108.750064 48.444625) (xy 108.876065 48.749572) (xy 109.248468 49.122625) (xy 109.268501 49.130943) (xy 109.18877 49.163969)
(xy 109.102083 49.419649) (xy 110 50.317566) (xy 110.014142 50.303424) (xy 110.196576 50.485858) (xy 110.182434 50.5)
(xy 110.196576 50.514142) (xy 110.014142 50.696576) (xy 110 50.682434) (xy 109.102083 51.580351) (xy 109.18877 51.836031)
(xy 109.732143 52.033973) (xy 106.6329 55.133216) (xy 106.614984 55.089857) (xy 106.411216 54.885733) (xy 106.144844 54.775126)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 105.856421 54.774874) (xy 105.614098 54.875) (xy 105.575741 54.875) (xy 105.575736 54.874999) (xy 105.336559 54.922575)
(xy 105.133794 55.058058) (xy 105.133792 55.058061) (xy 104.140854 56.050998) (xy 103.994752 56.050998) (xy 104.153 55.89275)
(xy 104.153 55.679088) (xy 104.056631 55.446434) (xy 103.878565 55.268368) (xy 103.645911 55.172) (xy 103.20725 55.172)
(xy 103.049 55.33025) (xy 103.049 56.051) (xy 103.069 56.051) (xy 103.069 56.309) (xy 103.049 56.309)
(xy 103.049 56.329) (xy 102.791 56.329) (xy 102.791 56.309) (xy 102.771 56.309) (xy 102.771 56.051)
(xy 102.791 56.051) (xy 102.791 55.33025) (xy 102.63275 55.172) (xy 102.194089 55.172) (xy 101.961435 55.268368)
(xy 101.809396 55.420407) (xy 101.785827 55.404659) (xy 101.62 55.371674) (xy 100.42 55.371674) (xy 100.254173 55.404659)
(xy 100.133934 55.485) (xy 99.750632 55.485) (xy 99.606421 55.484874) (xy 99.606116 55.485) (xy 98.638326 55.485)
(xy 98.638326 55.425) (xy 98.605341 55.259173) (xy 98.511408 55.118592) (xy 98.370827 55.024659) (xy 98.205 54.991674)
(xy 97.605 54.991674) (xy 97.439173 55.024659) (xy 97.298592 55.118592) (xy 97.27 55.161383) (xy 97.241408 55.118592)
(xy 97.100827 55.024659) (xy 96.935 54.991674) (xy 96.335 54.991674) (xy 96.169173 55.024659) (xy 96.028592 55.118592)
(xy 96 55.161383) (xy 95.995 55.1539) (xy 95.995 55.120188) (xy 96.164267 54.951216) (xy 96.274874 54.684844)
(xy 96.275126 54.396421) (xy 96.164984 54.129857) (xy 95.961216 53.925733) (xy 95.694844 53.815126) (xy 95.406421 53.814874)
(xy 95.139857 53.925016) (xy 94.935733 54.128784) (xy 94.825126 54.395156) (xy 94.825094 54.432155) (xy 94.792575 54.480823)
(xy 94.745 54.72) (xy 94.745 55.138934) (xy 94.73 55.161383) (xy 94.701408 55.118592) (xy 94.560827 55.024659)
(xy 94.395 54.991674) (xy 93.795 54.991674) (xy 93.629173 55.024659) (xy 93.488592 55.118592) (xy 93.394659 55.259173)
(xy 93.361674 55.425) (xy 93.361674 56.975) (xy 93.394659 57.140827) (xy 93.47 57.253583) (xy 93.47 57.546117)
(xy 93.399443 57.616674) (xy 92.8 57.616674) (xy 92.634173 57.649659) (xy 92.493592 57.743592) (xy 92.399659 57.884173)
(xy 92.366674 58.05) (xy 92.366674 58.499442) (xy 92.144637 58.721479) (xy 91.984842 58.655126) (xy 91.696419 58.654874)
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(xy 91.429855 58.765016) (xy 91.225731 58.968784) (xy 91.115124 59.235156) (xy 91.114872 59.523579) (xy 91.225014 59.790143)
(xy 91.428782 59.994267) (xy 91.695154 60.104874) (xy 91.983577 60.105126) (xy 92.2259 60.005) (xy 92.37 60.005)
(xy 92.609177 59.957425) (xy 92.811942 59.821942) (xy 93.250558 59.383326) (xy 94 59.383326) (xy 94.165827 59.350341)
(xy 94.306408 59.256408) (xy 94.400341 59.115827) (xy 94.433326 58.95) (xy 94.433326 58.350557) (xy 94.536939 58.246944)
(xy 94.536942 58.246942) (xy 94.566674 58.202445) (xy 94.566674 58.95) (xy 94.599659 59.115827) (xy 94.693592 59.256408)
(xy 94.834173 59.350341) (xy 95 59.383326) (xy 96.2 59.383326) (xy 96.365827 59.350341) (xy 96.506408 59.256408)
(xy 96.600341 59.115827) (xy 96.633326 58.95) (xy 96.633326 58.05) (xy 96.625184 58.009067) (xy 96.808056 58.191939)
(xy 96.808058 58.191942) (xy 96.911146 58.260823) (xy 97.010822 58.327425) (xy 97.25 58.375) (xy 103.325736 58.375)
(xy 103.40735 58.358766) (xy 101.571127 60.194989) (xy 90.125 60.194989) (xy 90.125 60.030506) (xy 90.125827 60.030341)
(xy 90.266408 59.936408) (xy 90.360341 59.795827) (xy 90.393326 59.63) (xy 90.393326 57.93) (xy 90.360341 57.764173)
(xy 90.266408 57.623592) (xy 90.125827 57.529659) (xy 90.125 57.529494) (xy 90.125 55.418884) (xy 90.868883 54.675)
(xy 93.91 54.675) (xy 94.149177 54.627425) (xy 94.351942 54.491942) (xy 95.806942 53.036942) (xy 95.942425 52.834177)
(xy 95.990001 52.595) (xy 95.99 52.594995) (xy 95.99 51.853583) (xy 96 51.838617) (xy 96.028592 51.881408)
(xy 96.169173 51.975341) (xy 96.335 52.008326) (xy 96.935 52.008326) (xy 97.100827 51.975341) (xy 97.241408 51.881408)
(xy 97.27 51.838617) (xy 97.298592 51.881408) (xy 97.439173 51.975341) (xy 97.605 52.008326) (xy 98.205 52.008326)
(xy 98.370827 51.975341) (xy 98.511408 51.881408) (xy 98.605341 51.740827) (xy 98.638326 51.575) (xy 98.638326 51.425)
(xy 99.6 51.425) (xy 99.839177 51.377425) (xy 100.041942 51.241942) (xy 100.253884 51.03) (xy 102.055 51.03)
(xy 102.055 54.53) (xy 102.064515 54.577835) (xy 102.091612 54.618388) (xy 102.132165 54.645485) (xy 102.18 54.655)
(xy 105.61 54.655) (xy 105.657835 54.645485) (xy 105.698388 54.618388) (xy 105.725485 54.577835) (xy 105.735 54.53)
(xy 105.735 51.580351) (xy 106.602083 51.580351) (xy 106.68877 51.836031) (xy 107.261798 52.044776) (xy 107.87109 52.018343)
(xy 108.31123 51.836031) (xy 108.397917 51.580351) (xy 107.5 50.682434) (xy 106.602083 51.580351) (xy 105.735 51.580351)
(xy 105.735 51.03) (xy 105.725485 50.982165) (xy 105.698388 50.941612) (xy 105.657835 50.914515) (xy 105.61 50.905)
(xy 102.18 50.905) (xy 102.132165 50.914515) (xy 102.091612 50.941612) (xy 102.064515 50.982165) (xy 102.055 51.03)
(xy 100.253884 51.03) (xy 100.650558 50.633326) (xy 101.25 50.633326) (xy 101.415827 50.600341) (xy 101.556408 50.506408)
(xy 101.650341 50.365827) (xy 101.683326 50.2) (xy 101.683326 49.3) (xy 101.650341 49.134173) (xy 101.625 49.096247)
(xy 101.625 45.5) (xy 101.577425 45.260823) (xy 101.480109 45.115179) (xy 105.889722 45.125) (xy 105.937835 45.115485)
(xy 105.978388 45.088388) (xy 106.005485 45.047835) (xy 106.015 45) (xy 106.015 41.5) (xy 106.005591 41.452422)
(xy 105.978585 41.411809) (xy 105.938093 41.384622) (xy 105.890278 41.375) (xy 101.400278 41.365) (xy 101.352165 41.374515)
(xy 101.311612 41.401612) (xy 101.284515 41.442165) (xy 101.275 41.49) (xy 101.275 44.891116) (xy 100.375 43.991116)
(xy 100.375 42.008884) (xy 101.363494 41.02039) (xy 105.742043 41.02039) (xy 105.811784 41.261771) (xy 106.334768 41.447445)
(xy 106.888996 41.418849) (xy 107.268216 41.261771) (xy 107.337957 41.02039) (xy 106.54 40.222434) (xy 105.742043 41.02039)
(xy 101.363494 41.02039) (xy 102.758884 39.625) (xy 105.207029 39.625)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
(filled_polygon
(pts
(xy 90.992 52.73725) (xy 90.992 53.175911) (xy 91.088368 53.408565) (xy 91.104803 53.425) (xy 90.61 53.425)
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(xy 90.370822 53.472575) (xy 90.292737 53.52475) (xy 90.168058 53.608058) (xy 90.168056 53.608061) (xy 90.125 53.651117)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 90.125 52.625) (xy 91.10425 52.625)
)
)
(filled_polygon
(pts
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 93.361674 51.575) (xy 93.394659 51.740827) (xy 93.488592 51.881408) (xy 93.629173 51.975341) (xy 93.795 52.008326)
(xy 94.395 52.008326) (xy 94.560827 51.975341) (xy 94.701408 51.881408) (xy 94.73 51.838617) (xy 94.74 51.853583)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 94.74 52.336116) (xy 93.651116 53.425) (xy 92.895197 53.425) (xy 92.911632 53.408565) (xy 93.008 53.175911)
(xy 93.008 52.73725) (xy 92.84975 52.579) (xy 92.129 52.579) (xy 92.129 52.599) (xy 91.871 52.599)
(xy 91.871 52.579) (xy 91.851 52.579) (xy 91.851 52.321) (xy 91.871 52.321) (xy 91.871 52.301)
(xy 92.129 52.301) (xy 92.129 52.321) (xy 92.84975 52.321) (xy 93.008 52.16275) (xy 93.008 51.724089)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 92.911632 51.491435) (xy 92.759593 51.339396) (xy 92.775341 51.315827) (xy 92.803353 51.175) (xy 93.361674 51.175)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
(filled_polygon
(pts
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(xy 99.308058 41.308058) (xy 99.172575 41.510823) (xy 99.125 41.75) (xy 99.125 44.25) (xy 99.172575 44.489177)
(xy 99.308058 44.691942) (xy 100.375 45.758884) (xy 100.375 46.114098) (xy 100.364984 46.089857) (xy 100.161216 45.885733)
add balance poti
2017-08-28 22:59:34 +02:00
(xy 99.894844 45.775126) (xy 99.606421 45.774874) (xy 99.339857 45.885016) (xy 99.135733 46.088784) (xy 99.025126 46.355156)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 99.025081 46.407073) (xy 99.022575 46.410823) (xy 98.975 46.65) (xy 98.975 47.121647) (xy 98.834173 47.149659)
(xy 98.693592 47.243592) (xy 98.599659 47.384173) (xy 98.566674 47.55) (xy 98.566674 48.45) (xy 98.599659 48.615827)
(xy 98.61247 48.635) (xy 98.38753 48.635) (xy 98.400341 48.615827) (xy 98.433326 48.45) (xy 98.433326 47.55)
(xy 98.400341 47.384173) (xy 98.306408 47.243592) (xy 98.165827 47.149659) (xy 98 47.116674) (xy 96.8 47.116674)
(xy 96.634173 47.149659) (xy 96.493592 47.243592) (xy 96.399659 47.384173) (xy 96.366674 47.55) (xy 96.366674 48.149443)
add balance poti
2017-08-28 22:59:34 +02:00
(xy 96.145119 48.370998) (xy 96.024752 48.370998) (xy 96.183 48.21275) (xy 96.183 47.999088) (xy 96.086631 47.766434)
(xy 95.908565 47.588368) (xy 95.675911 47.492) (xy 95.23725 47.492) (xy 95.079 47.65025) (xy 95.079 48.371)
(xy 95.099 48.371) (xy 95.099 48.629) (xy 95.079 48.629) (xy 95.079 49.34975) (xy 95.122683 49.393433)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 94.923058 49.593058) (xy 94.902368 49.624024) (xy 94.899173 49.624659) (xy 94.758592 49.718592) (xy 94.73 49.761383)
(xy 94.72 49.746417) (xy 94.72 49.545) (xy 94.704363 49.466387) (xy 94.821 49.34975) (xy 94.821 48.629)
(xy 94.801 48.629) (xy 94.801 48.371) (xy 94.821 48.371) (xy 94.821 47.65025) (xy 94.66275 47.492)
(xy 94.224089 47.492) (xy 93.991435 47.588368) (xy 93.839396 47.740407) (xy 93.815827 47.724659) (xy 93.675 47.696647)
(xy 93.675 43.5) (xy 94.375 43.5) (xy 94.375 46.5) (xy 94.384515 46.547835) (xy 94.411612 46.588388)
(xy 94.452165 46.615485) (xy 94.5 46.625) (xy 97.5 46.625) (xy 97.547835 46.615485) (xy 97.588388 46.588388)
(xy 97.615485 46.547835) (xy 97.625 46.5) (xy 97.625 43.5) (xy 97.615485 43.452165) (xy 97.588388 43.411612)
(xy 97.547835 43.384515) (xy 97.5 43.375) (xy 97.010803 43.375) (xy 97.050341 43.315827) (xy 97.083326 43.15)
(xy 97.083326 41.85) (xy 97.050341 41.684173) (xy 96.956408 41.543592) (xy 96.815827 41.449659) (xy 96.65 41.416674)
(xy 95.35 41.416674) (xy 95.184173 41.449659) (xy 95.043592 41.543592) (xy 94.949659 41.684173) (xy 94.916674 41.85)
(xy 94.916674 43.15) (xy 94.949659 43.315827) (xy 94.989197 43.375) (xy 94.5 43.375) (xy 94.452165 43.384515)
(xy 94.411612 43.411612) (xy 94.384515 43.452165) (xy 94.375 43.5) (xy 93.675 43.5) (xy 93.675 43.458884)
(xy 94.058832 43.075052) (xy 94.163383 43.075143) (xy 94.466715 42.949809) (xy 94.698993 42.717935) (xy 94.824857 42.414823)
(xy 94.825143 42.086617) (xy 94.699809 41.783285) (xy 94.467935 41.551007) (xy 94.164823 41.425143) (xy 94.100217 41.425087)
(xy 95.900304 39.625) (xy 100.991116 39.625)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
)
(zone (net 0) (net_name "") (layer F.Cu) (tstamp 0) (hatch edge 0.508)
(connect_pads (clearance 0.3))
(min_thickness 0.25)
(keepout (tracks allowed) (vias not_allowed) (copperpour not_allowed))
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 94.5 43.5) (xy 97.5 43.5) (xy 97.5 46.5) (xy 94.5 46.5)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
)
)
)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(zone (net 13) (net_name GNDPWR) (layer F.Cu) (tstamp 0) (hatch edge 0.508)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(priority 2)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(connect_pads (clearance 0.3))
(min_thickness 0.25)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 52.25 56) (xy 58.57 61.97) (xy 60.58 60.85) (xy 53.9 54.23)
)
)
(filled_polygon
(pts
shrink pcb to 100mmx50mm
2017-09-09 23:31:40 +02:00
(xy 59.881971 61.095855) (xy 59.255361 61.445011) (xy 58.578895 61.445011) (xy 52.884438 55.750554) (xy 52.81349 55.578846)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 53.562007 54.775891)
)
)
)
(zone (net 1) (net_name Earth) (layer F.Cu) (tstamp 0) (hatch edge 0.508)
(connect_pads (clearance 0.3))
(min_thickness 0.25)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 59 48.5) (xy 59 46.75) (xy 52.75 46.75) (xy 52.75 40.25) (xy 61.5 40.25)
(xy 65 40.25) (xy 65 52.75) (xy 59 52.75)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
(filled_polygon
(pts
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 64.875 52.625) (xy 59.125 52.625) (xy 59.125 50.28725) (xy 59.267 50.28725) (xy 59.267 51.475912)
(xy 59.363369 51.708566) (xy 59.541435 51.886632) (xy 59.774089 51.983) (xy 61.48775 51.983) (xy 61.646 51.82475)
(xy 61.646 50.129) (xy 61.904 50.129) (xy 61.904 51.82475) (xy 62.06225 51.983) (xy 63.775911 51.983)
(xy 64.008565 51.886632) (xy 64.186631 51.708566) (xy 64.283 51.475912) (xy 64.283 50.28725) (xy 64.12475 50.129)
(xy 61.904 50.129) (xy 61.646 50.129) (xy 59.42525 50.129) (xy 59.267 50.28725) (xy 59.125 50.28725)
(xy 59.125 48.524088) (xy 59.267 48.524088) (xy 59.267 49.71275) (xy 59.42525 49.871) (xy 61.646 49.871)
(xy 61.646 48.17525) (xy 61.904 48.17525) (xy 61.904 49.871) (xy 64.12475 49.871) (xy 64.283 49.71275)
(xy 64.283 48.524088) (xy 64.186631 48.291434) (xy 64.008565 48.113368) (xy 63.775911 48.017) (xy 62.06225 48.017)
(xy 61.904 48.17525) (xy 61.646 48.17525) (xy 61.48775 48.017) (xy 59.774089 48.017) (xy 59.541435 48.113368)
(xy 59.363369 48.291434) (xy 59.267 48.524088) (xy 59.125 48.524088) (xy 59.125 46.75) (xy 59.115485 46.702165)
(xy 59.088388 46.661612) (xy 59.047835 46.634515) (xy 59 46.625) (xy 57.675 46.625) (xy 57.675 43.25)
(xy 57.642649 43.08736) (xy 57.55052 42.94948) (xy 57.41264 42.857351) (xy 57.25 42.825) (xy 55.231979 42.825)
(xy 55.253009 42.745443) (xy 54.5 41.992434) (xy 53.746991 42.745443) (xy 53.785698 42.891871) (xy 53.69948 42.94948)
(xy 52.875 43.77396) (xy 52.875 41.619589) (xy 53.15429 41.619589) (xy 53.183859 42.149064) (xy 53.329593 42.500898)
(xy 53.564557 42.563009) (xy 54.317566 41.81) (xy 54.682434 41.81) (xy 55.435443 42.563009) (xy 55.670407 42.500898)
(xy 55.84571 42.000411) (xy 55.816141 41.470936) (xy 55.670407 41.119102) (xy 55.435443 41.056991) (xy 54.682434 41.81)
(xy 54.317566 41.81) (xy 53.564557 41.056991) (xy 53.329593 41.119102) (xy 53.15429 41.619589) (xy 52.875 41.619589)
(xy 52.875 40.874557) (xy 53.746991 40.874557) (xy 54.5 41.627566) (xy 55.253009 40.874557) (xy 55.190898 40.639593)
(xy 54.690411 40.46429) (xy 54.160936 40.493859) (xy 53.809102 40.639593) (xy 53.746991 40.874557) (xy 52.875 40.874557)
(xy 52.875 40.375) (xy 64.875 40.375)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
)
(zone (net 3) (net_name +5V) (layer F.Cu) (tstamp 0) (hatch edge 0.508)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(priority 1)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(connect_pads (clearance 0.3))
(min_thickness 0.25)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(xy 23.5 54) (xy 45.25 54) (xy 49.25 50) (xy 49.25 48) (xy 54 43.25)
Layout: Small Fix * Fix Footprint of SIL7-reduced. Old version does work, but soldering could become difficult
2017-09-10 20:07:19 +02:00
(xy 55.5 43.25) (xy 57.25 43.25) (xy 57.25 45.25) (xy 57.25 48.25) (xy 57.25 52.75)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(xy 56.75 52.75) (xy 56.75 61.5) (xy 14.5 61.5) (xy 14.5 35.5) (xy 23.5 35.5)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
(filled_polygon
(pts
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(xy 19.317 35.629002) (xy 19.475248 35.629002) (xy 19.317 35.78725) (xy 19.317 36.000912) (xy 19.365086 36.117)
(xy 18.220489 36.117) (xy 17.987835 36.213368) (xy 17.809769 36.391434) (xy 17.7134 36.624088) (xy 17.7134 38.21275)
(xy 17.87165 38.371) (xy 19.9674 38.371) (xy 19.9674 38.351) (xy 20.2254 38.351) (xy 20.2254 38.371)
(xy 22.32115 38.371) (xy 22.4794 38.21275) (xy 22.4794 36.624088) (xy 22.383031 36.391434) (xy 22.299923 36.308326)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 23.05 36.308326) (xy 23.215827 36.275341) (xy 23.356408 36.181408) (xy 23.375 36.153583) (xy 23.375 45.116674)
(xy 21.45 45.116674) (xy 21.284173 45.149659) (xy 21.143592 45.243592) (xy 21.049659 45.384173) (xy 21.016674 45.55)
(xy 21.016674 47.05) (xy 21.049659 47.215827) (xy 21.143592 47.356408) (xy 21.284173 47.450341) (xy 21.45 47.483326)
(xy 23.29137 47.483326) (xy 21.937348 48.837348) (xy 21.780187 49.072554) (xy 21.780187 49.072555) (xy 21.725 49.35)
(xy 21.725 49.516674) (xy 21.45 49.516674) (xy 21.284173 49.549659) (xy 21.143592 49.643592) (xy 21.049659 49.784173)
(xy 21.016674 49.95) (xy 21.016674 51.45) (xy 21.049659 51.615827) (xy 21.143592 51.756408) (xy 21.284173 51.850341)
(xy 21.45 51.883326) (xy 23.375 51.883326) (xy 23.375 54) (xy 23.384515 54.047835) (xy 23.411612 54.088388)
(xy 23.452165 54.115485) (xy 23.5 54.125) (xy 28.249696 54.125) (xy 30.997348 56.872652) (xy 31.232554 57.029813)
(xy 31.278585 57.038969) (xy 31.51 57.085) (xy 31.782606 57.085) (xy 31.803592 57.116408) (xy 31.944173 57.210341)
(xy 32.11 57.243326) (xy 33.31 57.243326) (xy 33.402131 57.225) (xy 37.216674 57.225) (xy 37.216674 57.35)
(xy 37.249659 57.515827) (xy 37.343592 57.656408) (xy 37.484173 57.750341) (xy 37.65 57.783326) (xy 39.35 57.783326)
(xy 39.515827 57.750341) (xy 39.637106 57.669305) (xy 39.653369 57.708566) (xy 39.831435 57.886632) (xy 40.064089 57.983)
(xy 40.75275 57.983) (xy 40.911 57.82475) (xy 40.911 56.629) (xy 41.169 56.629) (xy 41.169 57.82475)
(xy 41.32725 57.983) (xy 42.015911 57.983) (xy 42.248565 57.886632) (xy 42.426631 57.708566) (xy 42.523 57.475912)
(xy 42.523 56.78725) (xy 42.36475 56.629) (xy 41.169 56.629) (xy 40.911 56.629) (xy 40.891 56.629)
(xy 40.891 56.371) (xy 40.911 56.371) (xy 40.911 55.17525) (xy 41.169 55.17525) (xy 41.169 56.371)
(xy 42.36475 56.371) (xy 42.523 56.21275) (xy 42.523 55.524088) (xy 42.426631 55.291434) (xy 42.248565 55.113368)
(xy 42.015911 55.017) (xy 41.32725 55.017) (xy 41.169 55.17525) (xy 40.911 55.17525) (xy 40.75275 55.017)
(xy 40.064089 55.017) (xy 39.831435 55.113368) (xy 39.653369 55.291434) (xy 39.637106 55.330695) (xy 39.515827 55.249659)
(xy 39.35 55.216674) (xy 39.225 55.216674) (xy 39.225 55.050304) (xy 40.150304 54.125) (xy 45.25 54.125)
(xy 45.297835 54.115485) (xy 45.338388 54.088388) (xy 46.951776 52.475) (xy 48 52.475) (xy 48.231415 52.428969)
(xy 48.277446 52.419813) (xy 48.512652 52.262652) (xy 49.762652 51.012652) (xy 49.919813 50.777446) (xy 49.949104 50.630187)
(xy 49.975 50.5) (xy 49.975 50.28725) (xy 51.717 50.28725) (xy 51.717 51.475912) (xy 51.813369 51.708566)
(xy 51.991435 51.886632) (xy 52.224089 51.983) (xy 53.93775 51.983) (xy 54.096 51.82475) (xy 54.096 50.129)
(xy 54.354 50.129) (xy 54.354 51.82475) (xy 54.51225 51.983) (xy 56.225911 51.983) (xy 56.458565 51.886632)
(xy 56.636631 51.708566) (xy 56.733 51.475912) (xy 56.733 50.28725) (xy 56.57475 50.129) (xy 54.354 50.129)
(xy 54.096 50.129) (xy 51.87525 50.129) (xy 51.717 50.28725) (xy 49.975 50.28725) (xy 49.975 48.524088)
last changes. Stream out
2017-09-09 23:11:00 +02:00
(xy 51.717 48.524088) (xy 51.717 49.71275) (xy 51.87525 49.871) (xy 54.096 49.871) (xy 54.096 48.17525)
(xy 54.354 48.17525) (xy 54.354 49.871) (xy 56.57475 49.871) (xy 56.733 49.71275) (xy 56.733 48.524088)
(xy 56.636631 48.291434) (xy 56.458565 48.113368) (xy 56.225911 48.017) (xy 54.51225 48.017) (xy 54.354 48.17525)
(xy 54.096 48.17525) (xy 53.93775 48.017) (xy 52.224089 48.017) (xy 51.991435 48.113368) (xy 51.813369 48.291434)
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 51.717 48.524088) (xy 49.975 48.524088) (xy 49.975 47.75) (xy 49.925522 47.501254) (xy 52.141333 45.285443)
(xy 53.746991 45.285443) (xy 53.809102 45.520407) (xy 54.309589 45.69571) (xy 54.839064 45.666141) (xy 55.190898 45.520407)
(xy 55.253009 45.285443) (xy 54.5 44.532434) (xy 53.746991 45.285443) (xy 52.141333 45.285443) (xy 53.160261 44.266515)
(xy 53.183859 44.689064) (xy 53.329593 45.040898) (xy 53.564557 45.103009) (xy 54.317566 44.35) (xy 54.682434 44.35)
(xy 55.435443 45.103009) (xy 55.670407 45.040898) (xy 55.84571 44.540411) (xy 55.816141 44.010936) (xy 55.670407 43.659102)
(xy 55.435443 43.596991) (xy 54.682434 44.35) (xy 54.317566 44.35) (xy 54.303424 44.335858) (xy 54.485858 44.153424)
(xy 54.5 44.167566) (xy 55.253009 43.414557) (xy 55.242552 43.375) (xy 57.125 43.375) (xy 57.125 52.625)
(xy 53.75 52.625) (xy 53.702165 52.634515) (xy 53.661612 52.661612) (xy 50.911612 55.411612) (xy 50.884515 55.452165)
(xy 50.875 55.5) (xy 50.875 61.375) (xy 14.625 61.375) (xy 14.625 52.933326) (xy 15.95 52.933326)
(xy 16.115827 52.900341) (xy 16.256408 52.806408) (xy 16.350341 52.665827) (xy 16.383326 52.5) (xy 16.383326 51.188138)
(xy 17.499835 51.188138) (xy 17.644159 51.537429) (xy 17.911165 51.804902) (xy 18.260204 51.949835) (xy 18.638138 51.950165)
(xy 18.987429 51.805841) (xy 19.254902 51.538835) (xy 19.399835 51.189796) (xy 19.400165 50.811862) (xy 19.255841 50.462571)
(xy 18.988835 50.195098) (xy 18.639796 50.050165) (xy 18.261862 50.049835) (xy 17.912571 50.194159) (xy 17.645098 50.461165)
(xy 17.500165 50.810204) (xy 17.499835 51.188138) (xy 16.383326 51.188138) (xy 16.383326 50.5) (xy 16.350341 50.334173)
(xy 16.256408 50.193592) (xy 16.115827 50.099659) (xy 15.95 50.066674) (xy 14.625 50.066674) (xy 14.625 46.933326)
(xy 15.95 46.933326) (xy 16.115827 46.900341) (xy 16.256408 46.806408) (xy 16.350341 46.665827) (xy 16.383326 46.5)
(xy 16.383326 46.188138) (xy 17.499835 46.188138) (xy 17.644159 46.537429) (xy 17.911165 46.804902) (xy 18.260204 46.949835)
(xy 18.638138 46.950165) (xy 18.987429 46.805841) (xy 19.254902 46.538835) (xy 19.399835 46.189796) (xy 19.400165 45.811862)
(xy 19.255841 45.462571) (xy 18.988835 45.195098) (xy 18.639796 45.050165) (xy 18.261862 45.049835) (xy 17.912571 45.194159)
(xy 17.645098 45.461165) (xy 17.500165 45.810204) (xy 17.499835 46.188138) (xy 16.383326 46.188138) (xy 16.383326 44.5)
(xy 16.350341 44.334173) (xy 16.256408 44.193592) (xy 16.115827 44.099659) (xy 15.95 44.066674) (xy 14.625 44.066674)
(xy 14.625 38.78725) (xy 17.7134 38.78725) (xy 17.7134 40.375912) (xy 17.809769 40.608566) (xy 17.987835 40.786632)
(xy 18.220489 40.883) (xy 19.80915 40.883) (xy 19.9674 40.72475) (xy 19.9674 38.629) (xy 20.2254 38.629)
(xy 20.2254 40.72475) (xy 20.38365 40.883) (xy 21.972311 40.883) (xy 22.204965 40.786632) (xy 22.383031 40.608566)
(xy 22.4794 40.375912) (xy 22.4794 38.78725) (xy 22.32115 38.629) (xy 20.2254 38.629) (xy 19.9674 38.629)
(xy 17.87165 38.629) (xy 17.7134 38.78725) (xy 14.625 38.78725) (xy 14.625 35.625) (xy 19.317 35.625)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
)
(zone (net 1) (net_name Earth) (layer F.Cu) (tstamp 0) (hatch edge 0.508)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
(connect_pads (clearance 0.3))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
(xy 13 22.25) (xy 23 22.25) (xy 23 33.5) (xy 25.5 33.5) (xy 25.5 36.25)
(xy 21.5 36.25) (xy 21.5 34.75) (xy 18.75 34.75) (xy 13 34.75)
)
)
(filled_polygon
(pts
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 17.863335 27.95009) (xy 17.893144 28.09995) (xy 17.863335 28.24981) (xy 17.863335 28.75019) (xy 17.893144 28.90005)
(xy 17.863335 29.04991) (xy 17.863335 29.38735) (xy 17.760373 29.490311) (xy 17.6637 29.7237) (xy 17.6637 29.816355)
(xy 17.82245 29.975105) (xy 18.245661 29.975105) (xy 18.2987 29.985655) (xy 20.59994 29.985655) (xy 20.652979 29.975105)
(xy 21.07619 29.975105) (xy 21.23494 29.816355) (xy 21.23494 29.7237) (xy 21.138267 29.490311) (xy 21.035305 29.38735)
(xy 21.035305 29.052) (xy 21.84299 29.052) (xy 21.842883 29.174073) (xy 21.945733 29.422989) (xy 22.13601 29.613598)
(xy 22.384746 29.716882) (xy 22.654073 29.717117) (xy 22.873 29.626658) (xy 22.873 33.5) (xy 22.882667 33.548601)
(xy 22.910197 33.589803) (xy 22.951399 33.617333) (xy 23 33.627) (xy 25.373 33.627) (xy 25.373 34.530051)
(xy 25.276309 34.49) (xy 24.83575 34.49) (xy 24.677 34.64875) (xy 24.677 35.373) (xy 24.697 35.373)
(xy 24.697 35.627) (xy 24.677 35.627) (xy 24.677 35.647) (xy 24.423 35.647) (xy 24.423 35.627)
(xy 24.403 35.627) (xy 24.403 35.373) (xy 24.423 35.373) (xy 24.423 34.64875) (xy 24.26425 34.49)
(xy 23.823691 34.49) (xy 23.590302 34.586673) (xy 23.5 34.676974) (xy 23.409698 34.586673) (xy 23.176309 34.49)
(xy 22.73575 34.49) (xy 22.577 34.64875) (xy 22.577 35.073) (xy 22.323 35.073) (xy 22.323 34.64875)
(xy 22.16425 34.49) (xy 21.723691 34.49) (xy 21.490302 34.586673) (xy 21.453975 34.623) (xy 17.177 34.623)
(xy 17.177 33.23583) (xy 17.46558 33.23583) (xy 17.46558 34.07588) (xy 17.562253 34.309269) (xy 17.740882 34.487897)
(xy 17.974271 34.58457) (xy 19.06451 34.58457) (xy 19.22326 34.42582) (xy 19.22326 33.07708) (xy 19.47726 33.07708)
(xy 19.47726 34.42582) (xy 19.63601 34.58457) (xy 20.726249 34.58457) (xy 20.959638 34.487897) (xy 21.138267 34.309269)
(xy 21.23494 34.07588) (xy 21.23494 33.23583) (xy 21.07619 33.07708) (xy 19.47726 33.07708) (xy 19.22326 33.07708)
(xy 17.62433 33.07708) (xy 17.46558 33.23583) (xy 17.177 33.23583) (xy 17.177 31.82428) (xy 17.46558 31.82428)
(xy 17.46558 32.66433) (xy 17.62433 32.82308) (xy 19.22326 32.82308) (xy 19.22326 31.47434) (xy 19.47726 31.47434)
(xy 19.47726 32.82308) (xy 21.07619 32.82308) (xy 21.23494 32.66433) (xy 21.23494 31.82428) (xy 21.138267 31.590891)
(xy 20.959638 31.412263) (xy 20.726249 31.31559) (xy 19.63601 31.31559) (xy 19.47726 31.47434) (xy 19.22326 31.47434)
(xy 19.06451 31.31559) (xy 17.974271 31.31559) (xy 17.740882 31.412263) (xy 17.562253 31.590891) (xy 17.46558 31.82428)
(xy 17.177 31.82428) (xy 17.177 31.749221) (xy 17.133647 31.531272) (xy 17.346794 31.443201) (xy 17.593595 31.196831)
(xy 17.727327 30.874767) (xy 17.72754 30.630824) (xy 17.760373 30.710089) (xy 17.939002 30.888717) (xy 18.172391 30.98539)
(xy 19.16357 30.98539) (xy 19.32232 30.82664) (xy 19.32232 30.225295) (xy 19.57632 30.225295) (xy 19.57632 30.82664)
(xy 19.73507 30.98539) (xy 20.726249 30.98539) (xy 20.959638 30.888717) (xy 21.138267 30.710089) (xy 21.23494 30.4767)
(xy 21.23494 30.384045) (xy 21.07619 30.225295) (xy 19.57632 30.225295) (xy 19.32232 30.225295) (xy 17.82245 30.225295)
(xy 17.667422 30.380323) (xy 17.594461 30.203746) (xy 17.348091 29.956945) (xy 17.026027 29.823213) (xy 16.677302 29.822908)
(xy 16.627 29.843693) (xy 16.627 29.031134) (xy 17.863335 27.794798)
Schematic and Layout update * Layout: minor improvements * Schematic: add tp for common anode of HID switches
2017-07-27 19:47:56 +02:00
)
)
(filled_polygon
(pts
redesign of some minor bugs
2017-10-03 18:12:33 +02:00
(xy 22.873 24.595904) (xy 21.121104 26.3478) (xy 20.911826 26.3478) (xy 20.90779 26.34176) (xy 20.766547 26.247385)
(xy 20.752004 26.244492) (xy 20.727531 26.22814) (xy 20.44932 26.1728) (xy 17.730205 26.1728) (xy 17.7302 26.172799)
(xy 17.727591 26.173318) (xy 17.727632 26.126762) (xy 17.594461 25.804466) (xy 17.348091 25.557665) (xy 17.026027 25.423933)
(xy 16.677302 25.423628) (xy 16.355006 25.556799) (xy 16.108205 25.803169) (xy 15.974473 26.125233) (xy 15.974168 26.473958)
(xy 16.107339 26.796254) (xy 16.353709 27.043055) (xy 16.498634 27.103233) (xy 15.385933 28.215933) (xy 15.22834 28.451789)
(xy 15.22834 28.45179) (xy 15.172999 28.73) (xy 15.173 28.730005) (xy 15.173 29.630187) (xy 15.05834 29.801789)
(xy 15.049158 29.847948) (xy 15.002999 30.08) (xy 15.003 30.080005) (xy 15.003 30.984121) (xy 15.023403 31.086694)
(xy 15.033009 31.190839) (xy 15.050864 31.224747) (xy 15.05834 31.262332) (xy 15.093926 31.31559) (xy 14.13691 31.31559)
(xy 13.97816 31.47434) (xy 13.97816 32.82308) (xy 13.99816 32.82308) (xy 13.99816 33.07708) (xy 13.97816 33.07708)
(xy 13.97816 34.42582) (xy 14.13691 34.58457) (xy 15.227149 34.58457) (xy 15.460538 34.487897) (xy 15.523 34.425435)
(xy 15.523 34.623) (xy 13.502 34.623) (xy 13.502 34.58457) (xy 13.56541 34.58457) (xy 13.72416 34.42582)
(xy 13.72416 33.07708) (xy 13.70416 33.07708) (xy 13.70416 32.82308) (xy 13.72416 32.82308) (xy 13.72416 31.47434)
(xy 13.56541 31.31559) (xy 13.502 31.31559) (xy 13.502 25.68441) (xy 13.56541 25.68441) (xy 13.72416 25.52566)
(xy 13.72416 24.17692) (xy 13.97816 24.17692) (xy 13.97816 25.52566) (xy 14.13691 25.68441) (xy 15.227149 25.68441)
(xy 15.460538 25.587737) (xy 15.639167 25.409109) (xy 15.73584 25.17572) (xy 15.73584 24.33567) (xy 17.46558 24.33567)
(xy 17.46558 25.17572) (xy 17.562253 25.409109) (xy 17.740882 25.587737) (xy 17.974271 25.68441) (xy 19.06451 25.68441)
(xy 19.22326 25.52566) (xy 19.22326 24.17692) (xy 19.47726 24.17692) (xy 19.47726 25.52566) (xy 19.63601 25.68441)
(xy 20.726249 25.68441) (xy 20.959638 25.587737) (xy 21.138267 25.409109) (xy 21.23494 25.17572) (xy 21.23494 24.33567)
(xy 21.07619 24.17692) (xy 19.47726 24.17692) (xy 19.22326 24.17692) (xy 17.62433 24.17692) (xy 17.46558 24.33567)
(xy 15.73584 24.33567) (xy 15.57709 24.17692) (xy 13.97816 24.17692) (xy 13.72416 24.17692) (xy 13.70416 24.17692)
(xy 13.70416 23.92292) (xy 13.72416 23.92292) (xy 13.72416 22.57418) (xy 13.97816 22.57418) (xy 13.97816 23.92292)
(xy 15.57709 23.92292) (xy 15.73584 23.76417) (xy 15.73584 22.92412) (xy 17.46558 22.92412) (xy 17.46558 23.76417)
(xy 17.62433 23.92292) (xy 19.22326 23.92292) (xy 19.22326 22.57418) (xy 19.47726 22.57418) (xy 19.47726 23.92292)
(xy 21.07619 23.92292) (xy 21.23494 23.76417) (xy 21.23494 22.92412) (xy 21.138267 22.690731) (xy 20.959638 22.512103)
(xy 20.726249 22.41543) (xy 19.63601 22.41543) (xy 19.47726 22.57418) (xy 19.22326 22.57418) (xy 19.06451 22.41543)
(xy 17.974271 22.41543) (xy 17.740882 22.512103) (xy 17.562253 22.690731) (xy 17.46558 22.92412) (xy 15.73584 22.92412)
(xy 15.639167 22.690731) (xy 15.460538 22.512103) (xy 15.227149 22.41543) (xy 14.13691 22.41543) (xy 13.97816 22.57418)
(xy 13.72416 22.57418) (xy 13.56541 22.41543) (xy 13.502 22.41543) (xy 13.502 22.377) (xy 22.873 22.377)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
)
(zone (net 0) (net_name "") (layer F.Cu) (tstamp 5994FC9B) (hatch edge 0.508)
(connect_pads (clearance 0.3))
(min_thickness 0.254)
(keepout (tracks allowed) (vias not_allowed) (copperpour not_allowed))
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(xy 101.4 41.49) (xy 105.89 41.5) (xy 105.89 45) (xy 101.4 44.99)
Improve layout: GND traces, thicker vias, better power supply for chips
2017-08-17 04:24:37 +02:00
)
)
)
(zone (net 0) (net_name "") (layer F.Cu) (tstamp 5994FCB0) (hatch edge 0.508)
(connect_pads (clearance 0.3))
(min_thickness 0.254)
(keepout (tracks allowed) (vias not_allowed) (copperpour not_allowed))
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
move jacks outwards to fit in case
2017-10-03 18:29:05 +02:00
(xy 102.18 51.03) (xy 102.18 54.53) (xy 105.61 54.53) (xy 105.61 51.03)
Finished first draft * Schematic complete * Layout complete
2017-07-26 20:29:25 +02:00
)
)
)
improve layout, reorder silkscreen
2017-08-28 22:11:02 +02:00
(zone (net 0) (net_name "") (layer F.Cu) (tstamp 0) (hatch edge 0.508)
(connect_pads (clearance 0.3))
(min_thickness 0.25)
(keepout (tracks allowed) (vias allowed) (copperpour not_allowed))
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 56.75 52.75) (xy 53.75 52.75) (xy 51 55.5) (xy 51 61.5) (xy 56.75 61.5)
(xy 56.75 61) (xy 52.25 56) (xy 53.75 54.25) (xy 54.75 54.75) (xy 56.25 56.25)
(xy 57.25 56.25)
)
)
)
Layouted first draft
2017-06-09 00:41:36 +02:00
)
Reference in New Issue Copy Permalink