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Add SMD SMA jack, Add TME micro SD slot, add schematic: AOxxx Transistors and TI regulator

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This commit is contained in:
Mario Hüttel 2019-01-16 22:49:11 +01:00
parent 96d3ad5cf4
commit 0b0b1c8c26
4 changed files with 163 additions and 10 deletions
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41
footprints/pretty/shimatta_rf.pretty/SMD-SMA.kicad_mod Normal file
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@ -0,0 +1,41 @@
(module SMD-SMA (layer F.Cu) (tedit 5C01D97A)
(fp_text reference REF** (at -8.85 -2.85) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value SMD-SMA (at -5.8 -0.95) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd circle (at 0 0) (size 2.05 2.05) (layers F.Cu F.Paste F.Mask))
(pad 2 smd custom (at 2.75 -2.75) (size 1 1) (layers F.Cu F.Paste F.Mask)
(zone_connect 0)
(options (clearance outline) (anchor rect))
(primitives
(gr_poly (pts
(xy -1.22 -1.13) (xy 1.22 -1.13) (xy 1.22 2.75) (xy -0.195 2.75) (xy -0.195 0.75)
(xy -1.22 0.75)) (width 0))
))
(pad 2 smd custom (at -2.75 2.75 180) (size 1 1) (layers F.Cu F.Paste F.Mask)
(zone_connect 0)
(options (clearance outline) (anchor rect))
(primitives
(gr_poly (pts
(xy -1.22 -1.13) (xy 1.22 -1.13) (xy 1.22 2.75) (xy -0.195 2.75) (xy -0.195 0.75)
(xy -1.22 0.75)) (width 0))
))
(pad 2 smd custom (at -2.75 -2.75) (size 1 1) (layers F.Cu F.Paste F.Mask)
(zone_connect 0)
(options (clearance outline) (anchor rect))
(primitives
(gr_poly (pts
(xy 1.22 -1.13) (xy -1.22 -1.13) (xy -1.22 2.75) (xy 0.195 2.75) (xy 0.195 0.75)
(xy 1.22 0.75)) (width 0))
))
(pad 2 smd custom (at 2.75 2.75 180) (size 1 1) (layers F.Cu F.Paste F.Mask)
(zone_connect 0)
(options (clearance outline) (anchor rect))
(primitives
(gr_poly (pts
(xy 1.22 -1.13) (xy -1.22 -1.13) (xy -1.22 2.75) (xy 0.195 2.75) (xy 0.195 0.75)
(xy 1.22 0.75)) (width 0))
))
)

46
footprints/pretty/shimatta_smd.pretty/MCC-SDMICRO3-112J-TDAR-R01.kicad_mod Normal file
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@ -0,0 +1,46 @@
(module MCC-SDMICRO3-112J-TDAR-R01 (layer F.Cu) (tedit 5C3FA672)
(fp_text reference REF** (at 5.5 5) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value MCC-SDMICRO3-112J-TDAR-R01 (at 7.25 -2.25) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 9.6 6) (end 0.6 6) (layer F.CrtYd) (width 0.15))
(fp_line (start 0.6 6) (end 0.6 4) (layer F.CrtYd) (width 0.15))
(fp_line (start 0.6 4) (end 9.6 4) (layer F.CrtYd) (width 0.15))
(fp_line (start 9.6 4) (end 9.6 6) (layer F.CrtYd) (width 0.15))
(fp_line (start -2.25 11.25) (end -2.25 -1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 -1.25) (end -2.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 -1.5) (end 15.25 -1.5) (layer F.SilkS) (width 0.15))
(fp_line (start 15.25 -1.5) (end 15.25 14.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 14.5) (end -2.25 11.25) (layer F.SilkS) (width 0.15))
(fp_line (start -0.4 14.5) (end 10.6 14.5) (layer F.SilkS) (width 0.15))
(fp_line (start 10.6 14.5) (end 10.6 8.9) (layer F.SilkS) (width 0.15))
(fp_line (start 10.6 8.9) (end 10 8.55) (layer F.SilkS) (width 0.15))
(fp_line (start 10 8.55) (end 10.6 8.1) (layer F.SilkS) (width 0.15))
(fp_line (start 10.6 8.1) (end 10.6 7.1) (layer F.SilkS) (width 0.15))
(fp_line (start 10.6 7.1) (end 10 6.55) (layer F.SilkS) (width 0.15))
(fp_line (start 10 6.55) (end 10 2.75) (layer F.SilkS) (width 0.15))
(fp_line (start 10 2.75) (end 0.75 2.75) (layer F.SilkS) (width 0.15))
(fp_line (start 0.75 2.75) (end -0.4 2.75) (layer F.SilkS) (width 0.15))
(fp_line (start -0.4 2.75) (end -0.4 14.5) (layer F.SilkS) (width 0.15))
(fp_line (start -2.25 -1.5) (end 15.25 -1.5) (layer F.CrtYd) (width 0.15))
(fp_line (start 15.25 -1.5) (end 15.25 14.5) (layer F.CrtYd) (width 0.15))
(fp_line (start 15.25 14.5) (end -2.25 14.5) (layer F.CrtYd) (width 0.15))
(fp_line (start -2.25 14.5) (end -2.25 -1.5) (layer F.CrtYd) (width 0.15))
(pad 9 smd rect (at 0 0) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask))
(pad 8 smd rect (at 1.1 0) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask))
(pad 7 smd rect (at 2.2 0) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask))
(pad 6 smd rect (at 3.3 0) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask))
(pad 5 smd rect (at 4.4 0) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask))
(pad 4 smd rect (at 5.5 0) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask))
(pad 3 smd rect (at 6.6 0) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask))
(pad 2 smd rect (at 7.7 0) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask))
(pad 1 smd rect (at 8.8 0) (size 0.7 1.6) (layers F.Cu F.Paste F.Mask))
(pad 10 smd rect (at 13.4 0.5) (size 1.6 1.4) (layers F.Cu F.Paste F.Mask))
(pad 13 smd rect (at -1.2 0.5) (size 1.2 1.4) (layers F.Cu F.Paste F.Mask))
(pad 12 smd rect (at -1.2 10.1) (size 1.2 2.2) (layers F.Cu F.Paste F.Mask))
(pad "" np_thru_hole circle (at 1.6 10.5) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 9.6 10.5) (size 0.5 0.5) (drill 0.5) (layers *.Cu *.Mask))
(pad 11 smd rect (at 14.3 10.1) (size 1.2 2.2) (layers F.Cu F.Paste F.Mask))
)

41
schematics/shimatta_regulators.lib
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@ -1,4 +1,4 @@
EESchema-LIBRARY Version 2.3
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# LM2596
@ -32,7 +32,16 @@ F3 "" 0 0 60 H I C CNN
DRAW
S 0 0 1000 -1200 0 1 0 F
X SVin 1 -200 -50 200 R 50 50 1 1 W
X SGND 10 600 -1400 200 U 50 50 1 1 W
X SW 12 1200 -50 200 L 50 50 1 1 w
X SW 14 1200 -150 200 L 50 50 1 1 w
X PVIN 15 -200 -350 200 R 50 50 1 1 W
X PVIN 16 -200 -250 200 R 50 50 1 1 W
X SW 17 1200 -250 200 L 50 50 1 1 w
X SW 19 1200 -350 200 L 50 50 1 1 w
X RUN 2 -200 -700 200 R 50 50 1 1 I
X PVIN_DRV 20 -200 -150 200 R 50 50 1 1 W
X PGND-Pad 21 500 -1400 200 U 50 50 1 1 W
X PGOOD 3 -200 -500 200 R 50 50 1 1 C
X MODE 4 -200 -800 200 R 50 50 1 1 I
X VFB 5 -200 -900 200 R 50 50 1 1 I
@ -40,15 +49,6 @@ X ITH 6 -200 -1000 200 R 50 50 1 1 I
X TRACK/SS 7 -200 -600 200 R 50 50 1 1 I
X DDR 8 1200 -1050 200 L 50 50 1 1 I
X RT/SYNC 9 -200 -1100 200 R 50 50 1 1 I
X SGND 10 600 -1400 200 U 50 50 1 1 W
X PVIN_DRV 20 -200 -150 200 R 50 50 1 1 W
X PGND-Pad 21 500 -1400 200 U 50 50 1 1 W
X SW 12 1200 -50 200 L 50 50 1 1 w
X SW 14 1200 -150 200 L 50 50 1 1 w
X PVIN 15 -200 -350 200 R 50 50 1 1 W
X PVIN 16 -200 -250 200 R 50 50 1 1 W
X SW 17 1200 -250 200 L 50 50 1 1 w
X SW 19 1200 -350 200 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
@ -89,4 +89,25 @@ X VOUT+ 6 900 -50 200 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
# TPS54227
#
DEF TPS54227 U 0 40 Y Y 1 F N
F0 "U" 500 50 50 H V C CNN
F1 "TPS54227" 200 50 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
S 0 0 650 -750 0 1 0 f
X EN 1 -100 -100 100 R 50 50 1 1 I
X VFB 2 -100 -200 100 R 50 50 1 1 I
X VREG5 3 -100 -300 100 R 50 50 1 1 I
X GND 5 250 -850 100 U 50 50 1 1 W
X VBST 7 750 -200 100 L 50 50 1 1 W
X VIN 8 750 -100 100 L 50 50 1 1 W
X Pad 9 400 -850 100 U 50 50 1 1 W
X SS ~ -100 -450 100 R 50 50 1 1 I
X SW ~ 750 -300 100 L 50 50 1 1 w
ENDDRAW
ENDDEF
#
#End Library

45
schematics/shimatta_transistors.lib
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@ -37,4 +37,49 @@ X D 8 550 -350 100 L 50 50 1 1 I
ENDDRAW
ENDDEF
#
# AO4409
#
DEF AO4409 Q 0 40 Y Y 1 F N
F0 "Q" 50 50 50 H V C CNN
F1 "AO4409" 350 50 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
C 410 -330 10 0 1 0 F
S 0 0 550 -900 0 1 0 f
P 2 0 1 0 0 -400 300 -400 N
P 2 0 1 0 300 -480 300 -490 N
P 2 0 1 0 300 -450 300 -480 N
P 2 0 1 0 300 -350 300 -320 N
P 2 0 1 0 300 -320 300 -310 N
P 2 0 1 0 320 -480 320 -490 N
P 2 0 1 0 320 -480 320 -450 N
P 2 0 1 0 320 -400 380 -400 N
P 2 0 1 0 320 -380 320 -420 N
P 2 0 1 0 320 -330 410 -330 N
P 2 0 1 0 320 -320 320 -350 N
P 2 0 1 0 320 -320 320 -310 N
P 2 0 1 0 340 -420 340 -380 N
P 2 0 1 0 340 -380 380 -400 N
P 2 0 1 0 380 -400 340 -420 N
P 2 0 1 0 380 -400 410 -400 N
P 2 0 1 0 520 -600 550 -600 N
P 2 0 1 0 520 -200 550 -200 N
P 3 0 1 0 300 -350 300 -400 300 -450 N
P 3 0 1 0 410 -400 410 -300 550 -300 N
P 3 0 1 0 520 -510 520 -500 550 -500 N
P 3 0 1 0 520 -300 520 -100 550 -100 N
P 3 0 1 0 550 -700 530 -700 520 -700 N
P 4 0 1 0 320 -470 520 -470 520 -800 550 -800 N
X S 1 650 -100 100 L 50 50 1 1 I
X S 2 650 -200 100 L 50 50 1 1 I
X S 3 650 -300 100 L 50 50 1 1 I
X G 4 -100 -400 100 R 50 50 1 1 I
X D 5 650 -500 100 L 50 50 1 1 I
X D 6 650 -600 100 L 50 50 1 1 I
X D 7 650 -700 100 L 50 50 1 1 I
X D 8 650 -800 100 L 50 50 1 1 I
ENDDRAW
ENDDEF
#
#End Library