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Add Lattice FPGA and ADAU1966

This commit is contained in:
Mario Hüttel 2018-06-08 23:16:25 +02:00
parent 30e0d81f8f
commit 452aa34e98
4 changed files with 168 additions and 0 deletions
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4
README.MD
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@ -7,8 +7,12 @@ Libraries for KiCad.
## altera
* EP4CE6E22C8N
## analog
* ADAU1966
## lattice
* LFXP2-5E-6TN144C
* LCMXO2-1200HC-4SG32C
## HDMI
* ADV7513

94
schematics/shimatta_analog.lib
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@ -1,6 +1,100 @@
EESchema-LIBRARY Version 2.4
#encoding utf-8
#
# ADAU1966
#
DEF ADAU1966 U 0 40 Y Y 3 L N
F0 "U" 650 50 50 H V C CNN
F1 "ADAU1966" 200 50 50 H V C CNN
F2 "" 0 100 50 H I C CNN
F3 "" 0 100 50 H I C CNN
DRAW
S 0 0 850 -2250 1 1 0 f
S 0 0 1300 -1500 2 1 0 f
S 0 0 850 -2000 3 1 0 f
X DAC_BIAS3 1 -100 -1700 100 R 50 50 1 1 I
X AVDD4 12 -100 -400 100 R 50 50 1 1 W
X AGND4 13 950 -400 100 L 50 50 1 1 W
X PLLGND 14 950 -600 100 L 50 50 1 1 W
X LF 15 -100 -850 100 R 50 50 1 1 O
X PLLVDD 16 -100 -600 100 R 50 50 1 1 W
X DAC_BIAS4 2 -100 -1800 100 R 50 50 1 1 I
X DVDD 20 -100 -1050 100 R 50 50 1 1 W
X DGND 21 950 -1050 100 L 50 50 1 1 W
X IOVDD 22 -100 -1450 100 R 50 50 1 1 W
X VSENSE 23 950 -1900 100 L 50 50 1 1 I
X VDRIVE 24 950 -1800 100 L 50 50 1 1 O
X VSUPPLY 25 950 -1700 100 L 50 50 1 1 I
X DGND 26 950 -1150 100 L 50 50 1 1 W
X DVDD 29 -100 -1150 100 R 50 50 1 1 W
X AVDD3 3 -100 -300 100 R 50 50 1 1 W
X DGND 30 950 -1250 100 L 50 50 1 1 W
X IOVDD 39 -100 -1550 100 R 50 50 1 1 W
X DGND 40 950 -1350 100 L 50 50 1 1 W
X DVDD 41 -100 -1250 100 R 50 50 1 1 W
X AGND1 48 950 -100 100 L 50 50 1 1 W
X AVDD1 49 -100 -100 100 R 50 50 1 1 W
X AVDD2 58 -100 -200 100 R 50 50 1 1 W
X DAC_BIAS1 59 -100 -1900 100 R 50 50 1 1 I
X DAC_BIAS2 60 -100 -2000 100 R 50 50 1 1 I
X AGND2 61 950 -200 100 L 50 50 1 1 W
X CM 62 950 -2200 100 L 50 50 1 1 O
X TS_REF 63 -100 -2200 100 R 50 50 1 1 O
X AGND3 80 950 -300 100 L 50 50 1 1 W
X MCLKI/XTALI 17 -100 -100 100 R 50 50 2 1 I
X XTALO 18 -100 -200 100 R 50 50 2 1 O
X MCLKO 19 -100 -300 100 R 50 50 2 1 O
X DBCLK 27 -100 -450 100 R 50 50 2 1 B C
X DLRCLK 28 -100 -550 100 R 50 50 2 1 B C
X DSDATA8/SA 31 -100 -750 100 R 50 50 2 1 I
X DSDATA7/SA 32 -100 -850 100 R 50 50 2 1 I
X DSDATA6 33 -100 -950 100 R 50 50 2 1 I
X DSDATA5 34 -100 -1050 100 R 50 50 2 1 I
X DSDATA4 35 -100 -1150 100 R 50 50 2 1 I
X DSDATA3 36 -100 -1250 100 R 50 50 2 1 I
X DSDATA2 37 -100 -1350 100 R 50 50 2 1 I
X DSDATA1 38 -100 -1450 100 R 50 50 2 1 I
X CDATA/ADDR1/SA 42 1400 -800 100 L 50 50 2 1 I
X COUT/SDA/SA 43 1400 -700 100 L 50 50 2 1 B
X CCLK/SCL/SA 44 1400 -600 100 L 50 50 2 1 I C
X ~CLATCH~/ADDR0/SA 45 1400 -500 100 L 50 50 2 1 I
X SA_MODE 46 1400 -200 100 L 50 50 2 1 I
X PU/~RST~ 47 1400 -100 100 L 50 50 2 1 I
X DAC16+ 10 950 -100 100 L 50 50 3 1 O
X DAC16- 11 950 -200 100 L 50 50 3 1 O
X DAC13+ 4 950 -850 100 L 50 50 3 1 O
X DAC13- 5 950 -950 100 L 50 50 3 1 O
X DAC1+ 50 -100 -100 100 R 50 50 3 1 O
X DAC1- 51 -100 -200 100 R 50 50 3 1 O
X DAC2+ 52 -100 -350 100 R 50 50 3 1 O
X DAC2- 53 -100 -450 100 R 50 50 3 1 O
X DAC3+ 54 -100 -600 100 R 50 50 3 1 O
X DAC3- 55 -100 -700 100 R 50 50 3 1 O
X DAC4+ 56 -100 -850 100 R 50 50 3 1 O
X DAC4- 57 -100 -950 100 R 50 50 3 1 O
X DAC14+ 6 950 -600 100 L 50 50 3 1 O
X DAC5+ 64 -100 -1100 100 R 50 50 3 1 O
X DAC5- 65 -100 -1200 100 R 50 50 3 1 O
X DAC6+ 66 -100 -1350 100 R 50 50 3 1 O
X DAC6- 67 -100 -1450 100 R 50 50 3 1 O
X DAC7+ 68 -100 -1600 100 R 50 50 3 1 O
X DAC7- 69 -100 -1700 100 R 50 50 3 1 O
X DAC14- 7 950 -700 100 L 50 50 3 1 O
X DAC8+ 70 -100 -1850 100 R 50 50 3 1 O
X DAC8- 71 -100 -1950 100 R 50 50 3 1 O
X DAC9+ 72 950 -1850 100 L 50 50 3 1 O
X DAC9- 73 950 -1950 100 L 50 50 3 1 O
X DAC10+ 74 950 -1600 100 L 50 50 3 1 O
X DAC10- 75 950 -1700 100 L 50 50 3 1 O
X DAC11+ 76 950 -1350 100 L 50 50 3 1 O
X DAC11- 77 950 -1450 100 L 50 50 3 1 O
X DAC12+ 78 950 -1100 100 L 50 50 3 1 O
X DAC12- 79 950 -1200 100 L 50 50 3 1 O
X DAC15+ 8 950 -350 100 L 50 50 3 1 O
X DAC15- 9 950 -450 100 L 50 50 3 1 O
ENDDRAW
ENDDEF
#
# TSU101
#
DEF TSU101 U 0 40 Y Y 1 F N

6
schematics/shimatta_lattice.dcm
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@ -1,5 +1,11 @@
EESchema-DOCLIB Version 2.0
#
$CMP LCMXO2-1200HC-4SG32C
D Lattice MachXO2 FPGA
K Lattice MachXO2 FPGA
F http://www.latticesemi.com/~/media/LatticeSemi/Documents/DataSheets/MachXO23/MachXO2FamilyDataSheet.pdf?document_id=38834
$ENDCMP
#
$CMP LFXP2-5E-6TN144C
D Lattice XP2-5E FPGA (TQFP144, Speedgrade -6)
K Lattice XP2 FPGA PLD

64
schematics/shimatta_lattice.lib
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@ -1,6 +1,70 @@
EESchema-LIBRARY Version 2.3
#encoding utf-8
#
# LCMXO2-1200HC-4SG32C
#
DEF LCMXO2-1200HC-4SG32C U 0 40 Y Y 5 L N
F0 "U" 400 50 60 H V C CNN
F1 "LCMXO2-1200HC-4SG32C" 400 150 60 H V C CNN
F2 "" 250 -700 60 H I C CNN
F3 "" 250 -700 60 H I C CNN
ALIAS LCMXO2-1200HC-5SG32C LCMXO2-1200HC-6SG32C
$FPLIST
QFN32
QFN-32
$ENDFPLIST
DRAW
T 0 400 -50 60 0 1 1 FPGA~Power Normal 0 C C
T 0 400 -50 60 0 2 1 Bank~0 Normal 0 C C
T 0 400 -50 60 0 3 1 Bank~1 Normal 0 C C
T 0 400 -50 60 0 4 1 Bank~2 Normal 0 C C
T 0 400 -50 60 0 5 1 Bank~3 Normal 0 C C
S 0 -100 800 -550 1 1 0 f
S 0 0 800 -100 1 1 0 f
S 0 -100 800 -1350 2 1 0 f
S 800 0 0 -100 2 1 0 f
S 0 -100 800 -550 3 1 0 f
S 0 0 800 -100 3 1 0 f
S 0 -100 800 -1350 4 1 0 f
S 0 0 800 -100 4 1 0 f
S 0 -100 800 -550 5 1 0 f
S 0 0 800 -100 5 1 0 f
X VCC 18 -200 -300 200 R 50 50 1 1 W
X VCC 2 -200 -200 200 R 50 50 1 1 W
X GND 22 1000 -300 200 L 50 50 1 1 W
X GND 3 1000 -200 200 L 50 50 1 1 W
X PAD 33 -200 -450 200 R 50 50 1 1 U
X PT10C_TDO 1 -200 -1000 200 R 50 50 2 1 B
X PT17D_DONE 23 -200 -300 200 R 50 50 2 1 B
X VCCIO0 24 -200 -1150 200 R 50 50 2 1 W
X PT15D_PROGRAMN 25 -200 -200 200 R 50 50 2 1 B I
X PT15C_JTAGENB 26 -200 -400 200 R 50 50 2 1 B
X PT12D_SDAPCLKC0 27 -200 -500 200 R 50 50 2 1 B
X PT12C_SCLPCLKT0 28 -200 -600 200 R 50 50 2 1 B
X PT11D_TMS 29 -200 -700 200 R 50 50 2 1 B
X PT11C_TCK 30 -200 -800 200 R 50 50 2 1 B
X VCCIO0 31 -200 -1250 200 R 50 50 2 1 W
X PT10D_TDI 32 -200 -900 200 R 50 50 2 1 B
X VCCIO1 19 -200 -450 200 R 50 50 3 1 W
X PR5D_PCLKC1 20 -200 -200 200 R 50 50 3 1 B
X PR5C_PCLKT1 21 -200 -300 200 R 50 50 3 1 B
X PB6D_SOSPISO 10 -200 -400 200 R 50 50 4 1 B
X PB9A_PCLKT20 11 -200 -500 200 R 50 50 4 1 B
X PB9B_PCLKC20 12 -200 -600 200 R 50 50 4 1 B
X PB11A_PCLKT21 13 -200 -700 200 R 50 50 4 1 B
X PB11B_PCLKC21 14 -200 -800 200 R 50 50 4 1 B
X VCCIO2 15 -200 -1150 200 R 50 50 4 1 W
X PB20C_SN 16 -200 -900 200 R 50 50 4 1 B
X PB20D_SISPI 17 -200 -1000 200 R 50 50 4 1 B
X VCCIO2 7 -200 -1250 200 R 50 50 4 1 W
X PB4C_CSSPIN 8 -200 -200 200 R 50 50 4 1 B
X PB6C_MCLKCCLK 9 -200 -300 200 R 50 50 4 1 B
X PL9A_PCLKT3 4 -200 -200 200 R 50 50 5 1 B
X PL9B_PCLKC3 5 -200 -300 200 R 50 50 5 1 B
X VCCIO3 6 -200 -450 200 R 50 50 5 1 W
ENDDRAW
ENDDEF
#
# LFXP2-5E-6TN144C
#
DEF LFXP2-5E-6TN144C U 0 40 Y Y 6 L N