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Transistors, altera devs, and some regulator foo. Aditionally a Lumberg footprint

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This commit is contained in:
Mario Hüttel 2019-05-11 22:13:06 +02:00
parent 0b0b1c8c26
commit 7065e4eb22
4 changed files with 225 additions and 2 deletions
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29
footprints/pretty/shimatta_tht.pretty/Lumberg-1503-RST.kicad_mod Normal file
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@ -0,0 +1,29 @@
(module Lumberg-1503-RST (layer F.Cu) (tedit 5C4E04AE)
(fp_text reference J2 (at 0.88 -4.46) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Jack_3.5mm_3pin (at 0 4.75) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 9.75 2.5) (end 9.75 0) (layer F.SilkS) (width 0.15))
(fp_line (start -0.75 3) (end -2.5 3) (layer F.SilkS) (width 0.15))
(fp_line (start -0.75 3) (end -0.5 3) (layer F.SilkS) (width 0.15))
(fp_line (start 2.5 3) (end 1 3) (layer F.SilkS) (width 0.15))
(fp_line (start 1 -3) (end 2.5 -3) (layer F.SilkS) (width 0.15))
(fp_line (start -0.5 -3) (end -2.5 -3) (layer F.SilkS) (width 0.15))
(fp_line (start -4.25 0.25) (end -4.25 1.25) (layer F.SilkS) (width 0.15))
(fp_line (start -4.25 0.25) (end -4.25 -1.25) (layer F.SilkS) (width 0.15))
(fp_line (start 7.25 -3) (end 5 -3) (layer F.SilkS) (width 0.15))
(fp_line (start 7.25 0.75) (end 7.25 -3) (layer F.SilkS) (width 0.15))
(fp_line (start 7.25 3) (end 5 3) (layer F.SilkS) (width 0.15))
(fp_line (start 7.25 3) (end 7.25 0.75) (layer F.SilkS) (width 0.15))
(fp_line (start 7.25 2.5) (end 9.75 2.5) (layer F.SilkS) (width 0.15))
(fp_line (start 9.75 0) (end 9.75 -2.5) (layer F.SilkS) (width 0.15))
(fp_line (start 9.75 -2.5) (end 7.25 -2.5) (layer F.SilkS) (width 0.15))
(pad T thru_hole rect (at 3.75 -3) (size 2 2) (drill oval 1.3 1) (layers *.Cu *.Mask))
(pad T thru_hole rect (at 3.75 3) (size 2 2) (drill oval 1.3 1) (layers *.Cu *.Mask))
(pad S thru_hole rect (at -3.75 -2.2) (size 2 1.5) (drill oval 1.3 0.8) (layers *.Cu *.Mask))
(pad R thru_hole rect (at -3.75 2.2) (size 2 1.5) (drill oval 1.3 0.8) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 0.25 -2.5) (size 1.05 1.05) (drill 1.05) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 0.25 2.5) (size 1.05 1.05) (drill 1.05) (layers *.Cu *.Mask))
)

192
schematics/shimatta_altera.lib
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@ -1,6 +1,198 @@
EESchema-LIBRARY Version 2.4 EESchema-LIBRARY Version 2.4
#encoding utf-8 #encoding utf-8
# #
# 10M04SCE144
#
DEF 10M04SCE144 U 0 40 Y Y 11 L N
F0 "U" 100 50 50 H V C CNN
F1 "10M04SCE144" 300 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN
DRAW
T 0 550 -50 50 0 3 0 BANK1A Normal 0 C C
T 900 700 -550 50 0 3 0 "LOW SPEED" Normal 0 C C
T 0 600 -50 50 0 4 0 BANK1B Normal 0 C C
T 900 1000 -700 50 0 4 0 "LOW SPEED" Normal 0 C C
T 0 650 -50 50 0 5 0 BANK2 Normal 0 C C
T 0 1100 -600 50 0 5 0 "HIGH SPEED" Normal 0 C C
T 0 700 -50 50 0 6 0 BANK3 Normal 0 C C
T 900 1050 -1350 50 0 6 0 "HIGH SPEED" Normal 0 C C
T 0 700 -50 50 0 7 0 BANK4 Normal 0 C C
T 0 500 -50 50 0 8 0 BANK5 Normal 0 C C
T 0 650 -50 50 0 9 0 BANK6 Normal 0 C C
T 0 650 -50 50 0 10 0 BANK7 Normal 0 C C
T 0 950 -50 50 0 11 0 BANK8 Normal 0 C C
S 0 0 1150 -1200 4 0 0 f
S 0 0 1350 -900 5 0 0 f
S 0 0 1350 -1950 6 0 0 f
S 0 0 1300 -850 7 0 0 f
S 0 0 1000 -1350 8 0 0 f
S 0 0 1300 -1650 9 0 0 f
S 0 0 1300 -850 10 0 0 f
S 0 0 1750 -1850 11 0 0 f
S 0 0 450 -1500 1 1 0 f
S 0 0 450 -1750 2 1 0 f
S 0 0 1050 -950 3 1 0 f
P 2 4 0 0 0 -100 1150 -100 N
P 2 5 0 0 0 -100 1350 -100 N
P 2 6 0 0 0 -100 1350 -100 N
P 2 7 0 0 0 -100 1300 -100 N
P 2 8 0 0 0 -100 1000 -100 N
P 2 9 0 0 0 -100 1300 -100 N
P 2 10 0 0 0 -100 1300 -100 N
P 2 11 0 0 0 -100 1750 -100 N
P 2 2 1 0 0 -1050 450 -1050 N
P 2 2 1 0 0 -1000 450 -1000 N
P 4 2 1 0 300 -1300 350 -1300 350 -1400 300 -1400 N
P 2 3 1 0 0 -100 1050 -100 N
X GND 104 -200 -1350 200 R 50 50 1 1 W
X GND 116 -200 -1250 200 R 50 50 1 1 W
X GND 125 -200 -1150 200 R 50 50 1 1 W
X GND 133 -200 -1050 200 R 50 50 1 1 W
X GND 137 -200 -950 200 R 50 50 1 1 W
X GND 142 -200 -850 200 R 50 50 1 1 W
X GND-PAD 145 -200 -1450 200 R 50 50 1 1 W
X GND 3 -200 -50 200 R 50 50 1 1 W
X GND 4 -200 -150 200 R 50 50 1 1 W
X GND 42 -200 -750 200 R 50 50 1 1 W
X GND 53 -200 -650 200 R 50 50 1 1 W
X GND 63 -200 -550 200 R 50 50 1 1 W
X GND 68 -200 -450 200 R 50 50 1 1 W
X GND 83 -200 -350 200 R 50 50 1 1 W
X GND 95 -200 -250 200 R 50 50 1 1 W
X VCC_ONE 1 -200 -950 200 R 50 50 2 1 W
X VCCA3 107 -200 -1400 200 R 50 50 2 1 W
X VCC_ONE 108 -200 -850 200 R 50 50 2 1 W
X VCC_ONE 109 -200 -750 200 R 50 50 2 1 W
X VCC_ONE 115 -200 -650 200 R 50 50 2 1 W
X VCCA4 143 -200 -1500 200 R 50 50 2 1 W
X VCC_ONE 144 -200 -550 200 R 50 50 2 1 W
X VCCA6 2 -200 -1700 200 R 50 50 2 1 W
X VCCA2 34 -200 -1200 200 R 50 50 2 1 W
X VCCA1 35 -200 -1100 200 R 50 50 2 1 W
X VCC_ONE 36 -200 -450 200 R 50 50 2 1 W
X VCC_ONE 37 -200 -350 200 R 50 50 2 1 W
X VCCA3 5 -200 -1300 200 R 50 50 2 1 W
X VCC_ONE 51 -200 -250 200 R 50 50 2 1 W
X VCCA5 71 -200 -1600 200 R 50 50 2 1 W
X VCC_ONE 72 -200 -150 200 R 50 50 2 1 W
X VCC_ONE 73 -200 -50 200 R 50 50 2 1 W
X DIFFIO_RX_L3p 10 -200 -500 200 R 50 50 3 1 B
X DIFFIO_RX_L5n 11 -200 -600 200 R 50 50 3 1 B
X DIFFIO_RX_L5p 12 -200 -700 200 R 50 50 3 1 B
X DIFFIO_RX_L7n 13 -200 -800 200 R 50 50 3 1 B
X DIFFIO_RX_L7p 14 -200 -900 200 R 50 50 3 1 B
X DIFFIO_RX_L1n 6 -200 -200 200 R 50 50 3 1 B
X DIFFIO_RX_L1p 7 -200 -300 200 R 50 50 3 1 B
X DIFFIO_RX_L3n 8 -200 -400 200 R 50 50 3 1 B
X VCCIO1A 9 1250 -200 200 L 50 50 3 1 W
X IO/JTAGEN 15 -200 -200 200 R 50 50 4 1 B
X TMS/DIFFIO_RX_L11n 16 -200 -300 200 R 50 50 4 1 B
X IO/VREFB1N0 17 -200 -400 200 R 50 50 4 1 B
X TCK/DIFFIO_RX_L11p 18 -200 -500 200 R 50 50 4 1 B
X TDI/DIFFIO_RX_L12n 19 -200 -600 200 R 50 50 4 1 B
X TDO/DIFFIO_RX_L12p 20 -200 -700 200 R 50 50 4 1 B
X DIFFIO_RX_L14n 21 -200 -800 200 R 50 50 4 1 B
X DIFFIO_RX_L14p 22 -200 -900 200 R 50 50 4 1 B
X VCCIO1B 23 1350 -200 200 L 50 50 4 1 W
X DIFFIO_RX_L16n 24 -200 -1000 200 R 50 50 4 1 B
X DIFFIO_RX_L14p 25 -200 -1100 200 R 50 50 4 1 B
X CLK0n/DIFFIO_RX_L18n 26 -200 -200 200 R 50 50 5 1 B
X CLK0p/DIFFIO_RX_L18p 27 -200 -300 200 R 50 50 5 1 B
X CLK1n/DIFFIO_RX_L20n 28 -200 -400 200 R 50 50 5 1 B
X CLK1p/DIFFIO_RX_L20p 29 -200 -500 200 R 50 50 5 1 B
X IO/VREFB2NO 30 -200 -600 200 R 50 50 5 1 B
X VCCIO2 31 1550 -200 200 L 50 50 5 1 W
X PLL_L_CLKOUTn/DIFFIO_RX_L27n 32 -200 -700 200 R 50 50 5 1 B
X PLL_L_CLKOUTp/DIFFIO_RX_L27p 33 -200 -800 200 R 50 50 5 1 B
X DIFFIO_TX_RX_B1n 38 -200 -200 200 R 50 50 6 1 B
X DIFFIO_TX_RX_B1p 39 -200 -300 200 R 50 50 6 1 B
X VCCIO3 40 1550 -200 200 L 50 50 6 1 W
X DIFFIO_TX_RX_B3n 41 -200 -400 200 R 50 50 6 1 B
X DIFFIO_TX_RX_B3p 43 -200 -500 200 R 50 50 6 1 B
X DIFFIO_TX_RX_B5n 44 -200 -600 200 R 50 50 6 1 B
X DIFFIO_TX_RX_B5p 45 -200 -700 200 R 50 50 6 1 B
X DIFFIO_TX_RX_B7n 46 -200 -800 200 R 50 50 6 1 B
X DIFFIO_TX_RX_B7p 47 -200 -900 200 R 50 50 6 1 B
X IO/VREFB3N0 48 -200 -1000 200 R 50 50 6 1 B
X VCCIO3 49 1550 -300 200 L 50 50 6 1 W
X DIFFIO_TX_RX_B9n 50 -200 -1100 200 R 50 50 6 1 B
X DIFFIO_TX_RX_B9p 52 -200 -1200 200 R 50 50 6 1 B
X IO 54 -200 -1300 200 R 50 50 6 1 B
X DIFFIO_TX_RX_B12n 55 -200 -1400 200 R 50 50 6 1 B
X DIFFIO_TX_RX_B12p 56 -200 -1500 200 R 50 50 6 1 B
X DIFFIO_TX_RX_B14n 57 -200 -1600 200 R 50 50 6 1 B
X DIFFIO_TX_RX_B14p 58 -200 -1700 200 R 50 50 6 1 B
X DIFFIO_TX_RX_B16n 59 -200 -1800 200 R 50 50 6 1 B
X DIFFIO_TX_RX_B16p 60 -200 -1900 200 R 50 50 6 1 B
X IO/VREFB4N0 61 -200 -200 200 R 50 50 7 1 B
X IO 62 -200 -300 200 R 50 50 7 1 B
X DIFFIO_TX_RX_B23n 64 -200 -400 200 R 50 50 7 1 B
X DIFFIO_TX_RX_B23p 65 -200 -500 200 R 50 50 7 1 B
X IO 66 -200 -600 200 R 50 50 7 1 B
X VCCIO4 67 1500 -200 200 L 50 50 7 1 W
X DIFFIO_TX_RX_B27n 69 -200 -700 200 R 50 50 7 1 B
X DIFFIO_TX_RX_B27p 70 -200 -800 200 R 50 50 7 1 B
X DIFFIO_RX_R2p 74 -200 -300 200 R 50 50 8 1 B
X DIFFIO_RX_R1p 75 -200 -200 200 R 50 50 8 1 B
X DIFFIO_RX_R2n 76 -200 -500 200 R 50 50 8 1 B
X DIFFIO_RX_R1n 77 -200 -400 200 R 50 50 8 1 B
X IO 78 -200 -600 200 R 50 50 8 1 B
X DIFFIO_RX_R7p 79 -200 -700 200 R 50 50 8 1 B
X IO/VREFB5N0 80 -200 -800 200 R 50 50 8 1 B
X DIFFIO_RX_R7n 81 -200 -900 200 R 50 50 8 1 B
X VCCIO5 82 1200 -200 200 L 50 50 8 1 W
X DIFFIO_RX_R11p 84 -200 -1100 200 R 50 50 8 1 B
X DIFFIO_RX_R10p 85 -200 -1000 200 R 50 50 8 1 B
X DIFFIO_RX_R11n 86 -200 -1300 200 R 50 50 8 1 B
X DIFFIO_RX_R10n 87 -200 -1200 200 R 50 50 8 1 B
X DIFFIO_RX_R28p 100 -200 -1200 200 R 50 50 9 1 B
X DIFFIO_RX_R27n 101 -200 -1300 200 R 50 50 9 1 B
X DIFFIO_RX_R28n 102 -200 -1400 200 R 50 50 9 1 B
X VCCIO6 103 1500 -300 200 L 50 50 9 1 W
X DIFFIO_RX_R33p 105 -200 -1500 200 R 50 50 9 1 B
X DIFFIO_RX_R33n 106 -200 -1600 200 R 50 50 9 1 B
X CLK2p/DIFFIO_RX_R14p 88 -200 -200 200 R 50 50 9 1 B
X CLK2n/DIFFIO_RX_R14n 89 -200 -300 200 R 50 50 9 1 B
X CLK3p/DIFFIO_RX_R16p 90 -200 -400 200 R 50 50 9 1 B
X CLK3n/DIFFIO_RX_R16n 91 -200 -500 200 R 50 50 9 1 B
X DIFFIO_RX_R18p 92 -200 -600 200 R 50 50 9 1 B
X DIFFIO_RX_R18n 93 -200 -700 200 R 50 50 9 1 B
X VCCIO6 94 1500 -200 200 L 50 50 9 1 W
X DIFFIO_RX_R26p 96 -200 -800 200 R 50 50 9 1 B
X IO/VREFB6N0 97 -200 -900 200 R 50 50 9 1 B
X DPCLK2/DIFFIO_RX_R26n 98 -200 -1000 200 R 50 50 9 1 B
X DIFFIO_RX_R27p 99 -200 -1100 200 R 50 50 9 1 B
X DIFFIO_RX_T1p 110 -200 -200 200 R 50 50 10 1 B
X DIFFIO_RX_T1n 111 -200 -300 200 R 50 50 10 1 B
X IO/VREFB7N0 112 -200 -400 200 R 50 50 10 1 B
X IO 113 -200 -500 200 R 50 50 10 1 B
X IO 114 -200 -600 200 R 50 50 10 1 B
X VCCIO7 117 1500 -200 200 L 50 50 10 1 W
X DIFFIO_RX_T10p 118 -200 -700 200 R 50 50 10 1 B
X DIFFIO_RX_T10n 119 -200 -800 200 R 50 50 10 1 B
X DIFFIO_RX_T16p 120 -200 -200 200 R 50 50 11 1 B
X DEV_CLRn/DIFFIO_RX_T16n 121 -200 -300 200 R 50 50 11 1 B
X IO/DEV_OE 122 -200 -400 200 R 50 50 11 1 B
X IO/VREFB8N0 123 -200 -500 200 R 50 50 11 1 B
X DIFFIO_RX_T19p 124 -200 -700 200 R 50 50 11 1 B
X IO/CONFIG_SEL 126 -200 -600 200 R 50 50 11 1 B
X DIFFIO_RX_T19n 127 -200 -900 200 R 50 50 11 1 B
X VCCIO8 128 1950 -200 200 L 50 50 11 1 W
X I/nCONFIG 129 -200 -800 200 R 50 50 11 1 B
X DIFFIO_RX_T20p 130 -200 -1000 200 R 50 50 11 1 B
X DIFFIO_RX_T20n 131 -200 -1100 200 R 50 50 11 1 B
X DIFFIO_RX_T22p 132 -200 -1200 200 R 50 50 11 1 B
X CRC_ERROR/DIFFIO_RX_T22n 134 -200 -1300 200 R 50 50 11 1 B
X IO 135 -200 -1400 200 R 50 50 11 1 B
X nSTATUS/DIFFIO_RX_T24p 136 -200 -1500 200 R 50 50 11 1 B
X CONF_DONE/DIFFIO_RX_T24n 138 -200 -1600 200 R 50 50 11 1 B
X VCCIO8 139 1950 -300 200 L 50 50 11 1 W
X DIFFIO_RX_T26p 140 -200 -1700 200 R 50 50 11 1 B
X DIFFIO_RX_T26n 141 -200 -1800 200 R 50 50 11 1 B
ENDDRAW
ENDDEF
#
# EP4CE6E22C8N # EP4CE6E22C8N
# #
DEF EP4CE6E22C8N U 0 40 Y Y 10 L N DEF EP4CE6E22C8N U 0 40 Y Y 10 L N

4
schematics/shimatta_regulators.lib
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@ -101,12 +101,12 @@ S 0 0 650 -750 0 1 0 f
X EN 1 -100 -100 100 R 50 50 1 1 I X EN 1 -100 -100 100 R 50 50 1 1 I
X VFB 2 -100 -200 100 R 50 50 1 1 I X VFB 2 -100 -200 100 R 50 50 1 1 I
X VREG5 3 -100 -300 100 R 50 50 1 1 I X VREG5 3 -100 -300 100 R 50 50 1 1 I
X SS 4 -100 -450 100 R 50 50 1 1 I
X GND 5 250 -850 100 U 50 50 1 1 W X GND 5 250 -850 100 U 50 50 1 1 W
X SW 6 750 -300 100 L 50 50 1 1 w
X VBST 7 750 -200 100 L 50 50 1 1 W X VBST 7 750 -200 100 L 50 50 1 1 W
X VIN 8 750 -100 100 L 50 50 1 1 W X VIN 8 750 -100 100 L 50 50 1 1 W
X Pad 9 400 -850 100 U 50 50 1 1 W X Pad 9 400 -850 100 U 50 50 1 1 W
X SS ~ -100 -450 100 R 50 50 1 1 I
X SW ~ 750 -300 100 L 50 50 1 1 w
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #

2
schematics/shimatta_transistors.lib
View File

@ -8,6 +8,7 @@ F0 "U" 100 50 50 H V C CNN
F1 "AO4402" -150 50 50 H V C CNN F1 "AO4402" -150 50 50 H V C CNN
F2 "" 0 0 50 H I C CNN F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN F3 "" 0 0 50 H I C CNN
ALIAS AO4402G
DRAW DRAW
S 0 0 450 -700 0 1 0 f S 0 0 450 -700 0 1 0 f
P 2 0 1 0 250 -400 250 -500 N P 2 0 1 0 250 -400 250 -500 N
@ -44,6 +45,7 @@ F0 "Q" 50 50 50 H V C CNN
F1 "AO4409" 350 50 50 H V C CNN F1 "AO4409" 350 50 50 H V C CNN
F2 "" 0 0 50 H I C CNN F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN F3 "" 0 0 50 H I C CNN
ALIAS AO4423
DRAW DRAW
C 410 -330 10 0 1 0 F C 410 -330 10 0 1 0 F
S 0 0 550 -900 0 1 0 f S 0 0 550 -900 0 1 0 f