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shimatta-jtag-adapter
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Rename nets and round PCB corners

This commit is contained in:
Mario Hüttel 2021-05-16 17:51:57 +02:00
parent 2f1fa13ae1
commit 939c3683e8
4 changed files with 3854 additions and 3067 deletions
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2
FT4232H.sch
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@ -1069,7 +1069,7 @@ Text HLabel 7700 4050 2 50 Input ~ 0
Text HLabel 7700 3950 2 50 Input ~ 0
~DSR3
Text HLabel 7700 3750 2 50 Input ~ 0
~CTS
~CTS3
Text HLabel 7700 4150 2 50 Output ~ 0
TXDEN3
Wire Wire Line

6869
shimatta-jtag-adapter.kicad_pcb
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File diff suppressed because it is too large Load Diff

46
shimatta-jtag-adapter.sch
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@ -996,16 +996,16 @@ F19 "~DTR3" O L 4900 3000 50
F20 "~RTS3" O L 4900 3150 50
F21 "~DCD3" I L 4900 3250 50
F22 "~DSR3" I L 4900 3350 50
F23 "~CTS" I L 4900 3450 50
F24 "TXDEN3" O L 4900 3550 50
F25 "MPSSE2_0" B L 4900 4450 50
F26 "MPSSE2_1" B L 4900 4550 50
F27 "MPSSE2_2" B L 4900 4650 50
F28 "MPSSE2_3" B L 4900 4750 50
F29 "MPSSE2_4" B L 4900 4850 50
F30 "MPSSE2_5" B L 4900 4950 50
F31 "MPSSE2_6" B L 4900 5050 50
F32 "MPSSE2_7" B L 4900 5150 50
F23 "TXDEN3" O L 4900 3550 50
F24 "MPSSE2_0" B L 4900 4450 50
F25 "MPSSE2_1" B L 4900 4550 50
F26 "MPSSE2_2" B L 4900 4650 50
F27 "MPSSE2_3" B L 4900 4750 50
F28 "MPSSE2_4" B L 4900 4850 50
F29 "MPSSE2_5" B L 4900 4950 50
F30 "MPSSE2_6" B L 4900 5050 50
F31 "MPSSE2_7" B L 4900 5150 50
F32 "~CTS3" I L 4900 3450 50
$EndSheet
$Comp
L Connector_Generic:Conn_02x08_Odd_Even J5
@ -1094,17 +1094,17 @@ F4 "~DTR3~_VDDIO" O L 3500 3000 50
F5 "~RTS3~_VDDIO" O L 3500 3150 50
F6 "~DCD3~_VDDIO" I L 3500 3250 50
F7 "~DSR3~_VDDIO" I L 3500 3350 50
F8 "~CTS~_VDDIO" I L 3500 3450 50
F9 "TXDEN3_VDDIO" O L 3500 3550 50
F10 "VDDIO" I L 3500 2650 50
F11 "TXD3_3V3" I R 4750 2800 50
F12 "RXD3_3V3" O R 4750 2900 50
F13 "~RTS3~_3V3" I R 4750 3150 50
F14 "~CTS~_3V3" O R 4750 3450 50
F15 "~DTR3~_3V3" I R 4750 3000 50
F16 "~DSR3~_3V3" O R 4750 3350 50
F17 "~DCD3~_3V3" O R 4750 3250 50
F18 "TXDEN3_3V3" I R 4750 3550 50
F8 "TXDEN3_VDDIO" O L 3500 3550 50
F9 "VDDIO" I L 3500 2650 50
F10 "TXD3_3V3" I R 4750 2800 50
F11 "RXD3_3V3" O R 4750 2900 50
F12 "~RTS3~_3V3" I R 4750 3150 50
F13 "~DTR3~_3V3" I R 4750 3000 50
F14 "~DSR3~_3V3" O R 4750 3350 50
F15 "~DCD3~_3V3" O R 4750 3250 50
F16 "TXDEN3_3V3" I R 4750 3550 50
F17 "~CTS3~_VDDIO" I L 3500 3450 50
F18 "~CTS3~_3V3" O R 4750 3450 50
$EndSheet
Text Label 9850 3850 0 50 ~ 0
RS485+
@ -1668,10 +1668,10 @@ F 3 "" H 4250 4200 50 0001 C CNN
1 0 0 -1
$EndComp
$Comp
L power:GND #PWR?
L power:GND #PWR0196
U 1 1 60CE344C
P 10150 1100
F 0 "#PWR?" H 10150 850 50 0001 C CNN
F 0 "#PWR0196" H 10150 850 50 0001 C CNN
F 1 "GND" H 10155 927 50 0000 C CNN
F 2 "" H 10150 1100 50 0001 C CNN
F 3 "" H 10150 1100 50 0001 C CNN

4
uart3-level-translation.sch
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@ -26,7 +26,7 @@ Text HLabel 6500 5750 2 50 Input ~ 0
Text HLabel 6500 4300 2 50 Input ~ 0
~DSR3~_VDDIO
Text HLabel 6550 2850 2 50 Input ~ 0
~CTS~_VDDIO
~CTS3~_VDDIO
Text HLabel 3300 5750 2 50 Output ~ 0
TXDEN3_VDDIO
Text HLabel 1600 700 0 50 Input ~ 0
@ -38,7 +38,7 @@ RXD3_3V3
Text HLabel 1400 2850 0 50 Input ~ 0
~RTS3~_3V3
Text HLabel 4650 2850 0 50 Output ~ 0
~CTS~_3V3
~CTS3~_3V3
Text HLabel 1400 4300 0 50 Input ~ 0
~DTR3~_3V3
Text HLabel 4650 4300 0 50 Output ~ 0