First draft for v1.0
This commit is contained in:
commit
5b23665e66
47
.gitignore
vendored
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47
.gitignore
vendored
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@ -0,0 +1,47 @@
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||||
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# Created by https://www.gitignore.io/api/kicad
|
||||
# Edit at https://www.gitignore.io/?templates=kicad
|
||||
|
||||
### KiCad ###
|
||||
# For PCBs designed using KiCad: http://www.kicad-pcb.org/
|
||||
# Format documentation: http://kicad-pcb.org/help/file-formats/
|
||||
|
||||
*.blend1
|
||||
*.blend2
|
||||
*.blend3
|
||||
|
||||
|
||||
# Temporary files
|
||||
*.000
|
||||
*.bak
|
||||
*.bck
|
||||
*-bak
|
||||
*.kicad_pcb-bak
|
||||
*~
|
||||
_autosave-*
|
||||
*.tmp
|
||||
*-save.pro
|
||||
*-save.kicad_pcb
|
||||
fp-info-cache
|
||||
|
||||
# Netlist files (exported from Eeschema)
|
||||
*.net
|
||||
|
||||
# Autorouter files (exported from Pcbnew)
|
||||
*.dsn
|
||||
*.ses
|
||||
|
||||
# Exported BOM files
|
||||
*.xml
|
||||
*.csv
|
||||
|
||||
### KiCad Patch ###
|
||||
escue-backup/
|
||||
|
||||
*.tsv
|
||||
bom/
|
||||
|
||||
# Gerber export output
|
||||
out/
|
||||
|
||||
# End of https://www.gitignore.io/api/kicad
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||||
438
xilinx-jtag-cache.lib
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438
xilinx-jtag-cache.lib
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@ -0,0 +1,438 @@
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||||
EESchema-LIBRARY Version 2.4
|
||||
#encoding utf-8
|
||||
#
|
||||
# Connector_Generic_Conn_02x07_Odd_Even
|
||||
#
|
||||
DEF Connector_Generic_Conn_02x07_Odd_Even J 0 40 Y N 1 F N
|
||||
F0 "J" 50 400 50 H V C CNN
|
||||
F1 "Connector_Generic_Conn_02x07_Odd_Even" 50 -400 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
Connector*:*_2x??_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -50 -295 0 -305 1 1 6 N
|
||||
S -50 -195 0 -205 1 1 6 N
|
||||
S -50 -95 0 -105 1 1 6 N
|
||||
S -50 5 0 -5 1 1 6 N
|
||||
S -50 105 0 95 1 1 6 N
|
||||
S -50 205 0 195 1 1 6 N
|
||||
S -50 305 0 295 1 1 6 N
|
||||
S -50 350 150 -350 1 1 10 f
|
||||
S 150 -295 100 -305 1 1 6 N
|
||||
S 150 -195 100 -205 1 1 6 N
|
||||
S 150 -95 100 -105 1 1 6 N
|
||||
S 150 5 100 -5 1 1 6 N
|
||||
S 150 105 100 95 1 1 6 N
|
||||
S 150 205 100 195 1 1 6 N
|
||||
S 150 305 100 295 1 1 6 N
|
||||
X Pin_1 1 -200 300 150 R 50 50 1 1 P
|
||||
X Pin_10 10 300 -100 150 L 50 50 1 1 P
|
||||
X Pin_11 11 -200 -200 150 R 50 50 1 1 P
|
||||
X Pin_12 12 300 -200 150 L 50 50 1 1 P
|
||||
X Pin_13 13 -200 -300 150 R 50 50 1 1 P
|
||||
X Pin_14 14 300 -300 150 L 50 50 1 1 P
|
||||
X Pin_2 2 300 300 150 L 50 50 1 1 P
|
||||
X Pin_3 3 -200 200 150 R 50 50 1 1 P
|
||||
X Pin_4 4 300 200 150 L 50 50 1 1 P
|
||||
X Pin_5 5 -200 100 150 R 50 50 1 1 P
|
||||
X Pin_6 6 300 100 150 L 50 50 1 1 P
|
||||
X Pin_7 7 -200 0 150 R 50 50 1 1 P
|
||||
X Pin_8 8 300 0 150 L 50 50 1 1 P
|
||||
X Pin_9 9 -200 -100 150 R 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Connector_USB_B
|
||||
#
|
||||
DEF Connector_USB_B J 0 40 Y Y 1 F N
|
||||
F0 "J" -200 450 50 H V L CNN
|
||||
F1 "Connector_USB_B" -200 350 50 H V L CNN
|
||||
F2 "" 150 -50 50 H I C CNN
|
||||
F3 "" 150 -50 50 H I C CNN
|
||||
$FPLIST
|
||||
USB*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
C -150 85 25 0 1 10 F
|
||||
C -25 135 15 0 1 10 F
|
||||
S -200 -300 200 300 0 1 10 f
|
||||
S -150 220 -100 180 0 1 0 F
|
||||
S -5 -300 5 -270 0 1 0 N
|
||||
S 10 50 -20 20 0 1 10 F
|
||||
S 200 -105 170 -95 0 1 0 N
|
||||
S 200 -5 170 5 0 1 0 N
|
||||
S 200 195 170 205 0 1 0 N
|
||||
P 2 0 1 10 -75 85 25 85 N
|
||||
P 4 0 1 10 -125 85 -100 85 -50 135 -25 135 N
|
||||
P 4 0 1 10 -100 85 -75 85 -50 35 0 35 N
|
||||
P 4 0 1 10 25 110 25 60 75 85 25 110 F
|
||||
P 7 0 1 0 -160 170 -90 170 -90 225 -105 240 -145 240 -160 225 -160 170 N
|
||||
X VBUS 1 300 200 100 L 50 50 1 1 w
|
||||
X D- 2 300 -100 100 L 50 50 1 1 B
|
||||
X D+ 3 300 0 100 L 50 50 1 1 B
|
||||
X GND 4 0 -400 100 U 50 50 1 1 w
|
||||
X Shield 5 -100 -400 100 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_C
|
||||
#
|
||||
DEF Device_C C 0 10 N Y 1 F N
|
||||
F0 "C" 25 100 50 H V L CNN
|
||||
F1 "Device_C" 25 -100 50 H V L CNN
|
||||
F2 "" 38 -150 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
C_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 20 -80 -30 80 -30 N
|
||||
P 2 0 1 20 -80 30 80 30 N
|
||||
X ~ 1 0 150 110 D 50 50 1 1 P
|
||||
X ~ 2 0 -150 110 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_Crystal_GND24
|
||||
#
|
||||
DEF Device_Crystal_GND24 Y 0 40 Y N 1 F N
|
||||
F0 "Y" 125 200 50 H V L CNN
|
||||
F1 "Device_Crystal_GND24" 125 125 50 H V L CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
Crystal*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -45 100 45 -100 0 1 12 N
|
||||
P 2 0 1 0 -100 0 -80 0 N
|
||||
P 2 0 1 20 -80 -50 -80 50 N
|
||||
P 2 0 1 0 0 -150 0 -140 N
|
||||
P 2 0 1 0 0 140 0 150 N
|
||||
P 2 0 1 20 80 -50 80 50 N
|
||||
P 2 0 1 0 80 0 100 0 N
|
||||
P 4 0 1 0 -100 -90 -100 -140 100 -140 100 -90 N
|
||||
P 4 0 1 0 -100 90 -100 140 100 140 100 90 N
|
||||
X 1 1 -150 0 50 R 50 50 1 1 P
|
||||
X 2 2 0 200 50 D 50 50 1 1 P
|
||||
X 3 3 150 0 50 L 50 50 1 1 P
|
||||
X 4 4 0 -200 50 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_LED
|
||||
#
|
||||
DEF Device_LED D 0 40 N N 1 F N
|
||||
F0 "D" 0 100 50 H V C CNN
|
||||
F1 "Device_LED" 0 -100 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
LED*
|
||||
LED_SMD:*
|
||||
LED_THT:*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
P 2 0 1 10 -50 -50 -50 50 N
|
||||
P 2 0 1 0 -50 0 50 0 N
|
||||
P 4 0 1 10 50 -50 50 50 -50 0 50 -50 N
|
||||
P 5 0 1 0 -120 -30 -180 -90 -150 -90 -180 -90 -180 -60 N
|
||||
P 5 0 1 0 -70 -30 -130 -90 -100 -90 -130 -90 -130 -60 N
|
||||
X K 1 -150 0 100 R 50 50 1 1 P
|
||||
X A 2 150 0 100 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_L_Core_Ferrite
|
||||
#
|
||||
DEF Device_L_Core_Ferrite L 0 40 N N 1 F N
|
||||
F0 "L" -50 0 50 V V C CNN
|
||||
F1 "Device_L_Core_Ferrite" 110 0 50 V V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
Choke_*
|
||||
*Coil*
|
||||
Inductor_*
|
||||
L_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
A 0 -75 25 -899 899 0 1 0 N 0 -100 0 -50
|
||||
A 0 -25 25 -899 899 0 1 0 N 0 -50 0 0
|
||||
A 0 25 25 -899 899 0 1 0 N 0 0 0 50
|
||||
A 0 75 25 -899 899 0 1 0 N 0 50 0 100
|
||||
P 2 0 1 0 40 -110 40 -90 N
|
||||
P 2 0 1 0 40 -70 40 -50 N
|
||||
P 2 0 1 0 40 -30 40 -10 N
|
||||
P 2 0 1 0 40 10 40 30 N
|
||||
P 2 0 1 0 40 50 40 70 N
|
||||
P 2 0 1 0 40 90 40 110 N
|
||||
P 2 0 1 0 60 -90 60 -110 N
|
||||
P 2 0 1 0 60 -50 60 -70 N
|
||||
P 2 0 1 0 60 -10 60 -30 N
|
||||
P 2 0 1 0 60 30 60 10 N
|
||||
P 2 0 1 0 60 70 60 50 N
|
||||
P 2 0 1 0 60 110 60 90 N
|
||||
X 1 1 0 150 50 D 50 50 1 1 P
|
||||
X 2 2 0 -150 50 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Device_R
|
||||
#
|
||||
DEF Device_R R 0 0 N Y 1 F N
|
||||
F0 "R" 80 0 50 V V C CNN
|
||||
F1 "Device_R" 0 0 50 V V C CNN
|
||||
F2 "" -70 0 50 V I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
R_*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -40 -100 40 100 0 1 10 N
|
||||
X ~ 1 0 150 50 D 50 50 1 1 P
|
||||
X ~ 2 0 -150 50 U 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Interface_USB_FT2232HQ
|
||||
#
|
||||
DEF Interface_USB_FT2232HQ U 0 20 Y Y 1 F N
|
||||
F0 "U" -1050 2100 50 H V L CNN
|
||||
F1 "Interface_USB_FT2232HQ" 750 2100 50 H V L CNN
|
||||
F2 "Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP4.35x4.35mm" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
$FPLIST
|
||||
QFN*1EP*9x9mm*P0.5mm*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -1050 -2050 1050 2050 0 1 10 f
|
||||
X GND 1 -400 -2200 150 U 50 50 1 1 W
|
||||
X AGND 10 -600 -2200 150 U 50 50 1 1 W
|
||||
X GND 11 -200 -2200 150 U 50 50 1 1 W
|
||||
X VCORE 12 -200 2200 150 D 50 50 1 1 W
|
||||
X TEST 13 -1200 -1800 150 R 50 50 1 1 I
|
||||
X ~RESET 14 -1200 400 150 R 50 50 1 1 I
|
||||
X GND 15 -100 -2200 150 U 50 50 1 1 W
|
||||
X ADBUS0 16 1200 1900 150 L 50 50 1 1 B
|
||||
X ADBUS1 17 1200 1800 150 L 50 50 1 1 B
|
||||
X ADBUS2 18 1200 1700 150 L 50 50 1 1 B
|
||||
X ADBUS3 19 1200 1600 150 L 50 50 1 1 B
|
||||
X OSCI 2 -1200 -1200 150 R 50 50 1 1 I
|
||||
X VCCIO 20 200 2200 150 D 50 50 1 1 W
|
||||
X ADBUS4 21 1200 1500 150 L 50 50 1 1 B
|
||||
X ADBUS5 22 1200 1400 150 L 50 50 1 1 B
|
||||
X ADBUS6 23 1200 1300 150 L 50 50 1 1 B
|
||||
X ADBUS7 24 1200 1200 150 L 50 50 1 1 B
|
||||
X GND 25 0 -2200 150 U 50 50 1 1 W
|
||||
X ACBUS0 26 1200 1000 150 L 50 50 1 1 B
|
||||
X ACBUS1 27 1200 900 150 L 50 50 1 1 B
|
||||
X ACBUS2 28 1200 800 150 L 50 50 1 1 B
|
||||
X ACBUS3 29 1200 700 150 L 50 50 1 1 B
|
||||
X OSCO 3 -1200 -1600 150 R 50 50 1 1 O
|
||||
X ACBUS4 30 1200 600 150 L 50 50 1 1 B
|
||||
X VCCIO 31 300 2200 150 D 50 50 1 1 W
|
||||
X ACBUS5 32 1200 500 150 L 50 50 1 1 B
|
||||
X ACBUS6 33 1200 400 150 L 50 50 1 1 B
|
||||
X ACBUS7 34 1200 300 150 L 50 50 1 1 B
|
||||
X GND 35 100 -2200 150 U 50 50 1 1 W
|
||||
X ~SUSPEND 36 1200 -1800 150 L 50 50 1 1 O
|
||||
X VCORE 37 -100 2200 150 D 50 50 1 1 W
|
||||
X BDBUS0 38 1200 100 150 L 50 50 1 1 B
|
||||
X BDBUS1 39 1200 0 150 L 50 50 1 1 B
|
||||
X VPHY 4 -500 2200 150 D 50 50 1 1 W
|
||||
X BDBUS2 40 1200 -100 150 L 50 50 1 1 B
|
||||
X BDBUS3 41 1200 -200 150 L 50 50 1 1 B
|
||||
X VCCIO 42 400 2200 150 D 50 50 1 1 W
|
||||
X BDBUS4 43 1200 -300 150 L 50 50 1 1 B
|
||||
X BDBUS5 44 1200 -400 150 L 50 50 1 1 B
|
||||
X BDBUS6 45 1200 -500 150 L 50 50 1 1 B
|
||||
X BDBUS7 46 1200 -600 150 L 50 50 1 1 B
|
||||
X GND 47 200 -2200 150 U 50 50 1 1 W
|
||||
X BCBUS0 48 1200 -800 150 L 50 50 1 1 B
|
||||
X VREGOUT 49 -1200 1700 150 R 50 50 1 1 w
|
||||
X GND 5 -300 -2200 150 U 50 50 1 1 W
|
||||
X VREGIN 50 -1200 1900 150 R 50 50 1 1 W
|
||||
X GND 51 300 -2200 150 U 50 50 1 1 W
|
||||
X BCBUS1 52 1200 -900 150 L 50 50 1 1 B
|
||||
X BCBUS2 53 1200 -1000 150 L 50 50 1 1 B
|
||||
X BCBUS3 54 1200 -1100 150 L 50 50 1 1 B
|
||||
X BCBUS4 55 1200 -1200 150 L 50 50 1 1 B
|
||||
X VCCIO 56 500 2200 150 D 50 50 1 1 W
|
||||
X BCBUS5 57 1200 -1300 150 L 50 50 1 1 B
|
||||
X BCBUS6 58 1200 -1400 150 L 50 50 1 1 B
|
||||
X BCBUS7 59 1200 -1500 150 L 50 50 1 1 B
|
||||
X REF 6 -1200 600 150 R 50 50 1 1 O
|
||||
X ~PWREN 60 1200 -1700 150 L 50 50 1 1 O
|
||||
X EEDATA 61 -1200 -900 150 R 50 50 1 1 B
|
||||
X EECLK 62 -1200 -800 150 R 50 50 1 1 O
|
||||
X EECS 63 -1200 -700 150 R 50 50 1 1 O
|
||||
X VCORE 64 0 2200 150 D 50 50 1 1 W
|
||||
X GND 65 400 -2200 150 U 50 50 1 1 W
|
||||
X DM 7 -1200 900 150 R 50 50 1 1 B
|
||||
X DP 8 -1200 800 150 R 50 50 1 1 B
|
||||
X VPLL 9 -400 2200 150 D 50 50 1 1 I
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Logic_LevelTranslator_SN74LV1T34DBV
|
||||
#
|
||||
DEF Logic_LevelTranslator_SN74LV1T34DBV U 0 20 Y Y 1 F N
|
||||
F0 "U" 200 250 50 H V L CNN
|
||||
F1 "Logic_LevelTranslator_SN74LV1T34DBV" 200 150 50 H V L CNN
|
||||
F2 "Package_TO_SOT_SMD:SOT-23-5" 650 -250 50 H I C CNN
|
||||
F3 "" -400 -200 50 H I C CNN
|
||||
$FPLIST
|
||||
SOT?23*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -200 200 200 -200 0 1 10 f
|
||||
P 2 0 1 0 -30 0 -100 0 N
|
||||
P 2 0 1 0 40 0 100 0 N
|
||||
P 4 1 1 0 -30 -30 -30 30 40 0 -30 -30 N
|
||||
X NC 1 -200 100 100 R 50 50 1 1 N N
|
||||
X A 2 -300 0 100 R 50 50 1 1 I
|
||||
X GND 3 0 -300 100 U 50 50 1 1 W
|
||||
X Y 4 300 0 100 L 50 50 1 1 O
|
||||
X VCC 5 0 300 100 D 50 50 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Memory_EEPROM_93LCxxBxxOT
|
||||
#
|
||||
DEF Memory_EEPROM_93LCxxBxxOT U 0 20 Y Y 1 F N
|
||||
F0 "U" -250 250 50 H V C CNN
|
||||
F1 "Memory_EEPROM_93LCxxBxxOT" 300 -250 50 H V C CNN
|
||||
F2 "Package_TO_SOT_SMD:SOT-23-6" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
ALIAS 93LCxxBxxOT
|
||||
$FPLIST
|
||||
SOT?23*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -300 200 300 -200 0 1 10 f
|
||||
X DO 1 400 -100 100 L 50 50 1 1 T
|
||||
X GND 2 0 -300 100 U 50 50 1 1 W
|
||||
X DI 3 400 0 100 L 50 50 1 1 I
|
||||
X CLK 4 400 100 100 L 50 50 1 1 I
|
||||
X CS 5 -400 100 100 R 50 50 1 1 I
|
||||
X VCC 6 0 300 100 D 50 50 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# Regulator_Linear_AP1117-33
|
||||
#
|
||||
DEF Regulator_Linear_AP1117-33 U 0 10 Y Y 1 F N
|
||||
F0 "U" -150 125 50 H V C CNN
|
||||
F1 "Regulator_Linear_AP1117-33" 0 125 50 H V L CNN
|
||||
F2 "Package_TO_SOT_SMD:SOT-223-3_TabPin2" 0 200 50 H I C CNN
|
||||
F3 "" 100 -250 50 H I C CNN
|
||||
ALIAS AP1117-18 AP1117-25 AP1117-33 AP1117-50 LD1117S33TR_SOT223 LD1117S12TR_SOT223 LD1117S18TR_SOT223 LD1117S25TR_SOT223 LD1117S50TR_SOT223 NCP1117-12_SOT223 NCP1117-1.5_SOT223 NCP1117-1.8_SOT223 NCP1117-2.0_SOT223 NCP1117-2.5_SOT223 NCP1117-2.85_SOT223 NCP1117-3.3_SOT223 NCP1117-5.0_SOT223 AMS1117-1.5 AMS1117-1.8 AMS1117-2.5 AMS1117-2.85 AMS1117-3.3 AMS1117-5.0
|
||||
$FPLIST
|
||||
SOT?223*TabPin2*
|
||||
$ENDFPLIST
|
||||
DRAW
|
||||
S -200 -200 200 75 0 1 10 f
|
||||
X GND 1 0 -300 100 U 50 50 1 1 W
|
||||
X VO 2 300 0 100 L 50 50 1 1 w
|
||||
X VI 3 -300 0 100 R 50 50 1 1 W
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_+3V3
|
||||
#
|
||||
DEF power_+3V3 #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "power_+3V3" 0 140 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
ALIAS +3.3V
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +3V3 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_+5V
|
||||
#
|
||||
DEF power_+5V #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "power_+5V" 0 140 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X +5V 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_GND
|
||||
#
|
||||
DEF power_GND #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -250 50 H I C CNN
|
||||
F1 "power_GND" 0 -150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 6 0 1 0 0 0 0 -50 50 -50 0 -100 -50 -50 0 -50 N
|
||||
X GND 1 0 0 0 D 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# power_VDD
|
||||
#
|
||||
DEF power_VDD #PWR 0 0 Y Y 1 F P
|
||||
F0 "#PWR" 0 -150 50 H I C CNN
|
||||
F1 "power_VDD" 0 150 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 2 0 1 0 -30 50 0 100 N
|
||||
P 2 0 1 0 0 0 0 100 N
|
||||
P 2 0 1 0 0 100 30 50 N
|
||||
X VDD 1 0 0 0 U 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# shimatta_connectors_10PIN_JTAG_SWD
|
||||
#
|
||||
DEF shimatta_connectors_10PIN_JTAG_SWD J 0 40 Y Y 1 F N
|
||||
F0 "J" -280 40 50 H V C CNN
|
||||
F1 "shimatta_connectors_10PIN_JTAG_SWD" 10 110 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
S -820 0 0 -1000 0 1 0 f
|
||||
X VCC 1 100 -50 100 L 50 50 1 1 P
|
||||
X RESET 10 100 -350 100 L 50 50 1 1 P
|
||||
X TMS/SWDIO 2 100 -450 100 L 50 50 1 1 P
|
||||
X GND 3 100 -250 100 L 50 50 1 1 P
|
||||
X TCK/SWCLK 4 100 -550 100 L 50 50 1 1 P
|
||||
X TESTMODE/VCC/GND 5 100 -150 100 L 50 50 1 1 P
|
||||
X TDO/SWO 6 100 -650 100 L 50 50 1 1 P
|
||||
X RX/RTCLK 7 100 -850 100 L 50 50 1 1 P
|
||||
X TDI 8 100 -750 100 L 50 50 1 1 P
|
||||
X TX/~TRST 9 100 -950 100 L 50 50 1 1 P
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
# shimatta_supply_VCCINT
|
||||
#
|
||||
DEF shimatta_supply_VCCINT #PWR 0 40 Y Y 1 F P
|
||||
F0 "#PWR" 0 100 50 H I C CNN
|
||||
F1 "shimatta_supply_VCCINT" 0 100 50 H V C CNN
|
||||
F2 "" 0 0 50 H I C CNN
|
||||
F3 "" 0 0 50 H I C CNN
|
||||
DRAW
|
||||
P 4 0 1 0 0 0 0 50 50 50 -50 50 N
|
||||
X VCCINT ~ 0 0 0 L 50 50 1 1 W N
|
||||
ENDDRAW
|
||||
ENDDEF
|
||||
#
|
||||
#End Library
|
||||
5443
xilinx-jtag.kicad_pcb
Normal file
5443
xilinx-jtag.kicad_pcb
Normal file
File diff suppressed because it is too large
Load Diff
251
xilinx-jtag.pro
Normal file
251
xilinx-jtag.pro
Normal file
@ -0,0 +1,251 @@
|
||||
update=Sat 15 May 2021 01:15:33 PM CEST
|
||||
version=1
|
||||
last_client=kicad
|
||||
[general]
|
||||
version=1
|
||||
RootSch=
|
||||
BoardNm=
|
||||
[cvpcb]
|
||||
version=1
|
||||
NetIExt=net
|
||||
[eeschema]
|
||||
version=1
|
||||
LibDir=
|
||||
[eeschema/libraries]
|
||||
[pcbnew]
|
||||
version=1
|
||||
PageLayoutDescrFile=
|
||||
LastNetListRead=
|
||||
CopperLayerCount=2
|
||||
BoardThickness=1.6
|
||||
AllowMicroVias=0
|
||||
AllowBlindVias=0
|
||||
RequireCourtyardDefinitions=0
|
||||
ProhibitOverlappingCourtyards=1
|
||||
MinTrackWidth=0.2
|
||||
MinViaDiameter=0.4
|
||||
MinViaDrill=0.3
|
||||
MinMicroViaDiameter=0.2
|
||||
MinMicroViaDrill=0.09999999999999999
|
||||
MinHoleToHole=0.25
|
||||
TrackWidth1=0.25
|
||||
TrackWidth2=0.3
|
||||
TrackWidth3=0.6
|
||||
ViaDiameter1=0.6
|
||||
ViaDrill1=0.3
|
||||
dPairWidth1=0.2
|
||||
dPairGap1=0.25
|
||||
dPairViaGap1=0.25
|
||||
SilkLineWidth=0.12
|
||||
SilkTextSizeV=1
|
||||
SilkTextSizeH=1
|
||||
SilkTextSizeThickness=0.15
|
||||
SilkTextItalic=0
|
||||
SilkTextUpright=1
|
||||
CopperLineWidth=0.2
|
||||
CopperTextSizeV=1.5
|
||||
CopperTextSizeH=1.5
|
||||
CopperTextThickness=0.3
|
||||
CopperTextItalic=0
|
||||
CopperTextUpright=1
|
||||
EdgeCutLineWidth=0.05
|
||||
CourtyardLineWidth=0.05
|
||||
OthersLineWidth=0.15
|
||||
OthersTextSizeV=1
|
||||
OthersTextSizeH=1
|
||||
OthersTextSizeThickness=0.15
|
||||
OthersTextItalic=0
|
||||
OthersTextUpright=1
|
||||
SolderMaskClearance=0
|
||||
SolderMaskMinWidth=0
|
||||
SolderPasteClearance=0
|
||||
SolderPasteRatio=-0
|
||||
[pcbnew/Layer.F.Cu]
|
||||
Name=F.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.In1.Cu]
|
||||
Name=In1.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In2.Cu]
|
||||
Name=In2.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In3.Cu]
|
||||
Name=In3.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In4.Cu]
|
||||
Name=In4.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In5.Cu]
|
||||
Name=In5.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In6.Cu]
|
||||
Name=In6.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In7.Cu]
|
||||
Name=In7.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In8.Cu]
|
||||
Name=In8.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In9.Cu]
|
||||
Name=In9.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In10.Cu]
|
||||
Name=In10.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In11.Cu]
|
||||
Name=In11.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In12.Cu]
|
||||
Name=In12.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In13.Cu]
|
||||
Name=In13.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In14.Cu]
|
||||
Name=In14.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In15.Cu]
|
||||
Name=In15.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In16.Cu]
|
||||
Name=In16.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In17.Cu]
|
||||
Name=In17.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In18.Cu]
|
||||
Name=In18.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In19.Cu]
|
||||
Name=In19.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In20.Cu]
|
||||
Name=In20.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In21.Cu]
|
||||
Name=In21.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In22.Cu]
|
||||
Name=In22.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In23.Cu]
|
||||
Name=In23.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In24.Cu]
|
||||
Name=In24.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In25.Cu]
|
||||
Name=In25.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In26.Cu]
|
||||
Name=In26.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In27.Cu]
|
||||
Name=In27.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In28.Cu]
|
||||
Name=In28.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In29.Cu]
|
||||
Name=In29.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.In30.Cu]
|
||||
Name=In30.Cu
|
||||
Type=0
|
||||
Enabled=0
|
||||
[pcbnew/Layer.B.Cu]
|
||||
Name=B.Cu
|
||||
Type=0
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Adhes]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Paste]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.SilkS]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Mask]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Dwgs.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Cmts.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco1.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Eco2.User]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Edge.Cuts]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Margin]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.CrtYd]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.B.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.F.Fab]
|
||||
Enabled=1
|
||||
[pcbnew/Layer.Rescue]
|
||||
Enabled=0
|
||||
[pcbnew/Netclasses]
|
||||
[pcbnew/Netclasses/Default]
|
||||
Name=Default
|
||||
Clearance=0.2
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.6
|
||||
ViaDrill=0.3
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.2
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
[pcbnew/Netclasses/1]
|
||||
Name=USB
|
||||
Clearance=0.2
|
||||
TrackWidth=0.25
|
||||
ViaDiameter=0.6
|
||||
ViaDrill=0.3
|
||||
uViaDiameter=0.3
|
||||
uViaDrill=0.1
|
||||
dPairWidth=0.25
|
||||
dPairGap=0.25
|
||||
dPairViaGap=0.25
|
||||
1812
xilinx-jtag.sch
Normal file
1812
xilinx-jtag.sch
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user