shimatta-team/xilinx-jtag
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Performed final DRC

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This commit is contained in:
Mario Hüttel 2021-05-25 22:47:31 +02:00
parent cb527a31f3
commit f70cd7df6a
1 changed files with 3 additions and 3 deletions
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6
xilinx-jtag.kicad_pcb
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@ -3921,7 +3921,7 @@
(segment (start 71.9 64) (end 65.75 64) (width 0.25) (layer F.Cu) (net 30))
(segment (start 41 57.9625) (end 41 55.825) (width 0.3) (layer F.Cu) (net 31))
(zone (net 1) (net_name GND) (layer B.Cu) (tstamp 60AD7923) (hatch edge 0.508)
(zone (net 1) (net_name GND) (layer B.Cu) (tstamp 60AD7E3C) (hatch edge 0.508)
(connect_pads (clearance 0.25))
(min_thickness 0.254)
(fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))
@ -4345,7 +4345,7 @@
)
)
)
(zone (net 1) (net_name GND) (layer F.Cu) (tstamp 60AD7920) (hatch edge 0.508)
(zone (net 1) (net_name GND) (layer F.Cu) (tstamp 60AD7E39) (hatch edge 0.508)
(connect_pads (clearance 0.25))
(min_thickness 0.254)
(fill yes (arc_segments 32) (thermal_gap 0.508) (thermal_bridge_width 0.508))
@ -5386,7 +5386,7 @@
)
)
)
(zone (net 3) (net_name +3V3) (layer B.Cu) (tstamp 60AD791D) (hatch edge 0.508)
(zone (net 3) (net_name +3V3) (layer B.Cu) (tstamp 60AD7E36) (hatch edge 0.508)
(priority 1)
(connect_pads (clearance 0.5))
(min_thickness 0.254)