Add read support to SMI
This commit is contained in:
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@ -2,7 +2,7 @@
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-- Title : LED Demo File
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-- Project : EthMAC
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-------------------------------------------------------------------------------
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-- File : design/led-demo.vhd
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-- File : design/led-demo.vhd
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-- Author : Mario Hüttel <mario.huettel@gmx.net>
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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@ -18,7 +18,7 @@
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--
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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@ -33,54 +33,54 @@ use ieee.numeric_std.all;
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entity leddemo is
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port(
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clk_tx : in std_logic;
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clk_rx : in std_logic;
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data_in : in std_logic_vector(3 downto 0);
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clk_tx : in std_logic;
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clk_rx : in std_logic;
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data_in : in std_logic_vector(3 downto 0);
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data_out : out std_logic_vector(3 downto 0);
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rst_hw : in std_logic;
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rmii_tx : out std_logic_vector(1 downto 0);
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rst_hw : in std_logic;
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rmii_tx : out std_logic_vector(1 downto 0);
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rmii_txen : out std_logic;
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rmii_rx : in std_logic_vector(1 downto 0);
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rmii_rxen : in std_logic;
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mdc : out std_logic_vector(1 downto 0);
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mdio : out std_logic_vector(1 downto 0)
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);
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rmii_rx : in std_logic_vector(1 downto 0);
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rmii_rxen : in std_logic;
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mdc : out std_logic_vector(1 downto 0);
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mdio : out std_logic_vector(1 downto 0)
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);
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end entity leddemo;
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architecture RTL of leddemo is
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constant DELAYCNTVAL : integer := 100000
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-- pragma synthesis_off
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/50000
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-- pragma synthesis_on
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;
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-- pragma synthesis_off
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/50000
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-- pragma synthesis_on
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;
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type smisend_t is (IDLE, STROBE);
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type rx_state_t is (RXSOFWAIT, RXDATA, RXCRCCHECK);
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type tx_state_t is (TXWAIT, TXSEND);
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type smiinit_t is (RESET, INIT, DELAY, INIT_COMPLETE);
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signal rx_state : rx_state_t;
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signal tx_state : tx_state_t;
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signal rx_state : rx_state_t;
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signal tx_state : tx_state_t;
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signal sendstate : smisend_t;
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signal delaycounter : unsigned(19 downto 0);
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signal regaddr_s : std_logic_vector(4 downto 0);
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signal smi_data_s : std_logic_vector(15 downto 0);
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signal smi_strb_s : std_logic;
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signal rst_rxtx : std_logic;
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signal rst : std_logic;
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signal rst_rxtx : std_logic;
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signal rst : std_logic;
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signal smi_busy_s : std_logic;
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signal initstate : smiinit_t;
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signal mdio_s : std_logic;
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signal mdc_s : std_logic;
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signal rx_crc : std_logic;
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signal rx_strb : std_logic;
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signal rx_data : std_logic_vector(7 downto 0);
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signal rx_eof : std_logic;
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signal rx_sof : std_logic;
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signal rx_mem : std_logic_vector(3 downto 0);
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signal tx_ack : std_logic;
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signal tx_data : std_logic_vector(7 downto 0);
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signal tx_eof : std_logic;
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signal tx_sof : std_logic;
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signal mdio_s : std_logic;
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signal mdc_s : std_logic;
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signal rx_crc : std_logic;
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signal rx_strb : std_logic;
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signal rx_data : std_logic_vector(7 downto 0);
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signal rx_eof : std_logic;
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signal rx_sof : std_logic;
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signal rx_mem : std_logic_vector(3 downto 0);
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signal tx_ack : std_logic;
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signal tx_data : std_logic_vector(7 downto 0);
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signal tx_eof : std_logic;
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signal tx_sof : std_logic;
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begin
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rst <= not rst_hw;
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@ -92,26 +92,27 @@ begin
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clockdiv => 30
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-- pragma synthesis_off
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/10
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-- pragma synthesis_on
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)
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-- pragma synthesis_on
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)
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port map(
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clk_i => clk_tx,
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rst_i => rst,
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mdio_io => mdio_s,
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mdc_o => mdc_s,
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busy_o => smi_busy_s,
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data_o => open,
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phyaddr_i => "00001",
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regaddr_i => regaddr_s,
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data_i => smi_data_s,
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strb_i => smi_strb_s,
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rw_i => '0'
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);
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clk_i => clk_tx,
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rst_i => rst,
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mdio_io => mdio_s,
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mdc_o => mdc_s,
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busy_o => smi_busy_s,
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data_o => open, -- ignore read outputs
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data_o_strb => open, -- ignore read outputs
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phyaddr_i => "00001",
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regaddr_i => regaddr_s,
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data_i => smi_data_s,
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strb_i => smi_strb_s,
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rw_i => '0' -- Fix for write operation
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);
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initphy : process(clk_tx, rst) is
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procedure sendsmi(regaddr : in std_logic_vector(4 downto 0);
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data : in std_logic_vector(15 downto 0);
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nextstate : in smiinit_t) is
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data : in std_logic_vector(15 downto 0);
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nextstate : in smiinit_t) is
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begin
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case sendstate is
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when IDLE =>
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@ -144,7 +145,7 @@ begin
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sendsmi((others => '0'), x"8000", DELAY);
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when DELAY =>
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delaycounter <= delaycounter + 1;
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if delaycounter = DELAYCNTVAL then -- Set to 100000
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if delaycounter = DELAYCNTVAL then -- Set to 100000
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initstate <= INIT;
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end if;
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when INIT =>
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@ -158,22 +159,22 @@ begin
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ethmac_rx_inst : entity work.ethmac_rx
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port map(
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clk_50 => clk_rx,
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rst => rst,
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rmii_rx => rmii_rx,
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rmii_dv => rmii_rxen,
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start_of_frame => rx_sof,
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end_of_frame => rx_eof,
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data_out => rx_data,
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data_strb => rx_strb,
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clk_50 => clk_rx,
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rst => rst,
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rmii_rx => rmii_rx,
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rmii_dv => rmii_rxen,
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start_of_frame => rx_sof,
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end_of_frame => rx_eof,
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data_out => rx_data,
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data_strb => rx_strb,
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crc_check_valid => rx_crc
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);
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);
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receiver : process(clk_rx, rst) is
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begin
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if rst = '1' then
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rx_state <= RXSOFWAIT;
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rx_mem <= (others => '0');
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rx_mem <= (others => '0');
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data_out <= (others => '0');
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elsif rising_edge(clk_rx) then
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case rx_state is
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@ -183,7 +184,7 @@ begin
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end if;
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when RXDATA =>
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if rx_strb = '1' then
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rx_mem <= rx_data(3 downto 0);
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rx_mem <= rx_data(3 downto 0);
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rx_state <= RXCRCCHECK;
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end if;
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when RXCRCCHECK =>
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@ -199,17 +200,17 @@ begin
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ethmac_tx_inst : entity work.ethmac_tx
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port map(
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clk_50 => clk_tx,
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rst => rst,
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clk_50 => clk_tx,
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rst => rst,
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tx_ready => open,
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start_of_frame => tx_sof,
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end_of_frame => tx_eof,
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data_in => tx_data,
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data_in => tx_data,
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data_ack => tx_ack,
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abort => '0',
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rmii_tx => rmii_tx,
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abort => '0',
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rmii_tx => rmii_tx,
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rmii_txen => rmii_txen
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);
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);
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sender : process(clk_tx, rst_rxtx) is
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variable dummycnt : integer range 0 to 511 := 0;
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@ -217,26 +218,26 @@ begin
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begin
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if rst_rxtx = '1' then
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tx_state <= TXWAIT;
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tx_sof <= '0';
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tx_eof <= '0';
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tx_data <= x"00";
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tx_sof <= '0';
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tx_eof <= '0';
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tx_data <= x"00";
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dummycnt := 0;
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elsif rising_edge(clk_tx) then
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case tx_state is
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when TXWAIT =>
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tx_sof <= '1';
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tx_sof <= '1';
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tx_state <= TXSEND;
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tx_data <= "0000" & data_in;
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tx_data <= "0000" & data_in;
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dummycnt := 0;
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when TXSEND =>
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if tx_ack = '1' then
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tx_sof <= '0';
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tx_sof <= '0';
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dummycnt := dummycnt + 1;
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if dummycnt = 500 then
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tx_eof <= '1';
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end if;
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if dummycnt = 501 then
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tx_eof <= '0';
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tx_eof <= '0';
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tx_state <= TXWAIT;
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end if;
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end if;
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132
design/smi.vhd
132
design/smi.vhd
@ -2,7 +2,7 @@
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-- Title : SMI (MDIO)
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-- Project : EthMAC
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-------------------------------------------------------------------------------
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-- File : design/smi.vhd
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-- File : design/smi.vhd
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-- Author : Mario Hüttel <mario.huettel@gmx.net>
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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@ -18,7 +18,7 @@
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--
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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@ -32,49 +32,49 @@ use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Implementation of the SMI
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-- Only write Access implemented
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-- I think i won't implement read access because.........IT'S FUCKING USELESS
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entity smi is
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generic(
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clockdiv : integer := 64
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);
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);
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port(
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clk_i : in std_logic;
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rst_i : in std_logic;
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mdio_io : inout std_logic;
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mdc_o : out std_logic;
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busy_o : out std_logic;
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data_o : out std_logic_vector(15 downto 0);
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phyaddr_i : std_logic_vector(4 downto 0);
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regaddr_i : std_logic_vector(4 downto 0);
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data_i : in std_logic_vector(15 downto 0);
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strb_i : in std_logic;
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rw_i : in std_logic --Read/write. 0=write, 1=read
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);
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clk_i : in std_logic;
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rst_i : in std_logic;
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mdio_io : inout std_logic;
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mdc_o : out std_logic;
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busy_o : out std_logic;
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data_o : out std_logic_vector(15 downto 0);
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data_o_strb : out std_logic;
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phyaddr_i : std_logic_vector(4 downto 0);
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regaddr_i : std_logic_vector(4 downto 0);
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data_i : in std_logic_vector(15 downto 0);
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strb_i : in std_logic;
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rw_i : in std_logic --Read/write. 0=write, 1=read
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);
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end entity smi;
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architecture RTL of smi is
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type smistate_t is (IDLE, PRE, SOF, OPC, PHYADDR, REGADDR, TURN, DATA, CONCL);
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signal state_s : smistate_t;
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signal state_s : smistate_t;
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signal fedge_strb_s : std_logic;
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signal datashift_s : std_logic_vector(15 downto 0);
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signal regaddr_s : std_logic_vector(4 downto 0);
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signal phyaddr_s : std_logic_vector(4 downto 0);
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signal bitcounter_s : integer range 0 to 32;
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signal mdc_o_s : std_logic;
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signal mdc_o_s : std_logic;
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signal rw_latched : std_logic;
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begin
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mdc_o <= mdc_o_s;
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div : process(clk_i, rst_i) is
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variable counter : integer := 0;
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begin
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if rst_i = '1' then
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fedge_strb_s <= '0';
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counter := 0;
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mdc_o_s <= '0';
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counter := 0;
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mdc_o_s <= '0';
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elsif rising_edge(clk_i) then
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fedge_strb_s <= '0';
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counter := counter + 1;
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counter := counter + 1;
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if counter = clockdiv then
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mdc_o_s <= not mdc_o_s;
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counter := 0;
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@ -88,39 +88,49 @@ begin
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smishift : process(clk_i, rst_i) is
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begin
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if rst_i = '1' then
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mdio_io <= '1';
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state_s <= IDLE;
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busy_o <= '1';
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mdio_io <= '1';
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state_s <= IDLE;
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rw_latched <= '0';
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phyaddr_s <= (others => '0');
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regaddr_s <= (others => '0');
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datashift_s <= (others => '0');
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busy_o <= '1';
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data_o_strb <= '0';
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elsif rising_edge(clk_i) then
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busy_o <= '1';
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busy_o <= '1';
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data_o_strb <= '0';
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if state_s = IDLE then
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mdio_io <= '1';
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busy_o <= '0';
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mdio_io <= '1';
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busy_o <= '0';
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bitcounter_s <= 0;
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if (strb_i = '1') then
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state_s <= PRE;
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busy_o <= '1';
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state_s <= PRE;
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busy_o <= '1';
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--Load data
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phyaddr_s <= phyaddr_i;
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regaddr_s <= regaddr_i;
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datashift_s <= data_i;
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rw_latched <= rw_i;
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end if;
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elsif state_s = CONCL then -- Wait for falling edge to
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-- force output high after
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-- read
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if fedge_strb_s = '1' then
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mdio_io <= '1';
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busy_o <= '0';
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state_s <= IDLE;
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bitcounter_s <= 0;
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end if;
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elsif state_s = CONCL then
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mdio_io <= '1';
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busy_o <= '0';
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state_s <= IDLE;
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bitcounter_s <= 0;
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elsif fedge_strb_s = '1' then
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mdio_io <= '1';
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mdio_io <= '1';
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bitcounter_s <= bitcounter_s + 1;
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case state_s is
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when PRE =>
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if fedge_strb_s = '1' then
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--Mdio idle high for 32 cycles
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--Mdio idle high for 32 cycles
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if (bitcounter_s = 31) then
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bitcounter_s <= 0;
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state_s <= SOF;
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state_s <= SOF;
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end if;
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end if;
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when SOF =>
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@ -128,19 +138,19 @@ begin
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mdio_io <= '0';
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elsif bitcounter_s = 1 then
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bitcounter_s <= 0;
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--Mdio idle high
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state_s <= OPC;
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--Mdio idle high
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state_s <= OPC;
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end if;
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when OPC => --Write OPCODE
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when OPC => --Write OPCODE
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if bitcounter_s = 0 then
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if rw_i = '1' then
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if rw_latched = '1' then
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mdio_io <= '1';
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else
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mdio_io <= '0';
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end if;
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elsif bitcounter_s = 1 then
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bitcounter_s <= 0;
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if rw_i = '1' then
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if rw_latched = '1' then
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mdio_io <= '0';
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else
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mdio_io <= '1';
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@ -150,44 +160,46 @@ begin
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when PHYADDR =>
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if bitcounter_s = 4 then
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bitcounter_s <= 0;
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state_s <= REGADDR;
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state_s <= REGADDR;
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end if;
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mdio_io <= phyaddr_s(4);
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mdio_io <= phyaddr_s(4);
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phyaddr_s <= phyaddr_s(3 downto 0) & '0';
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when REGADDR =>
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if bitcounter_s = 4 then
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bitcounter_s <= 0;
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state_s <= TURN;
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state_s <= TURN;
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end if;
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mdio_io <= regaddr_s(4);
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mdio_io <= regaddr_s(4);
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regaddr_s <= regaddr_s(3 downto 0) & '0';
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when TURN =>
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if rw_i = '1' then
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||||
when TURN => -- Turn MDIO to input
|
||||
if rw_latched = '1' then
|
||||
mdio_io <= 'Z';
|
||||
end if;
|
||||
if bitcounter_s = 1 then
|
||||
bitcounter_s <= 0;
|
||||
state_s <= DATA;
|
||||
state_s <= DATA;
|
||||
end if;
|
||||
when DATA =>
|
||||
if bitcounter_s = 15 then
|
||||
bitcounter_s <= 0;
|
||||
state_s <= CONCL;
|
||||
state_s <= CONCL;
|
||||
if rw_latched = '1' then
|
||||
data_o_strb <= '1';
|
||||
end if;
|
||||
end if;
|
||||
if rw_i = '1' then
|
||||
mdio_io <= 'Z';
|
||||
--Not implemented => =>
|
||||
else
|
||||
mdio_io <= datashift_s(15);
|
||||
if rw_latched = '1' then -- read data
|
||||
mdio_io <= 'Z';
|
||||
datashift_s <= datashift_s(14 downto 0) & mdio_io;
|
||||
else -- write data
|
||||
mdio_io <= datashift_s(15);
|
||||
datashift_s <= datashift_s(14 downto 0) & '0';
|
||||
end if;
|
||||
when others =>
|
||||
null; -- This should not happen
|
||||
null; -- This should not happen
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process smishift;
|
||||
|
||||
data_o <= (others => '0');
|
||||
|
||||
end architecture RTL;
|
||||
|
Loading…
Reference in New Issue
Block a user