Add read support to SMI

design/led-demo.vhd

@@ -52,7 +52,7 @@ architecture RTL of leddemo is
 					-- pragma synthesis_off
 					  /50000
 					-- pragma synthesis_on
-	;
+;
 
 	type smisend_t is (IDLE, STROBE);
 	type rx_state_t is (RXSOFWAIT, RXDATA, RXCRCCHECK);
@@ -100,12 +100,13 @@ begin
 			mdio_io	    => mdio_s,
 			mdc_o	    => mdc_s,
 			busy_o	    => smi_busy_s,
-			data_o    => open,
+			data_o	    => open,  -- ignore read outputs
+			data_o_strb => open,  -- ignore read outputs 
 			phyaddr_i   => "00001",
 			regaddr_i   => regaddr_s,
 			data_i	    => smi_data_s,
 			strb_i	    => smi_strb_s,
-			rw_i      => '0'
+			rw_i	    => '0'  -- Fix for write operation
 			);
 
 	initphy : process(clk_tx, rst) is

design/smi.vhd

@@ -32,8 +32,6 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 -- Implementation of the SMI
--- Only write Access implemented
--- I think i won't implement read access because.........IT'S FUCKING USELESS
 entity smi is
 	generic(
 		clockdiv : integer := 64
@@ -45,6 +43,7 @@ entity smi is
 		mdc_o	    : out   std_logic;
 		busy_o	    : out   std_logic;
 		data_o	    : out   std_logic_vector(15 downto 0);
+		data_o_strb : out   std_logic;
 		phyaddr_i   :	    std_logic_vector(4 downto 0);
 		regaddr_i   :	    std_logic_vector(4 downto 0);
 		data_i	    : in    std_logic_vector(15 downto 0);
@@ -62,6 +61,7 @@ architecture RTL of smi is
 	signal phyaddr_s    : std_logic_vector(4 downto 0);
 	signal bitcounter_s : integer range 0 to 32;
 	signal mdc_o_s	    : std_logic;
+	signal rw_latched   : std_logic;
 begin
 	mdc_o <= mdc_o_s;
 
@@ -90,10 +90,15 @@ begin
 		if rst_i = '1' then
 			mdio_io	    <= '1';
 			state_s	    <= IDLE;
-
+			rw_latched  <= '0';
+			phyaddr_s   <= (others => '0');
+			regaddr_s   <= (others => '0');
+			datashift_s <= (others => '0');
 			busy_o	    <= '1';
+			data_o_strb <= '0';
 		elsif rising_edge(clk_i) then
 			busy_o	    <= '1';
+			data_o_strb <= '0';
 			if state_s = IDLE then
 				mdio_io	     <= '1';
 				busy_o	     <= '0';
@@ -105,12 +110,17 @@ begin
 					phyaddr_s   <= phyaddr_i;
 					regaddr_s   <= regaddr_i;
 					datashift_s <= data_i;
+					rw_latched  <= rw_i;
 				end if;
-			elsif state_s = CONCL then
+			elsif state_s = CONCL then  -- Wait for falling edge to
+						    -- force output high after
+						    -- read
+				if fedge_strb_s = '1' then
 					mdio_io	     <= '1';
 					busy_o	     <= '0';
 					state_s	     <= IDLE;
 					bitcounter_s <= 0;
+				end if;
 			elsif fedge_strb_s = '1' then
 				mdio_io	     <= '1';
 				bitcounter_s <= bitcounter_s + 1;
@@ -133,14 +143,14 @@ begin
 						end if;
 					when OPC =>    --Write OPCODE
 						if bitcounter_s = 0 then
-							if rw_i = '1' then
+							if rw_latched = '1' then
 								mdio_io <= '1';
 							else
 								mdio_io <= '0';
 							end if;
 						elsif bitcounter_s = 1 then
 							bitcounter_s <= 0;
-							if rw_i = '1' then
+							if rw_latched = '1' then
 								mdio_io <= '0';
 							else
 								mdio_io <= '1';
@@ -161,8 +171,8 @@ begin
 						end if;
 						mdio_io	  <= regaddr_s(4);
 						regaddr_s <= regaddr_s(3 downto 0) & '0';
-					when TURN =>
+					when TURN =>   -- Turn MDIO to input
-						if rw_i = '1' then
+						if rw_latched = '1' then
 							mdio_io <= 'Z';
 						end if;
 						if bitcounter_s = 1 then
@@ -173,11 +183,14 @@ begin
 						if bitcounter_s = 15 then
 							bitcounter_s <= 0;
 							state_s	     <= CONCL;
+							if rw_latched = '1' then
+								data_o_strb <= '1';
 							end if;
-						if rw_i = '1' then
+						end if;
+						if rw_latched = '1' then  -- read data
 							mdio_io	    <= 'Z';
-						--Not implemented =>  => 
+							datashift_s <= datashift_s(14 downto 0) & mdio_io;
-						else
+						else   -- write data
 							mdio_io	    <= datashift_s(15);
 							datashift_s <= datashift_s(14 downto 0) & '0';
 						end if;
@@ -188,6 +201,5 @@ begin
 		end if;
 	end process smishift;
 
-	data_o <= (others => '0');
 
 end architecture RTL;