Make design MII compatible
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commit
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3
.gitignore
vendored
3
.gitignore
vendored
@ -2,4 +2,5 @@
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quartus
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quartus
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diamond
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diamond
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*.bak
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*.bak
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sim/*
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*.vhd~
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@ -2,7 +2,7 @@
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-- Title : Bench for Ethernet RX Core
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-- Title : Bench for Ethernet RX Core
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-- Project : EthMAC
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-- Project : EthMAC
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- File : bench/bench_ethmac_rx.vhd
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-- File : bench/bench_ethmac_rx.vhd
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-- Author : Mario Hüttel <mario.huettel@gmx.net>
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-- Author : Mario Hüttel <mario.huettel@gmx.net>
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-- Standard : VHDL'93/02
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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@ -18,7 +18,7 @@
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--
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--
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-- This code is distributed in the hope that it will be useful,
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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-- GNU General Public License for more details.
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--
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--
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-- You should have received a copy of the GNU General Public License
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-- You should have received a copy of the GNU General Public License
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@ -37,22 +37,22 @@ entity bench_ethmac_rx is
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end entity bench_ethmac_rx;
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end entity bench_ethmac_rx;
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architecture RTL of bench_ethmac_rx is
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architecture RTL of bench_ethmac_rx is
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signal clk_hw : std_logic;
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signal clk_hw : std_logic;
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signal rst_hw : std_logic;
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signal rst_hw : std_logic;
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signal dv_i : std_logic;
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signal dv_i : std_logic;
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signal rxd_i : std_logic_vector(1 downto 0);
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signal rxd_i : std_logic_vector(1 downto 0);
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signal rst : std_logic;
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signal rst : std_logic;
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signal start_of_frame : std_logic;
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signal start_of_frame : std_logic;
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signal end_of_frame : std_logic;
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signal end_of_frame : std_logic;
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signal data_out : std_logic_vector(7 downto 0);
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signal data_out : std_logic_vector(7 downto 0);
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signal data_strb : std_logic;
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signal data_strb : std_logic;
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signal crc_check_valid : std_logic;
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signal crc_check_valid : std_logic;
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signal clock_fcs : std_logic;
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signal clock_fcs : std_logic;
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signal crc : std_logic_vector(7 downto 0);
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signal crc : std_logic_vector(7 downto 0);
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signal dvalid : std_logic;
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signal dvalid : std_logic;
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signal calc : std_logic;
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signal calc : std_logic;
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signal fcs_init : std_logic;
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signal fcs_init : std_logic;
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signal fcs_dat : std_logic_vector(7 downto 0);
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signal fcs_dat : std_logic_vector(7 downto 0);
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begin
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begin
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rst <= not rst_hw;
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rst <= not rst_hw;
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@ -66,29 +66,33 @@ begin
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end process clock_driver;
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end process clock_driver;
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ethmac_rx_inst : entity design.ethmac_rx
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ethmac_rx_inst : entity design.ethmac_rx
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port map(
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generic map (
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clk_50 => clk_hw,
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IFACE_WIDTH => 2);
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rst => rst,
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port map(
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rmii_rx => rxd_i,
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clk_50 => clk_hw,
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rmii_dv => dv_i,
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rst => rst,
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start_of_frame => start_of_frame,
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rmii_rx => rxd_i,
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end_of_frame => end_of_frame,
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rmii_dv => dv_i,
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data_out => data_out,
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start_of_frame => start_of_frame,
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data_strb => data_strb,
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end_of_frame => end_of_frame,
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crc_check_valid => crc_check_valid
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data_out => data_out,
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data_strb => data_strb,
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crc_check_valid => crc_check_valid
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);
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);
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ethfcs_inst : entity design.ethfcs
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ethfcs_inst : entity design.ethfcs
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port map(
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generic map (
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CLOCK => clock_fcs,
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IFACE_WIDTH => 2);
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RESET => rst,
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port map(
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DATA => fcs_dat,
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CLOCK => clock_fcs,
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LOAD_INIT => fcs_init,
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RESET => rst,
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CALC => calc,
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DATA => fcs_dat,
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D_VALID => dvalid,
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LOAD_INIT => fcs_init,
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CRC => crc,
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CALC => calc,
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CRC_REG => open,
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D_VALID => dvalid,
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CRC_VALID => open
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CRC => crc,
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CRC_REG => open,
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CRC_VALID => open
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);
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);
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sendphy : process is
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sendphy : process is
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@ -106,13 +110,13 @@ begin
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end procedure sendRMII;
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end procedure sendRMII;
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begin
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begin
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rst_hw <= '0';
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rst_hw <= '0';
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dv_i <= '0';
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dv_i <= '0';
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rxd_i <= "00";
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rxd_i <= "00";
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calc <= '0';
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calc <= '0';
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fcs_dat <= x"00";
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fcs_dat <= x"00";
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wait for 2 ns;
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wait for 2 ns;
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rst_hw <= '1';
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rst_hw <= '1';
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fcs_init <= '1';
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fcs_init <= '1';
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wait for 50 ns;
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wait for 50 ns;
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fcs_init <= '0';
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fcs_init <= '0';
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744
bench/bench_ethmac_tx_rx_mii.vhd
Normal file
744
bench/bench_ethmac_tx_rx_mii.vhd
Normal file
@ -0,0 +1,744 @@
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-------------------------------------------------------------------------------
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-- Title : Bench for Ethernet TX and RX Core
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-- Project : EthMAC
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-------------------------------------------------------------------------------
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-- File : design/ethmac_tx_rx.vhd
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-- Author : Mario Hüttel <mario.huettel@gmx.net>
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: Testbench for communication between TX and RX core.
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-------------------------------------------------------------------------------
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-- Copyright (c) 2016
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--
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-- This file is part of EthMAC.
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--
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-- EthMAC is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, version 2 of the License.
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--
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this code. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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library ieee;
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library design;
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use design.all;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity bench_ethmac_tx_rx_mii is
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end entity bench_ethmac_tx_rx_mii;
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architecture bench of bench_ethmac_tx_rx_mii is
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signal clk : std_logic;
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signal data_in : std_logic_vector(7 downto 0) := (others => '0');
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signal end_of_frame : std_logic := '0';
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signal data_ack : std_logic;
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signal start_of_frame : std_logic := '0';
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signal rst : std_logic;
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signal tx_ready : std_logic;
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signal rmii_tx : std_logic_vector(3 downto 0);
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signal rmii_txen : std_logic;
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signal data_out : std_logic_vector(7 downto 0);
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signal data_strb : std_logic;
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signal crc_check_valid : std_logic;
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signal end_of_frame_rx : std_logic;
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signal start_of_frame_rx : std_logic;
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begin
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clock_driver : process
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constant period : time := 40 ns;
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begin
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clk <= '0';
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wait for period / 2;
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clk <= '1';
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wait for period / 2;
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end process clock_driver;
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ethmac_tx_inst : entity design.ethmac_tx
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generic map(
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IFACE_WIDTH => 4)
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port map(
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clk_50 => clk,
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rst => rst,
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tx_ready => tx_ready,
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start_of_frame => start_of_frame,
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end_of_frame => end_of_frame,
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data_in => data_in,
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data_ack => data_ack,
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abort => '0',
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rmii_tx => rmii_tx,
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rmii_txen => rmii_txen
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);
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ethmac_rx_inst : entity design.ethmac_rx
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generic map(
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IFACE_WIDTH => 4)
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port map(
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clk_50 => clk,
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rst => rst,
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rmii_rx => rmii_tx,
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rmii_dv => rmii_txen,
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start_of_frame => start_of_frame_rx,
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end_of_frame => end_of_frame_rx,
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data_out => data_out,
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data_strb => data_strb,
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crc_check_valid => crc_check_valid
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);
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sendpkg : process is
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procedure sendByte(byte : std_logic_vector(7 downto 0); last : std_logic) is
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begin
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wait until rising_edge(clk);
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data_in <= byte;
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end_of_frame <= last;
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wait until data_ack = '1';
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end procedure sendByte;
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begin
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rst <= '1';
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wait for 5 ns;
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rst <= '0';
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wait for 20 ns;
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start_of_frame <= '1';
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sendByte(x"FF", '0');
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start_of_frame <= '0';
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sendByte(x"DE", '0');
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sendByte(x"AD", '0');
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sendByte(x"BE", '0');
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sendByte(x"EF", '0');
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sendByte(x"00", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"03", '0');
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sendByte(x"04", '0');
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sendByte(x"05", '0');
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sendByte(x"06", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"AA", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"DE", '0');
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sendByte(x"AD", '0');
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sendByte(x"BE", '0');
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sendByte(x"EF", '0');
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sendByte(x"00", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"03", '0');
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sendByte(x"EF", '0');
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sendByte(x"00", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"03", '0');
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sendByte(x"04", '0');
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sendByte(x"05", '0');
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sendByte(x"06", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"AA", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"DE", '0');
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sendByte(x"AD", '0');
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sendByte(x"BE", '0');
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sendByte(x"EF", '0');
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sendByte(x"00", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"03", '0');
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sendByte(x"04", '0');
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sendByte(x"05", '0');
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sendByte(x"06", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"AA", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"DE", '0');
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sendByte(x"AD", '0');
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sendByte(x"BE", '0');
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sendByte(x"EF", '0');
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sendByte(x"00", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"03", '0');
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sendByte(x"04", '0');
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sendByte(x"05", '0');
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sendByte(x"06", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"AA", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"DE", '0');
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sendByte(x"AD", '0');
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sendByte(x"BE", '0');
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sendByte(x"EF", '0');
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sendByte(x"00", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"03", '0');
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sendByte(x"04", '0');
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sendByte(x"05", '0');
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sendByte(x"06", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"AA", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"EF", '0');
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sendByte(x"00", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"03", '0');
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sendByte(x"04", '0');
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sendByte(x"05", '0');
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sendByte(x"06", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"AA", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"DE", '0');
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sendByte(x"AD", '0');
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sendByte(x"BE", '0');
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sendByte(x"EF", '0');
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sendByte(x"00", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"03", '0');
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sendByte(x"04", '0');
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sendByte(x"05", '0');
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sendByte(x"06", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"AA", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"DE", '0');
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sendByte(x"AD", '0');
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sendByte(x"BE", '0');
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sendByte(x"EF", '0');
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sendByte(x"00", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"03", '0');
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sendByte(x"04", '0');
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sendByte(x"05", '0');
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sendByte(x"06", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"AA", '0');
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sendByte(x"01", '0');
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sendByte(x"02", '0');
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sendByte(x"DE", '0');
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sendByte(x"AD", '0');
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sendByte(x"BE", '0');
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sendByte(x"EF", '0');
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sendByte(x"00", '0');
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||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '1');
|
||||||
|
wait for 100 ns;
|
||||||
|
end_of_frame <= '0';
|
||||||
|
wait for 1 us;
|
||||||
|
start_of_frame <= '1';
|
||||||
|
sendByte(x"FF", '0');
|
||||||
|
start_of_frame <= '0';
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '1');
|
||||||
|
|
||||||
|
wait for 100 ns;
|
||||||
|
end_of_frame <= '0';
|
||||||
|
wait for 1 us;
|
||||||
|
start_of_frame <= '1';
|
||||||
|
sendByte(x"FF", '0');
|
||||||
|
start_of_frame <= '0';
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '1');
|
||||||
|
|
||||||
|
wait for 100 ns;
|
||||||
|
end_of_frame <= '0';
|
||||||
|
wait for 1 us;
|
||||||
|
start_of_frame <= '1';
|
||||||
|
sendByte(x"FF", '0');
|
||||||
|
start_of_frame <= '0';
|
||||||
|
sendByte(x"DE", '0');
|
||||||
|
sendByte(x"AD", '0');
|
||||||
|
sendByte(x"BE", '0');
|
||||||
|
sendByte(x"EF", '0');
|
||||||
|
sendByte(x"00", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '0');
|
||||||
|
sendByte(x"04", '0');
|
||||||
|
sendByte(x"05", '0');
|
||||||
|
sendByte(x"06", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"AA", '0');
|
||||||
|
sendByte(x"01", '0');
|
||||||
|
sendByte(x"02", '0');
|
||||||
|
sendByte(x"03", '1');
|
||||||
|
wait;
|
||||||
|
end process sendpkg;
|
||||||
|
|
||||||
|
end architecture bench;
|
@ -1,63 +0,0 @@
|
|||||||
[*]
|
|
||||||
[*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI
|
|
||||||
[*] Tue Jan 31 10:51:17 2017
|
|
||||||
[*]
|
|
||||||
[dumpfile] "/tmp/SigasiCompileCache5252176646134126361/ethmac/mentor/bench_ethmac_rx.ghw"
|
|
||||||
[dumpfile_mtime] "Tue Jan 31 10:48:01 2017"
|
|
||||||
[dumpfile_size] 18590
|
|
||||||
[savefile] "/home/mari/projects/fpga/workspace/ethmac/bench_ethmac_rx.gtkw"
|
|
||||||
[timestart] 0
|
|
||||||
[size] 2880 1508
|
|
||||||
[pos] -1 -1
|
|
||||||
*-26.724226 2752900000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
|
||||||
[treeopen] top.
|
|
||||||
[treeopen] top.bench_ethmac_rx.
|
|
||||||
[treeopen] top.bench_ethmac_rx.ethmac_rx_inst.
|
|
||||||
[treeopen] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo.
|
|
||||||
[treeopen] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.
|
|
||||||
[sst_width] 287
|
|
||||||
[signals_width] 283
|
|
||||||
[sst_expanded] 1
|
|
||||||
[sst_vpaned_height] 445
|
|
||||||
@28
|
|
||||||
top.bench_ethmac_rx.rst
|
|
||||||
top.bench_ethmac_rx.end_of_frame
|
|
||||||
top.bench_ethmac_rx.start_of_frame
|
|
||||||
top.bench_ethmac_rx.clk_hw
|
|
||||||
top.bench_ethmac_rx.dv_i
|
|
||||||
top.bench_ethmac_rx.crc_check_valid
|
|
||||||
#{top.bench_ethmac_rx.rxd_i[1:0]} top.bench_ethmac_rx.rxd_i[1] top.bench_ethmac_rx.rxd_i[0]
|
|
||||||
top.bench_ethmac_rx.ethmac_rx_inst.framestate
|
|
||||||
@200
|
|
||||||
-
|
|
||||||
-
|
|
||||||
-
|
|
||||||
@28
|
|
||||||
top.bench_ethmac_rx.data_strb
|
|
||||||
@22
|
|
||||||
#{top.bench_ethmac_rx.data_out[7:0]} top.bench_ethmac_rx.data_out[7] top.bench_ethmac_rx.data_out[6] top.bench_ethmac_rx.data_out[5] top.bench_ethmac_rx.data_out[4] top.bench_ethmac_rx.data_out[3] top.bench_ethmac_rx.data_out[2] top.bench_ethmac_rx.data_out[1] top.bench_ethmac_rx.data_out[0]
|
|
||||||
#{top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][7:0]} top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][7] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][6] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][5] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][4] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][3] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][2] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][1] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][0]
|
|
||||||
#{top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][7:0]} top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][7] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][6] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][5] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][4] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][3] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][2] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][1] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][0]
|
|
||||||
#{top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][7:0]} top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][7] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][6] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][5] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][4] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][3] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][2] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][1] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][0]
|
|
||||||
@28
|
|
||||||
top.bench_ethmac_rx.ethmac_rx_inst.data_delay_truncate
|
|
||||||
top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in_strb
|
|
||||||
@22
|
|
||||||
#{top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[7:0]} top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[7] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[6] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[5] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[4] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[3] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[2] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[1] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[0]
|
|
||||||
@200
|
|
||||||
-
|
|
||||||
@29
|
|
||||||
top.bench_ethmac_rx.clk_hw
|
|
||||||
@200
|
|
||||||
-
|
|
||||||
@28
|
|
||||||
top.bench_ethmac_rx.ethmac_rx_inst.crc_data_valid
|
|
||||||
top.bench_ethmac_rx.ethmac_rx_inst.crc_calc_en
|
|
||||||
top.bench_ethmac_rx.ethmac_rx_inst.crc_init
|
|
||||||
top.bench_ethmac_rx.ethmac_rx_inst.crc_valid
|
|
||||||
top.bench_ethmac_rx.ethmac_rx_inst.crc_check_valid
|
|
||||||
@22
|
|
||||||
#{top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[7:0]} top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[7] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[6] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[5] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[4] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[3] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[2] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[1] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[0]
|
|
||||||
#{top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31:0]} top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[30] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[29] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[28] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[27] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[26] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[25] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[24] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[23] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[22] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[21] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[20] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[19] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[18] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[17] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[16] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[15] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[14] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[13] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[12] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[11] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[10] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[9] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[8] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[7] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[6] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[5] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[4] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[3] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[2] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[1] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[0]
|
|
||||||
[pattern_trace] 1
|
|
||||||
[pattern_trace] 0
|
|
@ -1,42 +0,0 @@
|
|||||||
[*]
|
|
||||||
[*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI
|
|
||||||
[*] Tue Jan 31 17:38:47 2017
|
|
||||||
[*]
|
|
||||||
[dumpfile] "/tmp/SigasiCompileCache7754218395000362562/ethmac/mentor/bench_ethmac_tx.ghw"
|
|
||||||
[dumpfile_mtime] "Tue Jan 31 17:37:54 2017"
|
|
||||||
[dumpfile_size] 13513
|
|
||||||
[savefile] "/home/mari/projects/fpga/workspace/ethmac/bench_ethmac_tx.gtkw"
|
|
||||||
[timestart] 489830000
|
|
||||||
[size] 2880 1508
|
|
||||||
[pos] -1 -1
|
|
||||||
*-23.703266 1550000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
|
||||||
[treeopen] top.
|
|
||||||
[treeopen] top.bench_ethmac_tx.
|
|
||||||
[treeopen] top.bench_ethmac_tx.ethmac_tx_inst.
|
|
||||||
[sst_width] 287
|
|
||||||
[signals_width] 250
|
|
||||||
[sst_expanded] 1
|
|
||||||
[sst_vpaned_height] 445
|
|
||||||
@28
|
|
||||||
top.bench_ethmac_tx.rst
|
|
||||||
@29
|
|
||||||
top.bench_ethmac_tx.clk
|
|
||||||
@28
|
|
||||||
#{top.bench_ethmac_tx.rmii_tx[1:0]} top.bench_ethmac_tx.rmii_tx[1] top.bench_ethmac_tx.rmii_tx[0]
|
|
||||||
top.bench_ethmac_tx.tx_ready
|
|
||||||
top.bench_ethmac_tx.rmii_txen
|
|
||||||
top.bench_ethmac_tx.abort
|
|
||||||
top.bench_ethmac_tx.ethmac_tx_inst.tx_state
|
|
||||||
top.bench_ethmac_tx.ethmac_tx_inst.byte_counter_disable
|
|
||||||
top.bench_ethmac_tx.ethmac_tx_inst.byte_counter
|
|
||||||
@200
|
|
||||||
-
|
|
||||||
-
|
|
||||||
@28
|
|
||||||
top.bench_ethmac_tx.ethmac_tx_inst.crc_init
|
|
||||||
top.bench_ethmac_tx.ethmac_tx_inst.crc_calc
|
|
||||||
top.bench_ethmac_tx.ethmac_tx_inst.crc_data_valid
|
|
||||||
@22
|
|
||||||
#{top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[7:0]} top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[7] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[6] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[5] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[4] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[3] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[2] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[1] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[0]
|
|
||||||
[pattern_trace] 1
|
|
||||||
[pattern_trace] 0
|
|
@ -1,130 +0,0 @@
|
|||||||
[*]
|
|
||||||
[*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI
|
|
||||||
[*] Wed Feb 1 16:36:58 2017
|
|
||||||
[*]
|
|
||||||
[dumpfile] "/tmp/SigasiCompileCache2061063648462684657/ethmac/mentor/bench_ethmac_tx_rx.ghw"
|
|
||||||
[dumpfile_mtime] "Wed Feb 1 16:34:58 2017"
|
|
||||||
[dumpfile_size] 313392
|
|
||||||
[savefile] "/home/mari/projects/fpga/workspace/ethmac/bench_ethmac_tx_rx.gtkw"
|
|
||||||
[timestart] 46144000000
|
|
||||||
[size] 2880 1508
|
|
||||||
[pos] -1 -1
|
|
||||||
*-26.708954 46844900000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
|
||||||
[treeopen] top.
|
|
||||||
[treeopen] top.bench_ethmac_tx_rx.
|
|
||||||
[treeopen] top.bench_ethmac_tx_rx.ethmac_rx_inst.
|
|
||||||
[treeopen] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo.
|
|
||||||
[treeopen] top.bench_ethmac_tx_rx.ethmac_tx_inst.
|
|
||||||
[sst_width] 287
|
|
||||||
[signals_width] 283
|
|
||||||
[sst_expanded] 1
|
|
||||||
[sst_vpaned_height] 445
|
|
||||||
@28
|
|
||||||
top.bench_ethmac_tx_rx.clk
|
|
||||||
top.bench_ethmac_tx_rx.start_of_frame_rx
|
|
||||||
top.bench_ethmac_tx_rx.end_of_frame_rx
|
|
||||||
top.bench_ethmac_tx_rx.crc_check_valid
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.framestate
|
|
||||||
top.bench_ethmac_tx_rx.data_strb
|
|
||||||
@22
|
|
||||||
#{top.bench_ethmac_tx_rx.data_out[7:0]} top.bench_ethmac_tx_rx.data_out[7] top.bench_ethmac_tx_rx.data_out[6] top.bench_ethmac_tx_rx.data_out[5] top.bench_ethmac_tx_rx.data_out[4] top.bench_ethmac_tx_rx.data_out[3] top.bench_ethmac_tx_rx.data_out[2] top.bench_ethmac_tx_rx.data_out[1] top.bench_ethmac_tx_rx.data_out[0]
|
|
||||||
@200
|
|
||||||
-
|
|
||||||
@22
|
|
||||||
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][7] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][6] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][5] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][4] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][3] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][2] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][1] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][0]
|
|
||||||
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][7] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][6] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][5] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][4] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][3] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][2] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][1] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][0]
|
|
||||||
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][7] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][6] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][5] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][4] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][3] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][2] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][1] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][0]
|
|
||||||
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][7] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][6] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][5] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][4] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][3] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][2] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][1] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][0]
|
|
||||||
@28
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_truncate
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_in_strb
|
|
||||||
@200
|
|
||||||
-
|
|
||||||
-
|
|
||||||
@28
|
|
||||||
top.bench_ethmac_tx_rx.start_of_frame
|
|
||||||
top.bench_ethmac_tx_rx.end_of_frame
|
|
||||||
@22
|
|
||||||
#{top.bench_ethmac_tx_rx.data_in[7:0]} top.bench_ethmac_tx_rx.data_in[7] top.bench_ethmac_tx_rx.data_in[6] top.bench_ethmac_tx_rx.data_in[5] top.bench_ethmac_tx_rx.data_in[4] top.bench_ethmac_tx_rx.data_in[3] top.bench_ethmac_tx_rx.data_in[2] top.bench_ethmac_tx_rx.data_in[1] top.bench_ethmac_tx_rx.data_in[0]
|
|
||||||
@28
|
|
||||||
top.bench_ethmac_tx_rx.data_ack
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_tx_inst.tx_state
|
|
||||||
@22
|
|
||||||
#{top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[7:0]} top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[7] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[6] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[5] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[4] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[3] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[2] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[1] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[0]
|
|
||||||
@28
|
|
||||||
top.bench_ethmac_tx_rx.tx_ready
|
|
||||||
@200
|
|
||||||
-
|
|
||||||
@29
|
|
||||||
top.bench_ethmac_tx_rx.rst
|
|
||||||
@28
|
|
||||||
top.bench_ethmac_tx_rx.clk
|
|
||||||
#{top.bench_ethmac_tx_rx.rmii_tx[1:0]} top.bench_ethmac_tx_rx.rmii_tx[1] top.bench_ethmac_tx_rx.rmii_tx[0]
|
|
||||||
top.bench_ethmac_tx_rx.rmii_txen
|
|
||||||
@200
|
|
||||||
-
|
|
||||||
-
|
|
||||||
@28
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_tx_inst.crc_init
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_tx_inst.crc_data_valid
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_tx_inst.crc_calc
|
|
||||||
@200
|
|
||||||
-
|
|
||||||
-
|
|
||||||
@800022
|
|
||||||
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[31:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[31] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[30] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[29] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[28] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[27] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[26] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[25] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[24] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[23] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[22] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[21] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[20] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[19] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[18] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[17] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[16] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[15] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[14] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[13] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[12] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[11] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[10] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[9] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[8] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[7] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[6] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[5] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[4] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[3] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[2] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[1] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[0]
|
|
||||||
@28
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[31]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[30]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[29]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[28]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[27]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[26]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[25]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[24]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[23]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[22]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[21]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[20]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[19]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[18]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[17]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[16]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[15]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[14]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[13]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[12]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[11]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[10]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[9]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[8]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[7]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[6]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[5]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[4]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[3]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[2]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[1]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[0]
|
|
||||||
@1001200
|
|
||||||
-group_end
|
|
||||||
@22
|
|
||||||
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[30] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[29] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[28] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[27] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[26] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[25] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[24] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[23] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[22] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[21] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[20] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[19] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[18] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[17] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[16] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[15] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[14] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[13] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[12] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[11] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[10] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[9] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[8] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[7] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[6] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[5] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[4] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[3] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[2] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[1] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[0]
|
|
||||||
@c00022
|
|
||||||
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[7] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[6] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[5] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[4] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[3] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[2] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[1] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[0]
|
|
||||||
@28
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[7]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[6]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[5]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[4]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[3]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[2]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[1]
|
|
||||||
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[0]
|
|
||||||
@1401200
|
|
||||||
-group_end
|
|
||||||
@22
|
|
||||||
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[31:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[31] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[30] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[29] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[28] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[27] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[26] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[25] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[24] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[23] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[22] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[21] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[20] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[19] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[18] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[17] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[16] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[15] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[14] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[13] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[12] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[11] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[10] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[9] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[8] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[7] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[6] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[5] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[4] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[3] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[2] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[1] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[0]
|
|
||||||
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[7] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[6] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[5] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[4] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[3] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[2] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[1] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[0]
|
|
||||||
[pattern_trace] 1
|
|
||||||
[pattern_trace] 0
|
|
@ -1,93 +0,0 @@
|
|||||||
[*]
|
|
||||||
[*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI
|
|
||||||
[*] Tue Feb 7 21:51:10 2017
|
|
||||||
[*]
|
|
||||||
[dumpfile] "(null)"
|
|
||||||
[savefile] "/home/mari/projects/fpga/workspace/ethmac/bench_led_demo.gtkw"
|
|
||||||
[timestart] 103800000000
|
|
||||||
[size] 1920 1016
|
|
||||||
[pos] -1 -1
|
|
||||||
*-30.954296 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
|
||||||
[treeopen] top.
|
|
||||||
[treeopen] top.bench_led_demo.
|
|
||||||
[treeopen] top.bench_led_demo.leddemo_inst.
|
|
||||||
[treeopen] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.
|
|
||||||
[treeopen] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.
|
|
||||||
[treeopen] top.bench_led_demo.leddemo_inst.ethmac_tx_inst.
|
|
||||||
[sst_width] 289
|
|
||||||
[signals_width] 150
|
|
||||||
[sst_expanded] 1
|
|
||||||
[sst_vpaned_height] 284
|
|
||||||
@28
|
|
||||||
#{top.bench_led_demo.rmii_rx[1:0]} top.bench_led_demo.rmii_rx[1] top.bench_led_demo.rmii_rx[0]
|
|
||||||
@22
|
|
||||||
#{top.bench_led_demo.data_out[3:0]} top.bench_led_demo.data_out[3] top.bench_led_demo.data_out[2] top.bench_led_demo.data_out[1] top.bench_led_demo.data_out[0]
|
|
||||||
@28
|
|
||||||
#{top.bench_led_demo.mdc[1:0]} top.bench_led_demo.mdc[1] top.bench_led_demo.mdc[0]
|
|
||||||
top.bench_led_demo.clk
|
|
||||||
top.bench_led_demo.leddemo_inst.rst_rxtx
|
|
||||||
top.bench_led_demo.leddemo_inst.initstate
|
|
||||||
@200
|
|
||||||
-
|
|
||||||
-
|
|
||||||
-RX Module
|
|
||||||
@28
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.crc_valid
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.end_of_frame
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.start_of_frame
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.rmii_dv
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_strb
|
|
||||||
@22
|
|
||||||
#{top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[7:0]} top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[7] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[6] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[5] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[4] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[3] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[2] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[1] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[0]
|
|
||||||
@200
|
|
||||||
-
|
|
||||||
-
|
|
||||||
-TX Module
|
|
||||||
@22
|
|
||||||
#{top.bench_led_demo.leddemo_inst.tx_data[7:0]} top.bench_led_demo.leddemo_inst.tx_data[7] top.bench_led_demo.leddemo_inst.tx_data[6] top.bench_led_demo.leddemo_inst.tx_data[5] top.bench_led_demo.leddemo_inst.tx_data[4] top.bench_led_demo.leddemo_inst.tx_data[3] top.bench_led_demo.leddemo_inst.tx_data[2] top.bench_led_demo.leddemo_inst.tx_data[1] top.bench_led_demo.leddemo_inst.tx_data[0]
|
|
||||||
@28
|
|
||||||
top.bench_led_demo.leddemo_inst.tx_sof
|
|
||||||
top.bench_led_demo.leddemo_inst.tx_eof
|
|
||||||
top.bench_led_demo.leddemo_inst.tx_ack
|
|
||||||
top.bench_led_demo.leddemo_inst.tx_state
|
|
||||||
top.bench_led_demo.leddemo_inst.clk_tx
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_tx_inst.tx_state
|
|
||||||
@800023
|
|
||||||
#{top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31:0]} top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[30] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[29] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[28] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[27] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[26] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[25] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[24] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[23] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[22] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[21] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[20] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[19] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[18] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[17] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[16] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[15] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[14] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[13] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[12] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[11] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[10] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[9] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[8] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[7] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[6] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[5] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[4] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[3] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[2] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[1] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[0]
|
|
||||||
@29
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[30]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[29]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[28]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[27]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[26]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[25]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[24]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[23]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[22]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[21]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[20]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[19]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[18]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[17]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[16]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[15]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[14]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[13]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[12]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[11]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[10]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[9]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[8]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[7]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[6]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[5]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[4]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[3]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[2]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[1]
|
|
||||||
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[0]
|
|
||||||
@1001201
|
|
||||||
-group_end
|
|
||||||
[pattern_trace] 1
|
|
||||||
[pattern_trace] 0
|
|
@ -2,7 +2,7 @@
|
|||||||
-- Title : Ethernet RX Core
|
-- Title : Ethernet RX Core
|
||||||
-- Project : EthMAC
|
-- Project : EthMAC
|
||||||
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
||||||
-- File : design/ethmac_rx.vhd
|
-- File : design/ethmac_rx.vhd
|
||||||
-- Author : Mario Hüttel <mario.huettel@gmx.net>
|
-- Author : Mario Hüttel <mario.huettel@gmx.net>
|
||||||
-- Standard : VHDL'93/02
|
-- Standard : VHDL'93/02
|
||||||
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
||||||
@ -18,7 +18,7 @@
|
|||||||
--
|
--
|
||||||
-- This code is distributed in the hope that it will be useful,
|
-- This code is distributed in the hope that it will be useful,
|
||||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
-- GNU General Public License for more details.
|
-- GNU General Public License for more details.
|
||||||
--
|
--
|
||||||
-- You should have received a copy of the GNU General Public License
|
-- You should have received a copy of the GNU General Public License
|
||||||
@ -33,32 +33,38 @@ use ieee.std_logic_1164.all;
|
|||||||
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
||||||
|
|
||||||
entity ethmac_rx is
|
entity ethmac_rx is
|
||||||
|
generic(
|
||||||
|
IFACE_WIDTH : natural := 2);
|
||||||
port(
|
port(
|
||||||
clk_50 : in std_logic;
|
clk_50 : in std_logic;
|
||||||
rst : in std_logic;
|
rst : in std_logic;
|
||||||
rmii_rx : in std_logic_vector(1 downto 0);
|
rmii_rx : in std_logic_vector(IFACE_WIDTH - 1 downto 0);
|
||||||
rmii_dv : in std_logic;
|
rmii_dv : in std_logic;
|
||||||
start_of_frame : out std_logic;
|
start_of_frame : out std_logic;
|
||||||
end_of_frame : out std_logic;
|
end_of_frame : out std_logic;
|
||||||
data_out : out std_logic_vector(7 downto 0);
|
data_out : out std_logic_vector(7 downto 0);
|
||||||
data_strb : out std_logic;
|
data_strb : out std_logic;
|
||||||
crc_check_valid : out std_logic
|
crc_check_valid : out std_logic
|
||||||
);
|
);
|
||||||
end entity ethmac_rx;
|
end entity ethmac_rx;
|
||||||
|
|
||||||
architecture RTL of ethmac_rx is
|
architecture RTL of ethmac_rx is
|
||||||
|
|
||||||
|
constant DIBIT_COUNT : natural := 8 / IFACE_WIDTH;
|
||||||
|
|
||||||
|
|
||||||
type ethstate_t is (ETH_INIT, ETH_PREAMBLE, ETH_DATA);
|
type ethstate_t is (ETH_INIT, ETH_PREAMBLE, ETH_DATA);
|
||||||
signal framestate : ethstate_t;
|
signal framestate : ethstate_t;
|
||||||
signal crc_data_in : std_logic_vector(7 downto 0);
|
signal crc_data_in : std_logic_vector(7 downto 0);
|
||||||
signal crc_init : std_logic;
|
signal crc_init : std_logic;
|
||||||
signal crc_calc_en : std_logic;
|
signal crc_calc_en : std_logic;
|
||||||
signal crc_data_valid : std_logic;
|
signal crc_data_valid : std_logic;
|
||||||
signal crc_valid : std_logic;
|
signal crc_valid : std_logic;
|
||||||
signal dibit_counter : integer range 0 to 3 := 0;
|
signal dibit_counter : integer range 0 to (DIBIT_COUNT - 1) := 0;
|
||||||
signal data_delay_in : std_logic_vector(7 downto 0);
|
signal data_delay_in : std_logic_vector(7 downto 0);
|
||||||
signal data_delay_in_strb : std_logic;
|
signal data_delay_in_strb : std_logic;
|
||||||
signal data_delay_truncate : std_logic;
|
signal data_delay_truncate : std_logic;
|
||||||
signal end_of_frame_s : std_logic;
|
signal end_of_frame_s : std_logic;
|
||||||
type data_fifo_t is array (0 to 3) of std_logic_vector(7 downto 0);
|
type data_fifo_t is array (0 to 3) of std_logic_vector(7 downto 0);
|
||||||
|
|
||||||
signal data_delay_fifo : data_fifo_t;
|
signal data_delay_fifo : data_fifo_t;
|
||||||
@ -68,14 +74,14 @@ architecture RTL of ethmac_rx is
|
|||||||
begin
|
begin
|
||||||
ethfcs_inst : entity work.ethfcs
|
ethfcs_inst : entity work.ethfcs
|
||||||
port map(
|
port map(
|
||||||
CLOCK => clk_50,
|
CLOCK => clk_50,
|
||||||
RESET => rst,
|
RESET => rst,
|
||||||
DATA => crc_data_in,
|
DATA => crc_data_in,
|
||||||
LOAD_INIT => crc_init,
|
LOAD_INIT => crc_init,
|
||||||
CALC => crc_calc_en,
|
CALC => crc_calc_en,
|
||||||
D_VALID => crc_data_valid,
|
D_VALID => crc_data_valid,
|
||||||
CRC => open,
|
CRC => open,
|
||||||
CRC_REG => open,
|
CRC_REG => open,
|
||||||
CRC_VALID => crc_valid);
|
CRC_VALID => crc_valid);
|
||||||
|
|
||||||
rx_framefsm : process(clk_50, rst) is
|
rx_framefsm : process(clk_50, rst) is
|
||||||
@ -83,63 +89,63 @@ begin
|
|||||||
|
|
||||||
begin
|
begin
|
||||||
if rst = '1' then
|
if rst = '1' then
|
||||||
framestate <= ETH_INIT;
|
framestate <= ETH_INIT;
|
||||||
dibit_counter <= 0;
|
dibit_counter <= 0;
|
||||||
recv_byte := (others => '0');
|
recv_byte := (others => '0');
|
||||||
crc_calc_en <= '0';
|
crc_calc_en <= '0';
|
||||||
data_delay_truncate <= '0';
|
data_delay_truncate <= '0';
|
||||||
data_delay_in_strb <= '0';
|
data_delay_in_strb <= '0';
|
||||||
data_delay_in <= (others => '0');
|
data_delay_in <= (others => '0');
|
||||||
crc_init <= '0';
|
crc_init <= '0';
|
||||||
crc_data_in <= (others => '0');
|
crc_data_in <= (others => '0');
|
||||||
crc_data_valid <= '0';
|
crc_data_valid <= '0';
|
||||||
crc_calc_en <= '0';
|
crc_calc_en <= '0';
|
||||||
start_of_frame <= '0';
|
start_of_frame <= '0';
|
||||||
end_of_frame_s <= '0';
|
end_of_frame_s <= '0';
|
||||||
elsif rising_edge(clk_50) then
|
elsif rising_edge(clk_50) then
|
||||||
end_of_frame_s <= '0';
|
end_of_frame_s <= '0';
|
||||||
crc_calc_en <= '0';
|
crc_calc_en <= '0';
|
||||||
start_of_frame <= '0';
|
start_of_frame <= '0';
|
||||||
data_delay_truncate <= '0';
|
data_delay_truncate <= '0';
|
||||||
data_delay_in_strb <= '0';
|
data_delay_in_strb <= '0';
|
||||||
crc_init <= '0';
|
crc_init <= '0';
|
||||||
crc_data_valid <= '0';
|
crc_data_valid <= '0';
|
||||||
if dibit_counter = 3 then
|
if dibit_counter = DIBIT_COUNT - 1 then
|
||||||
dibit_counter <= 0;
|
dibit_counter <= 0;
|
||||||
else
|
else
|
||||||
dibit_counter <= dibit_counter + 1;
|
dibit_counter <= dibit_counter + 1;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
-- input data shift register (LSB first)
|
-- input data shift register (LSB first)
|
||||||
recv_byte := rmii_rx & recv_byte(7 downto 2);
|
recv_byte := rmii_rx & recv_byte(7 downto IFACE_WIDTH);
|
||||||
|
|
||||||
case framestate is
|
case framestate is
|
||||||
when ETH_INIT =>
|
when ETH_INIT =>
|
||||||
if rmii_dv = '0' then -- Wait for inter frame gap for sync
|
if rmii_dv = '0' then -- Wait for inter frame gap for sync
|
||||||
crc_init <= '1';
|
crc_init <= '1';
|
||||||
framestate <= ETH_PREAMBLE;
|
framestate <= ETH_PREAMBLE;
|
||||||
end if;
|
end if;
|
||||||
when ETH_PREAMBLE =>
|
when ETH_PREAMBLE =>
|
||||||
if rmii_dv = '1' and rmii_rx = "11" then -- Data valid and last dibit of preamble recieved
|
if rmii_dv = '1' and rmii_rx(rmii_rx'left downto rmii_rx'left - 1) = "11" then -- Data valid and last dibit of preamble recieved
|
||||||
-- reset dibit counter
|
-- reset dibit counter
|
||||||
dibit_counter <= 0;
|
dibit_counter <= 0;
|
||||||
start_of_frame <= '1';
|
start_of_frame <= '1';
|
||||||
framestate <= ETH_DATA;
|
framestate <= ETH_DATA;
|
||||||
-- crc_init <= '1';
|
-- crc_init <= '1';
|
||||||
end if;
|
end if;
|
||||||
when ETH_DATA =>
|
when ETH_DATA =>
|
||||||
crc_calc_en <= '1';
|
crc_calc_en <= '1';
|
||||||
if rmii_dv = '1' then
|
if rmii_dv = '1' then
|
||||||
if dibit_counter = 3 then -- Data word received
|
if dibit_counter = DIBIT_COUNT -1 then -- Data word received
|
||||||
data_delay_in <= recv_byte;
|
data_delay_in <= recv_byte;
|
||||||
data_delay_in_strb <= '1';
|
data_delay_in_strb <= '1';
|
||||||
crc_data_in <= recv_byte;
|
crc_data_in <= recv_byte;
|
||||||
crc_data_valid <= '1';
|
crc_data_valid <= '1';
|
||||||
end if;
|
end if;
|
||||||
else
|
else
|
||||||
framestate <= ETH_INIT;
|
framestate <= ETH_INIT;
|
||||||
end_of_frame_s <= '1';
|
end_of_frame_s <= '1';
|
||||||
crc_calc_en <= '0';
|
crc_calc_en <= '0';
|
||||||
data_delay_truncate <= '1';
|
data_delay_truncate <= '1';
|
||||||
end if;
|
end if;
|
||||||
end case;
|
end case;
|
||||||
@ -147,7 +153,7 @@ begin
|
|||||||
end if;
|
end if;
|
||||||
end process rx_framefsm;
|
end process rx_framefsm;
|
||||||
|
|
||||||
data_delay : process(rst, clk_50) is -- This implements a four byte big delay buffer/FIFO used for removing the crc
|
data_delay : process(rst, clk_50) is -- This implements a four byte big delay buffer/FIFO used for removing the crc
|
||||||
variable data_count : integer range 0 to 4 := 0;
|
variable data_count : integer range 0 to 4 := 0;
|
||||||
begin
|
begin
|
||||||
if rst = '1' then
|
if rst = '1' then
|
||||||
@ -161,7 +167,7 @@ begin
|
|||||||
elsif rising_edge(clk_50) then
|
elsif rising_edge(clk_50) then
|
||||||
data_strb <= '0';
|
data_strb <= '0';
|
||||||
if data_delay_truncate = '1' then
|
if data_delay_truncate = '1' then
|
||||||
data_count := 0; -- resetting counter is enough. FIFO itself has not to be cleared
|
data_count := 0; -- resetting counter is enough. FIFO itself has not to be cleared
|
||||||
elsif data_delay_in_strb = '1' then
|
elsif data_delay_in_strb = '1' then
|
||||||
data_delay_fifo(0) <= data_delay_in;
|
data_delay_fifo(0) <= data_delay_in;
|
||||||
for i in 3 downto 1 loop
|
for i in 3 downto 1 loop
|
||||||
@ -170,7 +176,7 @@ begin
|
|||||||
|
|
||||||
if data_count < 4 then
|
if data_count < 4 then
|
||||||
data_count := data_count + 1;
|
data_count := data_count + 1;
|
||||||
else -- Enable output
|
else -- Enable output
|
||||||
data_out <= data_delay_fifo(3);
|
data_out <= data_delay_fifo(3);
|
||||||
data_strb <= '1';
|
data_strb <= '1';
|
||||||
end if;
|
end if;
|
||||||
|
@ -2,7 +2,7 @@
|
|||||||
-- Title : Ethernet TX Core
|
-- Title : Ethernet TX Core
|
||||||
-- Project : EthMAC
|
-- Project : EthMAC
|
||||||
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
||||||
-- File : design/ethmac_tx.vhd
|
-- File : design/ethmac_tx.vhd
|
||||||
-- Author : Mario Hüttel <mario.huettel@gmx.net>
|
-- Author : Mario Hüttel <mario.huettel@gmx.net>
|
||||||
-- Standard : VHDL'93/02
|
-- Standard : VHDL'93/02
|
||||||
-------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
|
||||||
@ -18,7 +18,7 @@
|
|||||||
--
|
--
|
||||||
-- This code is distributed in the hope that it will be useful,
|
-- This code is distributed in the hope that it will be useful,
|
||||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
-- GNU General Public License for more details.
|
-- GNU General Public License for more details.
|
||||||
--
|
--
|
||||||
-- You should have received a copy of the GNU General Public License
|
-- You should have received a copy of the GNU General Public License
|
||||||
@ -33,50 +33,57 @@ use ieee.std_logic_1164.all;
|
|||||||
use ieee.numeric_std.all;
|
use ieee.numeric_std.all;
|
||||||
|
|
||||||
entity ethmac_tx is
|
entity ethmac_tx is
|
||||||
|
generic(
|
||||||
|
IFACE_WIDTH : natural := 2);
|
||||||
port(
|
port(
|
||||||
clk_50 : in std_logic;
|
clk_50 : in std_logic;
|
||||||
rst : in std_logic;
|
rst : in std_logic;
|
||||||
tx_ready : out std_logic;
|
tx_ready : out std_logic;
|
||||||
start_of_frame : in std_logic;
|
start_of_frame : in std_logic;
|
||||||
end_of_frame : in std_logic;
|
end_of_frame : in std_logic;
|
||||||
data_in : in std_logic_vector(7 downto 0);
|
data_in : in std_logic_vector(7 downto 0);
|
||||||
data_ack : out std_logic;
|
data_ack : out std_logic;
|
||||||
abort : in std_logic;
|
abort : in std_logic;
|
||||||
--- RMII Interface
|
--- RMII Interface
|
||||||
rmii_tx : out std_logic_vector(1 downto 0);
|
rmii_tx : out std_logic_vector(IFACE_WIDTH -1 downto 0);
|
||||||
rmii_txen : out std_logic
|
rmii_txen : out std_logic
|
||||||
);
|
);
|
||||||
end entity ethmac_tx;
|
end entity ethmac_tx;
|
||||||
|
|
||||||
architecture RTL of ethmac_tx is
|
architecture RTL of ethmac_tx is
|
||||||
|
|
||||||
|
constant DIBIT_COUNT : natural := 8 / IFACE_WIDTH;
|
||||||
|
constant PREAMBLE_BYTE : std_logic_vector(7 downto 0) := x"55";
|
||||||
|
constant PREAMBLE_SFD : std_logic_vector(7 downto 0) := x"D5";
|
||||||
|
|
||||||
type eth_tx_state_t is (INIT, PREAMBLE, DATA, CRC, IPG);
|
type eth_tx_state_t is (INIT, PREAMBLE, DATA, CRC, IPG);
|
||||||
|
|
||||||
signal crc_data_in : std_logic_vector(7 downto 0);
|
signal crc_data_in : std_logic_vector(7 downto 0);
|
||||||
signal crc_init : std_logic;
|
signal crc_init : std_logic;
|
||||||
signal crc_data_out : std_logic_vector(7 downto 0);
|
signal crc_data_out : std_logic_vector(7 downto 0);
|
||||||
signal crc_data_valid : std_logic;
|
signal crc_data_valid : std_logic;
|
||||||
signal crc_calc : std_logic;
|
signal crc_calc : std_logic;
|
||||||
signal dibit_counter : integer range 0 to 3 := 0;
|
signal dibit_counter : integer range 0 to DIBIT_COUNT - 1 := 0;
|
||||||
signal byte_counter : integer range 0 to 15 := 0;
|
signal byte_counter : integer range 0 to 15 := 0;
|
||||||
signal tx_state : eth_tx_state_t;
|
signal tx_state : eth_tx_state_t;
|
||||||
|
|
||||||
signal data_reg : std_logic_vector(7 downto 0);
|
signal data_reg : std_logic_vector(7 downto 0);
|
||||||
signal eof_reg : std_logic;
|
signal eof_reg : std_logic;
|
||||||
signal byte_counter_disable : std_logic;
|
signal byte_counter_disable : std_logic;
|
||||||
|
|
||||||
begin
|
begin
|
||||||
ethfcs_inst : entity work.ethfcs
|
ethfcs_inst : entity work.ethfcs
|
||||||
port map(
|
port map(
|
||||||
CLOCK => clk_50,
|
CLOCK => clk_50,
|
||||||
RESET => rst,
|
RESET => rst,
|
||||||
DATA => crc_data_in,
|
DATA => crc_data_in,
|
||||||
LOAD_INIT => crc_init,
|
LOAD_INIT => crc_init,
|
||||||
CALC => crc_calc,
|
CALC => crc_calc,
|
||||||
D_VALID => crc_data_valid,
|
D_VALID => crc_data_valid,
|
||||||
CRC => crc_data_out,
|
CRC => crc_data_out,
|
||||||
CRC_REG => open,
|
CRC_REG => open,
|
||||||
CRC_VALID => open
|
CRC_VALID => open
|
||||||
);
|
);
|
||||||
|
|
||||||
eth_tx_fsm : process(clk_50, rst) is
|
eth_tx_fsm : process(clk_50, rst) is
|
||||||
begin
|
begin
|
||||||
@ -88,7 +95,7 @@ begin
|
|||||||
dibit_counter <= 0;
|
dibit_counter <= 0;
|
||||||
byte_counter <= 0;
|
byte_counter <= 0;
|
||||||
rmii_txen <= '0';
|
rmii_txen <= '0';
|
||||||
rmii_tx <= "00";
|
rmii_tx <= (others => '0');
|
||||||
tx_state <= INIT;
|
tx_state <= INIT;
|
||||||
data_reg <= (others => '0');
|
data_reg <= (others => '0');
|
||||||
data_ack <= '0';
|
data_ack <= '0';
|
||||||
@ -100,10 +107,10 @@ begin
|
|||||||
crc_data_valid <= '0';
|
crc_data_valid <= '0';
|
||||||
|
|
||||||
-- Shift data register
|
-- Shift data register
|
||||||
data_reg <= "00" & data_reg(7 downto 2);
|
data_reg <= std_logic_vector(to_unsigned(0, IFACE_WIDTH)) & data_reg(7 downto IFACE_WIDTH);
|
||||||
|
|
||||||
-- Increment counters:
|
-- Increment counters:
|
||||||
if dibit_counter = 3 then
|
if dibit_counter = DIBIT_COUNT - 1 then
|
||||||
dibit_counter <= 0;
|
dibit_counter <= 0;
|
||||||
if byte_counter_disable /= '1' then
|
if byte_counter_disable /= '1' then
|
||||||
if byte_counter = 15 then
|
if byte_counter = 15 then
|
||||||
@ -123,73 +130,75 @@ begin
|
|||||||
case tx_state is
|
case tx_state is
|
||||||
when INIT =>
|
when INIT =>
|
||||||
byte_counter_disable <= '1';
|
byte_counter_disable <= '1';
|
||||||
-- Wait for start of frame
|
-- Wait for start of frame
|
||||||
if start_of_frame = '1' then
|
if start_of_frame = '1' then
|
||||||
crc_init <= '1';
|
crc_init <= '1';
|
||||||
tx_state <= PREAMBLE;
|
tx_state <= PREAMBLE;
|
||||||
byte_counter_disable <= '0';
|
byte_counter_disable <= '0';
|
||||||
dibit_counter <= 0;
|
dibit_counter <= 0;
|
||||||
byte_counter <= 0;
|
byte_counter <= 0;
|
||||||
eof_reg <= '0';
|
eof_reg <= '0';
|
||||||
end if;
|
end if;
|
||||||
when PREAMBLE =>
|
when PREAMBLE =>
|
||||||
rmii_txen <= '1';
|
rmii_txen <= '1';
|
||||||
byte_counter_disable <= '0';
|
byte_counter_disable <= '0';
|
||||||
if (byte_counter = 7 and dibit_counter = 3) then -- Last dibit of preamble+SFD
|
if (byte_counter = 7 and dibit_counter = DIBIT_COUNT -1) then -- Last dibit of preamble+SFD
|
||||||
rmii_tx <= "11";
|
|
||||||
-- latch data_in and continue to data phase
|
rmii_tx <= PREAMBLE_SFD(7 downto 8 - IFACE_WIDTH);
|
||||||
data_reg <= data_in;
|
-- latch data_in and continue to data phase
|
||||||
data_ack <= '1';
|
data_reg <= data_in;
|
||||||
tx_state <= DATA;
|
data_ack <= '1';
|
||||||
eof_reg <= end_of_frame;
|
tx_state <= DATA;
|
||||||
|
eof_reg <= end_of_frame;
|
||||||
|
crc_data_valid <= '1';
|
||||||
|
crc_calc <= '1';
|
||||||
|
crc_data_in <= data_in;
|
||||||
else
|
else
|
||||||
rmii_tx <= "01";
|
rmii_tx <= PREAMBLE_BYTE(IFACE_WIDTH -1 downto 0);
|
||||||
end if;
|
end if;
|
||||||
when DATA =>
|
when DATA =>
|
||||||
rmii_txen <= '1';
|
rmii_txen <= '1';
|
||||||
crc_calc <= '1';
|
crc_calc <= '1';
|
||||||
byte_counter_disable <= '1';
|
byte_counter_disable <= '1';
|
||||||
rmii_tx <= data_reg(1 downto 0);
|
rmii_tx <= data_reg(IFACE_WIDTH - 1 downto 0);
|
||||||
if dibit_counter = 0 then -- first dibit to transmit => shift register yet intact => Load crc;
|
|
||||||
crc_data_in <= data_reg;
|
if dibit_counter = DIBIT_COUNT - 1 and eof_reg = '0' then -- Ladt dibit sent => latch new data
|
||||||
|
data_reg <= data_in;
|
||||||
|
data_ack <= '1';
|
||||||
|
eof_reg <= end_of_frame;
|
||||||
crc_data_valid <= '1';
|
crc_data_valid <= '1';
|
||||||
end if;
|
crc_data_in <= data_in;
|
||||||
-- Output Least significant dibit of data reg
|
elsif dibit_counter = DIBIT_COUNT - 1 and eof_reg = '1' then -- Last dibit sent, no further data => CRC
|
||||||
if dibit_counter = 3 and eof_reg = '0' then -- Ladt dibit sent => latch new data
|
tx_state <= CRC;
|
||||||
data_reg <= data_in;
|
data_reg <= crc_data_out;
|
||||||
data_ack <= '1';
|
crc_data_valid <= '1';
|
||||||
eof_reg <= end_of_frame;
|
byte_counter <= 0;
|
||||||
elsif dibit_counter = 3 and eof_reg = '1' then -- Last dibit sent, no further data => CRC
|
|
||||||
tx_state <= CRC;
|
|
||||||
data_reg <= crc_data_out;
|
|
||||||
byte_counter <= 0;
|
|
||||||
byte_counter_disable <= '0';
|
byte_counter_disable <= '0';
|
||||||
crc_calc <= '0';
|
crc_calc <= '0';
|
||||||
end if;
|
end if;
|
||||||
when CRC =>
|
when CRC =>
|
||||||
byte_counter_disable <= '0';
|
byte_counter_disable <= '0';
|
||||||
rmii_txen <= '1';
|
rmii_txen <= '1';
|
||||||
rmii_tx <= data_reg(1 downto 0);
|
rmii_tx <= data_reg(IFACE_WIDTH - 1 downto 0);
|
||||||
if dibit_counter = 1 and byte_counter /= 3 then -- Request new data byte
|
if dibit_counter = DIBIT_COUNT - 1 then -- Either latch new CRC data or proceed to IPG when CRC is finished.
|
||||||
crc_data_valid <= '1';
|
|
||||||
elsif dibit_counter = 3 then -- Either latch new CRC data or proceed to IPG when CRC is finished.
|
|
||||||
if byte_counter = 3 then
|
if byte_counter = 3 then
|
||||||
byte_counter <= 0;
|
byte_counter <= 0;
|
||||||
tx_state <= IPG;
|
tx_state <= IPG;
|
||||||
else
|
else
|
||||||
data_reg <= crc_data_out;
|
data_reg <= crc_data_out;
|
||||||
|
crc_data_valid <= '1';
|
||||||
end if;
|
end if;
|
||||||
end if;
|
end if;
|
||||||
|
|
||||||
when IPG =>
|
when IPG =>
|
||||||
rmii_txen <= '0';
|
rmii_txen <= '0';
|
||||||
byte_counter_disable <= '0';
|
byte_counter_disable <= '0';
|
||||||
if byte_counter = 11 and dibit_counter = 3 then
|
if byte_counter = 11 and dibit_counter = DIBIT_COUNT - 1 then
|
||||||
tx_state <= INIT;
|
tx_state <= INIT;
|
||||||
end if;
|
end if;
|
||||||
end case;
|
end case;
|
||||||
end if; -- abort condition
|
end if; -- abort condition
|
||||||
end if; -- rising edge end process eth_tx_fsm;
|
end if; -- rising edge end process eth_tx_fsm;
|
||||||
end process eth_tx_fsm;
|
end process eth_tx_fsm;
|
||||||
|
|
||||||
tx_ready <= '1' when tx_state = INIT else '0';
|
tx_ready <= '1' when tx_state = INIT else '0';
|
||||||
|
Loading…
Reference in New Issue
Block a user