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init EthMac prject with RX, TX core and LED Demo

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This commit is contained in:
Mario Hüttel 2017-02-25 21:12:20 +01:00
commit f91c1d91ab
20 changed files with 2400 additions and 0 deletions
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5
.gitignore vendored Normal file
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# FPGA Design Folders
quartus
diamond
*.bak

11
.library_mapping.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<com.sigasi.hdt.shared.librarymapping.model:LibraryMappings xmlns:com.sigasi.hdt.shared.librarymapping.model="com.sigasi.hdt.vhdl.scoping.librarymapping" Version="2">
<Mappings Location="bench" Library="bench"/>
<Mappings Location="design" Library="design"/>
<Mappings Location="Common Libraries/IEEE" Library="ieee"/>
<Mappings Location="Common Libraries" Library="not mapped"/>
<Mappings Location="fcs-c" Library="not mapped"/>
<Mappings Location="quartus" Library="not mapped"/>
<Mappings Location="Common Libraries/STD" Library="std"/>
<Mappings Location="" Library="work"/>
</com.sigasi.hdt.shared.librarymapping.model:LibraryMappings>

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.project Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<projectDescription>
<name>ethmac</name>
<comment></comment>
<projects>
</projects>
<buildSpec>
<buildCommand>
<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
<arguments>
</arguments>
</buildCommand>
</buildSpec>
<natures>
<nature>com.sigasi.hdt.vhdl.ui.vhdlNature</nature>
<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
</natures>
<linkedResources>
<link>
<name>Common Libraries</name>
<type>2</type>
<locationURI>virtual:/virtual</locationURI>
</link>
<link>
<name>Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt</name>
<type>1</type>
<locationURI>sigasiresource:/vhdl/readme2.txt</locationURI>
</link>
<link>
<name>Common Libraries/IEEE</name>
<type>2</type>
<locationURI>sigasiresource:/vhdl/93/IEEE</locationURI>
</link>
<link>
<name>Common Libraries/STD</name>
<type>2</type>
<locationURI>sigasiresource:/vhdl/93/STD</locationURI>
</link>
<link>
<name>Common Libraries/IEEE/Synopsys</name>
<type>2</type>
<locationURI>sigasiresource:/vhdl/93/IEEE%20Synopsys</locationURI>
</link>
</linkedResources>
</projectDescription>

1
.settings/com.sigasi.hdt.vhdl.version.prefs Normal file
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<project>=93

5
.settings/org.eclipse.core.resources.prefs Normal file
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eclipse.preferences.version=1
encoding//Common\ Libraries/IEEE=utf-8
encoding//Common\ Libraries/IEEE/Synopsys=utf-8
encoding//Common\ Libraries/STD=utf-8
encoding/Common\ Libraries=utf-8

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bench/bench_ethmac_rx.vhd Normal file
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library design;
use design.all;
entity bench_ethmac_rx is
end entity bench_ethmac_rx;
architecture RTL of bench_ethmac_rx is
signal clk_hw : std_logic;
signal rst_hw : std_logic;
signal dv_i : std_logic;
signal rxd_i : std_logic_vector(1 downto 0);
signal rst : std_logic;
signal start_of_frame : std_logic;
signal end_of_frame : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal data_strb : std_logic;
signal crc_check_valid : std_logic;
signal clock_fcs : std_logic;
signal crc : std_logic_vector(7 downto 0);
signal dvalid : std_logic;
signal calc : std_logic;
signal fcs_init : std_logic;
signal fcs_dat : std_logic_vector(7 downto 0);
begin
rst <= not rst_hw;
clock_driver : process
constant period : time := 20 ns;
begin
clk_hw <= '0';
wait for period / 2;
clk_hw <= '1';
wait for period / 2;
end process clock_driver;
ethmac_rx_inst : entity design.ethmac_rx
port map(
clk_50 => clk_hw,
rst => rst,
rmii_rx => rxd_i,
rmii_dv => dv_i,
start_of_frame => start_of_frame,
end_of_frame => end_of_frame,
data_out => data_out,
data_strb => data_strb,
crc_check_valid => crc_check_valid
);
ethfcs_inst : entity design.ethfcs
port map(
CLOCK => clock_fcs,
RESET => rst,
DATA => fcs_dat,
LOAD_INIT => fcs_init,
CALC => calc,
D_VALID => dvalid,
CRC => crc,
CRC_REG => open,
CRC_VALID => open
);
sendphy : process is
procedure sendRMII(byte : in std_logic_vector(7 downto 0)) is
begin
wait until falling_edge(clk_hw);
dv_i <= '1';
rxd_i <= byte(1 downto 0);
wait until falling_edge(clk_hw);
rxd_i <= byte(3 downto 2);
wait until falling_edge(clk_hw);
rxd_i <= byte(5 downto 4);
wait until falling_edge(clk_hw);
rxd_i <= byte(7 downto 6);
end procedure sendRMII;
begin
rst_hw <= '0';
dv_i <= '0';
rxd_i <= "00";
calc <= '0';
fcs_dat <= x"00";
wait for 2 ns;
rst_hw <= '1';
fcs_init <= '1';
wait for 50 ns;
fcs_init <= '0';
wait for 50 ns;
wait for 10 ns;
sendRMII(x"55");
sendRMII(x"55");
sendRMII(x"55");
sendRMII(x"55");
sendRMII(x"55");
sendRMII(x"55");
sendRMII(x"55");
sendRMII(x"55");
sendRMII(x"D5");
sendRMII(x"FF");
sendRMII(x"DE");
sendRMII(x"AD");
sendRMII(x"BE");
sendRMII(x"EF");
sendRMII(x"00");
sendRMII(x"01");
sendRMII(x"02");
sendRMII(x"03");
sendRMII(x"04");
sendRMII(x"05");
sendRMII(x"06");
sendRMII(x"01");
sendRMII(x"02");
sendRMII(x"AA");
sendRMII(x"01");
sendRMII(x"02");
sendRMII(x"03");
-- Send FCS
sendRMII(x"BD");
sendRMII(x"9B");
sendRMII(x"AC");
sendRMII(x"54");
-- sendRMII(x"AB");
wait until falling_edge(clk_hw);
wait for 10 ns;
dv_i <= '0';
wait for 200 ns;
sendRMII(x"55");
sendRMII(x"55");
sendRMII(x"55");
sendRMII(x"55");
sendRMII(x"55");
sendRMII(x"55");
sendRMII(x"55");
sendRMII(x"55");
sendRMII(x"D5");
sendRMII(x"00");
sendRMII(x"DE");
sendRMII(x"AD");
sendRMII(x"BE");
sendRMII(x"EF");
sendRMII(x"00");
sendRMII(x"01");
sendRMII(x"02");
sendRMII(x"03");
sendRMII(x"04");
sendRMII(x"05");
sendRMII(x"06");
sendRMII(x"01");
sendRMII(x"02");
sendRMII(x"FA");
wait until falling_edge(clk_hw);
dv_i <= '0';
wait;
end process sendphy;
end architecture RTL;

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bench/bench_ethmac_tx.vhd Normal file
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library ieee;
library design;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use design.all;
entity bench_ethmac_tx is
end entity bench_ethmac_tx;
architecture RTL of bench_ethmac_tx is
signal clk : std_logic;
signal rst : std_logic;
signal tx_ready : std_logic;
signal start_of_frame : std_logic;
signal end_of_frame : std_logic;
signal data_in : std_logic_vector(7 downto 0);
signal data_ack : std_logic;
signal abort : std_logic;
signal rmii_tx : std_logic_vector(1 downto 0);
signal rmii_txen : std_logic;
begin
clock_driver : process
constant period : time := 20 ns;
begin
clk <= '0';
wait for period / 2;
clk <= '1';
wait for period / 2;
end process clock_driver;
ethmac_tx_inst : entity design.ethmac_tx
port map(
clk_50 => clk,
rst => rst,
tx_ready => tx_ready,
start_of_frame => start_of_frame,
end_of_frame => end_of_frame,
data_in => data_in,
data_ack => data_ack,
abort => abort,
rmii_tx => rmii_tx,
rmii_txen => rmii_txen
);
abort <= '0';
sendpkg : process is
procedure sendByte(byte : std_logic_vector(7 downto 0); last : std_logic) is
begin
wait until rising_edge(clk);
data_in <= byte;
end_of_frame <= last;
wait until data_ack = '1';
end procedure sendByte;
begin
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 20 ns;
start_of_frame <= '1';
sendByte(x"FF", '0');
start_of_frame <= '0';
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '1');
wait;
end process sendpkg;
end architecture RTL;

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bench/bench_ethmac_tx_rx.vhd Normal file
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library ieee;
library design;
use design.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bench_ethmac_tx_rx is
end entity bench_ethmac_tx_rx;
architecture bench of bench_ethmac_tx_rx is
signal clk : std_logic;
signal data_in : std_logic_vector(7 downto 0) := (others => '0');
signal end_of_frame : std_logic := '0';
signal data_ack : std_logic;
signal start_of_frame : std_logic := '0';
signal rst : std_logic;
signal tx_ready : std_logic;
signal rmii_tx : std_logic_vector(1 downto 0);
signal rmii_txen : std_logic;
signal data_out : std_logic_vector(7 downto 0);
signal data_strb : std_logic;
signal crc_check_valid : std_logic;
signal end_of_frame_rx : std_logic;
signal start_of_frame_rx : std_logic;
begin
clock_driver : process
constant period : time := 20 ns;
begin
clk <= '0';
wait for period / 2;
clk <= '1';
wait for period / 2;
end process clock_driver;
ethmac_tx_inst : entity design.ethmac_tx
port map(
clk_50 => clk,
rst => rst,
tx_ready => tx_ready,
start_of_frame => start_of_frame,
end_of_frame => end_of_frame,
data_in => data_in,
data_ack => data_ack,
abort => '0',
rmii_tx => rmii_tx,
rmii_txen => rmii_txen
);
ethmac_rx_inst : entity design.ethmac_rx
port map(
clk_50 => clk,
rst => rst,
rmii_rx => rmii_tx,
rmii_dv => rmii_txen,
start_of_frame => start_of_frame_rx,
end_of_frame => end_of_frame_rx,
data_out => data_out,
data_strb => data_strb,
crc_check_valid => crc_check_valid
);
sendpkg : process is
procedure sendByte(byte : std_logic_vector(7 downto 0); last : std_logic) is
begin
wait until rising_edge(clk);
data_in <= byte;
end_of_frame <= last;
wait until data_ack = '1';
end procedure sendByte;
begin
rst <= '1';
wait for 5 ns;
rst <= '0';
wait for 20 ns;
start_of_frame <= '1';
sendByte(x"FF", '0');
start_of_frame <= '0';
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '1');
wait for 100 ns;
end_of_frame <= '0';
wait for 1 us;
start_of_frame <= '1';
sendByte(x"FF", '0');
start_of_frame <= '0';
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '1');
wait for 100 ns;
end_of_frame <= '0';
wait for 1 us;
start_of_frame <= '1';
sendByte(x"FF", '0');
start_of_frame <= '0';
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '1');
wait for 100 ns;
end_of_frame <= '0';
wait for 1 us;
start_of_frame <= '1';
sendByte(x"05", '0');
start_of_frame <= '0';
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '0');
sendByte(x"04", '0');
sendByte(x"05", '0');
sendByte(x"06", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"AA", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"DE", '0');
sendByte(x"AD", '0');
sendByte(x"BE", '0');
sendByte(x"EF", '0');
sendByte(x"00", '0');
sendByte(x"01", '0');
sendByte(x"02", '0');
sendByte(x"03", '1');
wait;
end process sendpkg;
end architecture bench;

58
bench/bench_led_demo.vhd Normal file
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@ -0,0 +1,58 @@
library ieee;
library design;
use design.all;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bench_led_demo is
end entity bench_led_demo;
architecture RTL of bench_led_demo is
signal clk : std_logic;
signal data_out : std_logic_vector(3 downto 0);
signal rst_hw : std_logic;
signal rmii_tx : std_logic_vector(1 downto 0);
signal rmii_txen : std_logic;
signal rmii_rx : std_logic_vector(1 downto 0);
signal rmii_rxen : std_logic;
signal mdc : std_logic_vector(1 downto 0);
signal mdio : std_logic_vector(1 downto 0);
begin
clock_driver : process
constant period : time := 20 ns;
begin
clk <= '0';
wait for period / 2;
clk <= '1';
wait for period / 2;
end process clock_driver;
rmii_rx <= rmii_tx;
rmii_rxen <= rmii_txen;
rstegen : process is
begin
rst_hw <= '0';
wait for 5 ns;
rst_hw <= '1';
wait;
end process rstegen;
leddemo_inst : entity design.leddemo
port map(
clk_tx => clk,
clk_rx => clk,
data_in => "1010",
data_out => data_out,
rst_hw => rst_hw,
rmii_tx => rmii_tx,
rmii_txen => rmii_txen,
rmii_rx => rmii_rx,
rmii_rxen => rmii_rxen,
mdc => mdc,
mdio => mdio
);
end architecture RTL;

63
bench_ethmac_rx.gtkw Normal file
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@ -0,0 +1,63 @@
[*]
[*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI
[*] Tue Jan 31 10:51:17 2017
[*]
[dumpfile] "/tmp/SigasiCompileCache5252176646134126361/ethmac/mentor/bench_ethmac_rx.ghw"
[dumpfile_mtime] "Tue Jan 31 10:48:01 2017"
[dumpfile_size] 18590
[savefile] "/home/mari/projects/fpga/workspace/ethmac/bench_ethmac_rx.gtkw"
[timestart] 0
[size] 2880 1508
[pos] -1 -1
*-26.724226 2752900000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.bench_ethmac_rx.
[treeopen] top.bench_ethmac_rx.ethmac_rx_inst.
[treeopen] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo.
[treeopen] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.
[sst_width] 287
[signals_width] 283
[sst_expanded] 1
[sst_vpaned_height] 445
@28
top.bench_ethmac_rx.rst
top.bench_ethmac_rx.end_of_frame
top.bench_ethmac_rx.start_of_frame
top.bench_ethmac_rx.clk_hw
top.bench_ethmac_rx.dv_i
top.bench_ethmac_rx.crc_check_valid
#{top.bench_ethmac_rx.rxd_i[1:0]} top.bench_ethmac_rx.rxd_i[1] top.bench_ethmac_rx.rxd_i[0]
top.bench_ethmac_rx.ethmac_rx_inst.framestate
@200
-
-
-
@28
top.bench_ethmac_rx.data_strb
@22
#{top.bench_ethmac_rx.data_out[7:0]} top.bench_ethmac_rx.data_out[7] top.bench_ethmac_rx.data_out[6] top.bench_ethmac_rx.data_out[5] top.bench_ethmac_rx.data_out[4] top.bench_ethmac_rx.data_out[3] top.bench_ethmac_rx.data_out[2] top.bench_ethmac_rx.data_out[1] top.bench_ethmac_rx.data_out[0]
#{top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][7:0]} top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][7] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][6] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][5] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][4] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][3] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][2] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][1] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[2][0]
#{top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][7:0]} top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][7] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][6] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][5] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][4] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][3] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][2] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][1] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[1][0]
#{top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][7:0]} top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][7] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][6] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][5] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][4] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][3] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][2] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][1] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_fifo[0][0]
@28
top.bench_ethmac_rx.ethmac_rx_inst.data_delay_truncate
top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in_strb
@22
#{top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[7:0]} top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[7] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[6] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[5] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[4] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[3] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[2] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[1] top.bench_ethmac_rx.ethmac_rx_inst.data_delay_in[0]
@200
-
@29
top.bench_ethmac_rx.clk_hw
@200
-
@28
top.bench_ethmac_rx.ethmac_rx_inst.crc_data_valid
top.bench_ethmac_rx.ethmac_rx_inst.crc_calc_en
top.bench_ethmac_rx.ethmac_rx_inst.crc_init
top.bench_ethmac_rx.ethmac_rx_inst.crc_valid
top.bench_ethmac_rx.ethmac_rx_inst.crc_check_valid
@22
#{top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[7:0]} top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[7] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[6] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[5] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[4] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[3] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[2] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[1] top.bench_ethmac_rx.ethmac_rx_inst.crc_data_in[0]
#{top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31:0]} top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[30] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[29] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[28] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[27] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[26] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[25] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[24] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[23] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[22] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[21] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[20] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[19] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[18] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[17] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[16] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[15] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[14] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[13] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[12] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[11] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[10] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[9] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[8] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[7] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[6] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[5] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[4] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[3] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[2] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[1] top.bench_ethmac_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[0]
[pattern_trace] 1
[pattern_trace] 0

42
bench_ethmac_tx.gtkw Normal file
View File

@ -0,0 +1,42 @@
[*]
[*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI
[*] Tue Jan 31 17:38:47 2017
[*]
[dumpfile] "/tmp/SigasiCompileCache7754218395000362562/ethmac/mentor/bench_ethmac_tx.ghw"
[dumpfile_mtime] "Tue Jan 31 17:37:54 2017"
[dumpfile_size] 13513
[savefile] "/home/mari/projects/fpga/workspace/ethmac/bench_ethmac_tx.gtkw"
[timestart] 489830000
[size] 2880 1508
[pos] -1 -1
*-23.703266 1550000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.bench_ethmac_tx.
[treeopen] top.bench_ethmac_tx.ethmac_tx_inst.
[sst_width] 287
[signals_width] 250
[sst_expanded] 1
[sst_vpaned_height] 445
@28
top.bench_ethmac_tx.rst
@29
top.bench_ethmac_tx.clk
@28
#{top.bench_ethmac_tx.rmii_tx[1:0]} top.bench_ethmac_tx.rmii_tx[1] top.bench_ethmac_tx.rmii_tx[0]
top.bench_ethmac_tx.tx_ready
top.bench_ethmac_tx.rmii_txen
top.bench_ethmac_tx.abort
top.bench_ethmac_tx.ethmac_tx_inst.tx_state
top.bench_ethmac_tx.ethmac_tx_inst.byte_counter_disable
top.bench_ethmac_tx.ethmac_tx_inst.byte_counter
@200
-
-
@28
top.bench_ethmac_tx.ethmac_tx_inst.crc_init
top.bench_ethmac_tx.ethmac_tx_inst.crc_calc
top.bench_ethmac_tx.ethmac_tx_inst.crc_data_valid
@22
#{top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[7:0]} top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[7] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[6] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[5] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[4] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[3] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[2] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[1] top.bench_ethmac_tx.ethmac_tx_inst.crc_data_out[0]
[pattern_trace] 1
[pattern_trace] 0

130
bench_ethmac_tx_rx.gtkw Normal file
View File

@ -0,0 +1,130 @@
[*]
[*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI
[*] Wed Feb 1 16:36:58 2017
[*]
[dumpfile] "/tmp/SigasiCompileCache2061063648462684657/ethmac/mentor/bench_ethmac_tx_rx.ghw"
[dumpfile_mtime] "Wed Feb 1 16:34:58 2017"
[dumpfile_size] 313392
[savefile] "/home/mari/projects/fpga/workspace/ethmac/bench_ethmac_tx_rx.gtkw"
[timestart] 46144000000
[size] 2880 1508
[pos] -1 -1
*-26.708954 46844900000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.bench_ethmac_tx_rx.
[treeopen] top.bench_ethmac_tx_rx.ethmac_rx_inst.
[treeopen] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo.
[treeopen] top.bench_ethmac_tx_rx.ethmac_tx_inst.
[sst_width] 287
[signals_width] 283
[sst_expanded] 1
[sst_vpaned_height] 445
@28
top.bench_ethmac_tx_rx.clk
top.bench_ethmac_tx_rx.start_of_frame_rx
top.bench_ethmac_tx_rx.end_of_frame_rx
top.bench_ethmac_tx_rx.crc_check_valid
top.bench_ethmac_tx_rx.ethmac_rx_inst.framestate
top.bench_ethmac_tx_rx.data_strb
@22
#{top.bench_ethmac_tx_rx.data_out[7:0]} top.bench_ethmac_tx_rx.data_out[7] top.bench_ethmac_tx_rx.data_out[6] top.bench_ethmac_tx_rx.data_out[5] top.bench_ethmac_tx_rx.data_out[4] top.bench_ethmac_tx_rx.data_out[3] top.bench_ethmac_tx_rx.data_out[2] top.bench_ethmac_tx_rx.data_out[1] top.bench_ethmac_tx_rx.data_out[0]
@200
-
@22
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][7] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][6] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][5] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][4] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][3] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][2] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][1] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[3][0]
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][7] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][6] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][5] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][4] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][3] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][2] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][1] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[2][0]
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][7] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][6] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][5] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][4] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][3] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][2] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][1] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[1][0]
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][7] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][6] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][5] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][4] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][3] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][2] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][1] top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_fifo[0][0]
@28
top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_truncate
top.bench_ethmac_tx_rx.ethmac_rx_inst.data_delay_in_strb
@200
-
-
@28
top.bench_ethmac_tx_rx.start_of_frame
top.bench_ethmac_tx_rx.end_of_frame
@22
#{top.bench_ethmac_tx_rx.data_in[7:0]} top.bench_ethmac_tx_rx.data_in[7] top.bench_ethmac_tx_rx.data_in[6] top.bench_ethmac_tx_rx.data_in[5] top.bench_ethmac_tx_rx.data_in[4] top.bench_ethmac_tx_rx.data_in[3] top.bench_ethmac_tx_rx.data_in[2] top.bench_ethmac_tx_rx.data_in[1] top.bench_ethmac_tx_rx.data_in[0]
@28
top.bench_ethmac_tx_rx.data_ack
top.bench_ethmac_tx_rx.ethmac_tx_inst.tx_state
@22
#{top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[7:0]} top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[7] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[6] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[5] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[4] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[3] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[2] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[1] top.bench_ethmac_tx_rx.ethmac_tx_inst.data_reg[0]
@28
top.bench_ethmac_tx_rx.tx_ready
@200
-
@29
top.bench_ethmac_tx_rx.rst
@28
top.bench_ethmac_tx_rx.clk
#{top.bench_ethmac_tx_rx.rmii_tx[1:0]} top.bench_ethmac_tx_rx.rmii_tx[1] top.bench_ethmac_tx_rx.rmii_tx[0]
top.bench_ethmac_tx_rx.rmii_txen
@200
-
-
@28
top.bench_ethmac_tx_rx.ethmac_tx_inst.crc_init
top.bench_ethmac_tx_rx.ethmac_tx_inst.crc_data_valid
top.bench_ethmac_tx_rx.ethmac_tx_inst.crc_calc
@200
-
-
@800022
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[31:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[31] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[30] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[29] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[28] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[27] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[26] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[25] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[24] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[23] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[22] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[21] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[20] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[19] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[18] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[17] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[16] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[15] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[14] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[13] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[12] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[11] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[10] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[9] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[8] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[7] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[6] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[5] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[4] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[3] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[2] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[1] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[0]
@28
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[31]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[30]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[29]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[28]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[27]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[26]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[25]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[24]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[23]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[22]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[21]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[20]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[19]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[18]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[17]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[16]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[15]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[14]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[13]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[12]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[11]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[10]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[9]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[8]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[7]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[6]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[5]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[4]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[3]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[2]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[1]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_next_crc[0]
@1001200
-group_end
@22
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[30] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[29] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[28] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[27] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[26] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[25] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[24] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[23] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[22] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[21] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[20] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[19] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[18] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[17] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[16] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[15] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[14] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[13] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[12] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[11] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[10] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[9] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[8] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[7] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[6] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[5] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[4] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[3] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[2] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[1] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc_reg[0]
@c00022
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[7] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[6] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[5] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[4] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[3] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[2] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[1] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[0]
@28
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[7]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[6]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[5]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[4]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[3]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[2]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[1]
top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.s_crc[0]
@1401200
-group_end
@22
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[31:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[31] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[30] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[29] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[28] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[27] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[26] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[25] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[24] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[23] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[22] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[21] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[20] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[19] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[18] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[17] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[16] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[15] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[14] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[13] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[12] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[11] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[10] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[9] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[8] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[7] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[6] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[5] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[4] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[3] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[2] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[1] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.crc_reg[0]
#{top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[7:0]} top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[7] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[6] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[5] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[4] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[3] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[2] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[1] top.bench_ethmac_tx_rx.ethmac_rx_inst.ethfcs_inst.data[0]
[pattern_trace] 1
[pattern_trace] 0

93
bench_led_demo.gtkw Normal file
View File

@ -0,0 +1,93 @@
[*]
[*] GTKWave Analyzer v3.3.79 (w)1999-2017 BSI
[*] Tue Feb 7 21:51:10 2017
[*]
[dumpfile] "(null)"
[savefile] "/home/mari/projects/fpga/workspace/ethmac/bench_led_demo.gtkw"
[timestart] 103800000000
[size] 1920 1016
[pos] -1 -1
*-30.954296 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] top.
[treeopen] top.bench_led_demo.
[treeopen] top.bench_led_demo.leddemo_inst.
[treeopen] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.
[treeopen] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.
[treeopen] top.bench_led_demo.leddemo_inst.ethmac_tx_inst.
[sst_width] 289
[signals_width] 150
[sst_expanded] 1
[sst_vpaned_height] 284
@28
#{top.bench_led_demo.rmii_rx[1:0]} top.bench_led_demo.rmii_rx[1] top.bench_led_demo.rmii_rx[0]
@22
#{top.bench_led_demo.data_out[3:0]} top.bench_led_demo.data_out[3] top.bench_led_demo.data_out[2] top.bench_led_demo.data_out[1] top.bench_led_demo.data_out[0]
@28
#{top.bench_led_demo.mdc[1:0]} top.bench_led_demo.mdc[1] top.bench_led_demo.mdc[0]
top.bench_led_demo.clk
top.bench_led_demo.leddemo_inst.rst_rxtx
top.bench_led_demo.leddemo_inst.initstate
@200
-
-
-RX Module
@28
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.crc_valid
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.end_of_frame
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.start_of_frame
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.rmii_dv
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_strb
@22
#{top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[7:0]} top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[7] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[6] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[5] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[4] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[3] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[2] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[1] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.data_out[0]
@200
-
-
-TX Module
@22
#{top.bench_led_demo.leddemo_inst.tx_data[7:0]} top.bench_led_demo.leddemo_inst.tx_data[7] top.bench_led_demo.leddemo_inst.tx_data[6] top.bench_led_demo.leddemo_inst.tx_data[5] top.bench_led_demo.leddemo_inst.tx_data[4] top.bench_led_demo.leddemo_inst.tx_data[3] top.bench_led_demo.leddemo_inst.tx_data[2] top.bench_led_demo.leddemo_inst.tx_data[1] top.bench_led_demo.leddemo_inst.tx_data[0]
@28
top.bench_led_demo.leddemo_inst.tx_sof
top.bench_led_demo.leddemo_inst.tx_eof
top.bench_led_demo.leddemo_inst.tx_ack
top.bench_led_demo.leddemo_inst.tx_state
top.bench_led_demo.leddemo_inst.clk_tx
top.bench_led_demo.leddemo_inst.ethmac_tx_inst.tx_state
@800023
#{top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31:0]} top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[30] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[29] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[28] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[27] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[26] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[25] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[24] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[23] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[22] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[21] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[20] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[19] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[18] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[17] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[16] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[15] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[14] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[13] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[12] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[11] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[10] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[9] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[8] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[7] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[6] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[5] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[4] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[3] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[2] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[1] top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[0]
@29
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[31]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[30]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[29]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[28]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[27]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[26]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[25]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[24]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[23]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[22]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[21]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[20]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[19]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[18]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[17]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[16]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[15]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[14]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[13]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[12]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[11]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[10]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[9]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[8]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[7]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[6]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[5]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[4]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[3]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[2]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[1]
top.bench_led_demo.leddemo_inst.ethmac_rx_inst.ethfcs_inst.s_crc_reg[0]
@1001201
-group_end
[pattern_trace] 1
[pattern_trace] 0

165
design/ehtmac_rx.vhd Normal file
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@ -0,0 +1,165 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ethmac_rx is
port(
clk_50 : in std_logic;
rst : in std_logic;
rmii_rx : in std_logic_vector(1 downto 0);
rmii_dv : in std_logic;
start_of_frame : out std_logic;
end_of_frame : out std_logic;
data_out : out std_logic_vector(7 downto 0);
data_strb : out std_logic;
crc_check_valid : out std_logic
);
end entity ethmac_rx;
architecture RTL of ethmac_rx is
type ethstate_t is (ETH_INIT, ETH_PREAMBLE, ETH_DATA);
signal framestate : ethstate_t;
signal crc_data_in : std_logic_vector(7 downto 0);
signal crc_init : std_logic;
signal crc_calc_en : std_logic;
signal crc_data_valid : std_logic;
signal crc_valid : std_logic;
signal dibit_counter : integer range 0 to 3 := 0;
signal data_delay_in : std_logic_vector(7 downto 0);
signal data_delay_in_strb : std_logic;
signal data_delay_truncate : std_logic;
signal end_of_frame_s : std_logic;
type data_fifo_t is array (0 to 3) of std_logic_vector(7 downto 0);
signal data_delay_fifo : data_fifo_t;
-- signal datatype_reg: ethfield_t;
-- signal data : std_logic_vector( 7 downto 0);
begin
ethfcs_inst : entity work.ethfcs
port map(
CLOCK => clk_50,
RESET => rst,
DATA => crc_data_in,
LOAD_INIT => crc_init,
CALC => crc_calc_en,
D_VALID => crc_data_valid,
CRC => open,
CRC_REG => open,
CRC_VALID => crc_valid);
rx_framefsm : process(clk_50, rst) is
variable recv_byte : std_logic_vector(7 downto 0) := (others => '0');
begin
if rst = '1' then
framestate <= ETH_INIT;
dibit_counter <= 0;
recv_byte := (others => '0');
crc_calc_en <= '0';
data_delay_truncate <= '0';
data_delay_in_strb <= '0';
data_delay_in <= (others => '0');
crc_init <= '0';
crc_data_in <= (others => '0');
crc_data_valid <= '0';
crc_calc_en <= '0';
start_of_frame <= '0';
end_of_frame_s <= '0';
elsif rising_edge(clk_50) then
end_of_frame_s <= '0';
crc_calc_en <= '0';
start_of_frame <= '0';
data_delay_truncate <= '0';
data_delay_in_strb <= '0';
crc_init <= '0';
crc_data_valid <= '0';
if dibit_counter = 3 then
dibit_counter <= 0;
else
dibit_counter <= dibit_counter + 1;
end if;
-- input data shift register (LSB first)
recv_byte := rmii_rx & recv_byte(7 downto 2);
case framestate is
when ETH_INIT =>
if rmii_dv = '0' then -- Wait for inter frame gap for sync
crc_init <= '1';
framestate <= ETH_PREAMBLE;
end if;
when ETH_PREAMBLE =>
if rmii_dv = '1' and rmii_rx = "11" then -- Data valid and last dibit of preamble recieved
-- reset dibit counter
dibit_counter <= 0;
start_of_frame <= '1';
framestate <= ETH_DATA;
-- crc_init <= '1';
end if;
when ETH_DATA =>
crc_calc_en <= '1';
if rmii_dv = '1' then
if dibit_counter = 3 then -- Data word received
data_delay_in <= recv_byte;
data_delay_in_strb <= '1';
crc_data_in <= recv_byte;
crc_data_valid <= '1';
end if;
else
framestate <= ETH_INIT;
end_of_frame_s <= '1';
crc_calc_en <= '0';
data_delay_truncate <= '1';
end if;
end case;
end if;
end process rx_framefsm;
data_delay : process(rst, clk_50) is -- This implements a four byte big delay buffer/FIFO used for removing the crc
variable data_count : integer range 0 to 4 := 0;
begin
if rst = '1' then
data_out <= (others => '0');
data_strb <= '0';
data_count := 0;
for i in 0 to 3 loop
data_delay_fifo(i) <= (others => '0');
end loop;
elsif rising_edge(clk_50) then
data_strb <= '0';
if data_delay_truncate = '1' then
data_count := 0; -- resetting counter is enough. FIFO itself has not to be cleared
elsif data_delay_in_strb = '1' then
data_delay_fifo(0) <= data_delay_in;
for i in 3 downto 1 loop
data_delay_fifo(i) <= data_delay_fifo(i - 1);
end loop;
if data_count < 4 then
data_count := data_count + 1;
else -- Enable output
data_out <= data_delay_fifo(3);
data_strb <= '1';
end if;
end if;
end if;
end process data_delay;
crc_valid_gen : process(crc_valid) is
begin
crc_check_valid <= crc_valid;
end process crc_valid_gen;
eof_sync : process(clk_50, rst) is
begin
if rst = '1' then
end_of_frame <= '0';
elsif rising_edge(clk_50) then
end_of_frame <= end_of_frame_s;
end if;
end process eof_sync;
end architecture RTL;

217
design/eth-fcs.vhdl Normal file
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@ -0,0 +1,217 @@
--------------------------------------------------------------------------------
-- CRC GENERATOR
-- Computes the CRC32 (802.3) for the input byte stream. Assert D_VALID to load
-- each byte for calculation. LOAD_INIT should be asserted at the beginning of a
-- data stream in order to prime with CRC generator with 32'hFFFFFFFF
-- which will cause the initial 32 bits in to be complemented as per 802.3.
--
-- IO DESCRIPTION
-- Clock: 100MHz Clock
-- Reset: Active high reset
-- Data: 8Bit Data In
-- Load Init: Asserted for one clock period, loads the CRC gen with 32'hFFFFFFFF
-- Calc: Asserted to enable calculation of the CRC.
-- D_valid: Asserted for one clock period, loads in the next byte on DATA.
--
-- @author Peter A Bennett
-- @copyright (c) 2012 Peter A Bennett
-- @version $Rev: 2 $
-- @lastrevision $Date: 2012-03-11 15:19:25 +0000 (Sun, 11 Mar 2012) $
-- @license LGPL
-- @email pab850@googlemail.com
-- @contact www.bytebash.com
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ethfcs is
Port ( CLOCK : in std_logic;
RESET : in std_logic;
DATA : in std_logic_vector(7 downto 0);
LOAD_INIT : in std_logic;
CALC : in std_logic;
D_VALID : in std_logic;
CRC : out std_logic_vector(7 downto 0);
CRC_REG : out std_logic_vector(31 downto 0);
CRC_VALID : out std_logic
);
end ethfcs;
architecture RTL of ethfcs is
-- Block Diagram for Parallel CRC-32 generation.
-- (Based on Xilinx CRC App Note)
-- http://www.xilinx.com/support/documentation/application_notes/xapp209.pdf
-- Data In is byte reversed internally as per the requirements of the easics comb CRC block.
--
-- The "8-bit CRC Out" register always contains the bit-reversed and complimented most
-- significant bits of the "32-bit CRC" register. The final IEEE 802.3 FCS can be read from the
-- "8-bit CRC Out" register by asserting d_valid four times after the de-assertion of calc
--
-- +--------------------------------------+-----------------------------------+
-- | | _____ |
-- | comb_crc_gen next_crc(23:0) | | \ +--->CRC_REG(31:0)
-- | +---------------+ & x"FF" +-->|00 \ +-----+ |
-- +-->| Combinatorial |--------------------->|01 \__________|D Q|______|
--D(7:0) >--->| Next CRC Gen | xFFFFFFFF---->|10 / +--|---|En |
-- +---------------+ xFFFFFFFF---->|11 / | | +-----+ ____ +-----+
-- (complements first |_____/ | +------------>| = |-->|D Q|--> VALID_REG
-- 32 bits of frame) | | | residue ---->|____| +-|En |
--load_init >----------------------+------------------+ | | xC704DD7B | +-----+
--calc >-----------+ | | | |
--d_valid >-------+ | _ | | |-----------------------+
-- | +---|x\____|____________________| |
-- +---|---|_/ | _ |
-- | | +---|+\_______________________|
-- +---|----------+---|_/
-- | |
-- | +------------------------------------+
-- | ________ ____ | +-----+
-- | crc_reg (16:23)>-----|0 \ +--|En |
-- | ________ | \___|D Q|------>CRC(7:0)
-- | next_crc(24:31)>-----|1 / +-----+
-- | |_____/
-- | |
-- +------------------------------------------+
-- First, the data stream and CRC of the received frame are sent through the circuit.
-- Then the value left in the CRC-32 registers can be compared with a constant, commonly
-- referred to as the residue. In this implementation, the value of the residue is 0xC704DD7B
-- when no CRC errors are detected. (Xilinx CRC App Note).
-- CRC32 (Easics generator).
function comb_crc_gen
(
data_in : std_logic_vector(7 downto 0);
crc_in : std_logic_vector(31 downto 0)
)
return std_logic_vector is
variable d: std_logic_vector(7 downto 0);
variable c: std_logic_vector(31 downto 0);
variable newcrc: std_logic_vector(31 downto 0);
begin
d := data_in;
c := crc_in;
-- Easics
newcrc(0) := d(6) xor d(0) xor c(24) xor c(30);
newcrc(1) := d(7) xor d(6) xor d(1) xor d(0) xor c(24) xor c(25) xor c(30) xor c(31);
newcrc(2) := d(7) xor d(6) xor d(2) xor d(1) xor d(0) xor c(24) xor c(25) xor c(26) xor c(30) xor c(31);
newcrc(3) := d(7) xor d(3) xor d(2) xor d(1) xor c(25) xor c(26) xor c(27) xor c(31);
newcrc(4) := d(6) xor d(4) xor d(3) xor d(2) xor d(0) xor c(24) xor c(26) xor c(27) xor c(28) xor c(30);
newcrc(5) := d(7) xor d(6) xor d(5) xor d(4) xor d(3) xor d(1) xor d(0) xor c(24) xor c(25) xor c(27) xor c(28) xor c(29) xor c(30) xor c(31);
newcrc(6) := d(7) xor d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30) xor c(31);
newcrc(7) := d(7) xor d(5) xor d(3) xor d(2) xor d(0) xor c(24) xor c(26) xor c(27) xor c(29) xor c(31);
newcrc(8) := d(4) xor d(3) xor d(1) xor d(0) xor c(0) xor c(24) xor c(25) xor c(27) xor c(28);
newcrc(9) := d(5) xor d(4) xor d(2) xor d(1) xor c(1) xor c(25) xor c(26) xor c(28) xor c(29);
newcrc(10) := d(5) xor d(3) xor d(2) xor d(0) xor c(2) xor c(24) xor c(26) xor c(27) xor c(29);
newcrc(11) := d(4) xor d(3) xor d(1) xor d(0) xor c(3) xor c(24) xor c(25) xor c(27) xor c(28);
newcrc(12) := d(6) xor d(5) xor d(4) xor d(2) xor d(1) xor d(0) xor c(4) xor c(24) xor c(25) xor c(26) xor c(28) xor c(29) xor c(30);
newcrc(13) := d(7) xor d(6) xor d(5) xor d(3) xor d(2) xor d(1) xor c(5) xor c(25) xor c(26) xor c(27) xor c(29) xor c(30) xor c(31);
newcrc(14) := d(7) xor d(6) xor d(4) xor d(3) xor d(2) xor c(6) xor c(26) xor c(27) xor c(28) xor c(30) xor c(31);
newcrc(15) := d(7) xor d(5) xor d(4) xor d(3) xor c(7) xor c(27) xor c(28) xor c(29) xor c(31);
newcrc(16) := d(5) xor d(4) xor d(0) xor c(8) xor c(24) xor c(28) xor c(29);
newcrc(17) := d(6) xor d(5) xor d(1) xor c(9) xor c(25) xor c(29) xor c(30);
newcrc(18) := d(7) xor d(6) xor d(2) xor c(10) xor c(26) xor c(30) xor c(31);
newcrc(19) := d(7) xor d(3) xor c(11) xor c(27) xor c(31);
newcrc(20) := d(4) xor c(12) xor c(28);
newcrc(21) := d(5) xor c(13) xor c(29);
newcrc(22) := d(0) xor c(14) xor c(24);
newcrc(23) := d(6) xor d(1) xor d(0) xor c(15) xor c(24) xor c(25) xor c(30);
newcrc(24) := d(7) xor d(2) xor d(1) xor c(16) xor c(25) xor c(26) xor c(31);
newcrc(25) := d(3) xor d(2) xor c(17) xor c(26) xor c(27);
newcrc(26) := d(6) xor d(4) xor d(3) xor d(0) xor c(18) xor c(24) xor c(27) xor c(28) xor c(30);
newcrc(27) := d(7) xor d(5) xor d(4) xor d(1) xor c(19) xor c(25) xor c(28) xor c(29) xor c(31);
newcrc(28) := d(6) xor d(5) xor d(2) xor c(20) xor c(26) xor c(29) xor c(30);
newcrc(29) := d(7) xor d(6) xor d(3) xor c(21) xor c(27) xor c(30) xor c(31);
newcrc(30) := d(7) xor d(4) xor c(22) xor c(28) xor c(31);
newcrc(31) := d(5) xor c(23) xor c(29);
return newcrc;
end comb_crc_gen;
-- Reverse the input vector.
function reversed(slv: std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(slv'reverse_range);
begin
for i in slv'range loop
result(i) := slv(i);
end loop;
return result;
end reversed;
-- Magic number for the CRC generator.
constant c_crc_residue : std_logic_vector(31 downto 0) := x"C704DD7B";
signal s_next_crc : std_logic_vector(31 downto 0) := (others => '0');
signal s_crc_reg : std_logic_vector(31 downto 0) := (others => '0');
signal s_crc : std_logic_vector(7 downto 0) := (others => '0');
signal s_reversed_byte : std_logic_vector(7 downto 0) := (others => '0');
signal s_crc_valid : std_logic := '0';
begin
CRC <= s_crc;
CRC_REG <= s_crc_reg;
CRC_VALID <= s_crc_valid;
BYTE_REVERSE : process (DATA)
-- Nibble swapped and Bit reversed version of DATA
begin
--s_reversed_byte <= reversed(DATA(3 downto 0) & DATA(7 downto 4));
s_reversed_byte <= reversed(DATA);
end process;
COMB_NEXT_CRC_GEN : process (s_reversed_byte, s_crc_reg)
begin
s_next_crc <= comb_crc_gen(s_reversed_byte, s_crc_reg);
end process COMB_NEXT_CRC_GEN;
CRC_GEN : process (CLOCK)
variable state : std_logic_vector(2 downto 0);
begin
if rising_edge(CLOCK) then
if RESET = '1' then
s_crc_reg <= (others => '0');
s_crc <= (others => '0');
s_crc_valid <= '0';
state := (others => '0');
else
state := LOAD_INIT & CALC & D_VALID;
case state is
when "000" =>
-- No change.
when "001" =>
s_crc_reg <= s_crc_reg(23 downto 0) & x"FF";
s_crc <= not reversed(s_crc_reg(23 downto 16));
when "010" =>
-- No Change
when "011" =>
s_crc_reg <= s_next_crc;
s_crc <= not reversed(s_next_crc(31 downto 24));
when "100" =>
s_crc_reg <= x"FFFFFFFF";
when "101" =>
s_crc_reg <= x"FFFFFFFF";
s_crc <= not reversed(s_crc_reg(23 downto 16));
when "110" =>
s_crc_reg <= x"FFFFFFFF";
when "111" =>
s_crc_reg <= x"FFFFFFFF";
s_crc <= not reversed(s_next_crc(31 downto 24));
when others =>
null;
end case;
if c_crc_residue = s_crc_reg then
s_crc_valid <= '1';
else
s_crc_valid <= '0';
end if;
end if;
end if;
end process CRC_GEN;
end RTL;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ethmac_tx is
port(
clk_50 : in std_logic;
rst : in std_logic;
tx_ready : out std_logic;
start_of_frame : in std_logic;
end_of_frame : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_ack : out std_logic;
abort : in std_logic;
--- RMII Interface
rmii_tx : out std_logic_vector(1 downto 0);
rmii_txen : out std_logic
);
end entity ethmac_tx;
architecture RTL of ethmac_tx is
type eth_tx_state_t is (INIT, PREAMBLE, DATA, CRC, IPG);
signal crc_data_in : std_logic_vector(7 downto 0);
signal crc_init : std_logic;
signal crc_data_out : std_logic_vector(7 downto 0);
signal crc_data_valid : std_logic;
signal crc_calc : std_logic;
signal dibit_counter : integer range 0 to 3 := 0;
signal byte_counter : integer range 0 to 15 := 0;
signal tx_state : eth_tx_state_t;
signal data_reg : std_logic_vector(7 downto 0);
signal eof_reg : std_logic;
signal byte_counter_disable : std_logic;
begin
ethfcs_inst : entity work.ethfcs
port map(
CLOCK => clk_50,
RESET => rst,
DATA => crc_data_in,
LOAD_INIT => crc_init,
CALC => crc_calc,
D_VALID => crc_data_valid,
CRC => crc_data_out,
CRC_REG => open,
CRC_VALID => open
);
eth_tx_fsm : process(clk_50, rst) is
begin
if rst = '1' then
crc_data_in <= (others => '0');
crc_data_valid <= '0';
crc_calc <= '0';
crc_init <= '0';
dibit_counter <= 0;
byte_counter <= 0;
rmii_txen <= '0';
rmii_tx <= "00";
tx_state <= INIT;
data_reg <= (others => '0');
data_ack <= '0';
elsif rising_edge(clk_50) then
crc_init <= '0';
crc_calc <= '0';
rmii_txen <= '0';
data_ack <= '0';
crc_data_valid <= '0';
-- Shift data register
data_reg <= "00" & data_reg(7 downto 2);
-- Increment counters:
if dibit_counter = 3 then
dibit_counter <= 0;
if byte_counter_disable /= '1' then
if byte_counter = 15 then
report "Byte Counter overflow" severity error;
end if;
byte_counter <= byte_counter + 1;
end if;
else
dibit_counter <= dibit_counter + 1;
end if;
if abort = '1' then
report "Ethernet Transfer aborted in state " & eth_tx_state_t'image(tx_state) severity note;
tx_state <= INIT;
else
case tx_state is
when INIT =>
byte_counter_disable <= '1';
-- Wait for start of frame
if start_of_frame = '1' then
crc_init <= '1';
tx_state <= PREAMBLE;
byte_counter_disable <= '0';
dibit_counter <= 0;
byte_counter <= 0;
eof_reg <= '0';
end if;
when PREAMBLE =>
rmii_txen <= '1';
byte_counter_disable <= '0';
if (byte_counter = 7 and dibit_counter = 3) then -- Last dibit of preamble+SFD
rmii_tx <= "11";
-- latch data_in and continue to data phase
data_reg <= data_in;
data_ack <= '1';
tx_state <= DATA;
eof_reg <= end_of_frame;
else
rmii_tx <= "01";
end if;
when DATA =>
rmii_txen <= '1';
crc_calc <= '1';
byte_counter_disable <= '1';
rmii_tx <= data_reg(1 downto 0);
if dibit_counter = 0 then -- first dibit to transmit => shift register yet intact => Load crc;
crc_data_in <= data_reg;
crc_data_valid <= '1';
end if;
-- Output Least significant dibit of data reg
if dibit_counter = 3 and eof_reg = '0' then -- Ladt dibit sent => latch new data
data_reg <= data_in;
data_ack <= '1';
eof_reg <= end_of_frame;
elsif dibit_counter = 3 and eof_reg = '1' then -- Last dibit sent, no further data => CRC
tx_state <= CRC;
data_reg <= crc_data_out;
byte_counter <= 0;
byte_counter_disable <= '0';
crc_calc <= '0';
end if;
when CRC =>
byte_counter_disable <= '0';
rmii_txen <= '1';
rmii_tx <= data_reg(1 downto 0);
if dibit_counter = 1 and byte_counter /= 3 then -- Request new data byte
crc_data_valid <= '1';
elsif dibit_counter = 3 then -- Either latch new CRC data or proceed to IPG when CRC is finished.
if byte_counter = 3 then
byte_counter <= 0;
tx_state <= IPG;
else
data_reg <= crc_data_out;
end if;
end if;
when IPG =>
rmii_txen <= '0';
byte_counter_disable <= '0';
if byte_counter = 11 and dibit_counter = 3 then
tx_state <= INIT;
end if;
end case;
end if; -- abort condition
end if; -- rising edge end process eth_tx_fsm;
end process eth_tx_fsm;
tx_ready <= '1' when tx_state = INIT else '0';
end architecture RTL;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity leddemo is
port(
clk_tx : in std_logic;
clk_rx : in std_logic;
data_in : in std_logic_vector(3 downto 0);
data_out : out std_logic_vector(3 downto 0);
rst_hw : in std_logic;
rmii_tx : out std_logic_vector(1 downto 0);
rmii_txen : out std_logic;
rmii_rx : in std_logic_vector(1 downto 0);
rmii_rxen : in std_logic;
mdc : out std_logic_vector(1 downto 0);
mdio : out std_logic_vector(1 downto 0)
);
end entity leddemo;
architecture RTL of leddemo is
constant DELAYCNTVAL : integer := 100000
-- pragma synthesis_off
/50000
-- pragma synthesis_on
;
type smisend_t is (IDLE, STROBE);
type rx_state_t is (RXSOFWAIT, RXDATA, RXCRCCHECK);
type tx_state_t is (TXWAIT, TXSEND);
type smiinit_t is (RESET, INIT, DELAY, INIT_COMPLETE);
signal rx_state : rx_state_t;
signal tx_state : tx_state_t;
signal sendstate : smisend_t;
signal delaycounter : unsigned(19 downto 0);
signal regaddr_s : std_logic_vector(4 downto 0);
signal smi_data_s : std_logic_vector(15 downto 0);
signal smi_strb_s : std_logic;
signal rst_rxtx : std_logic;
signal rst : std_logic;
signal smi_busy_s : std_logic;
signal initstate : smiinit_t;
signal mdio_s : std_logic;
signal mdc_s : std_logic;
signal rx_crc : std_logic;
signal rx_strb : std_logic;
signal rx_data : std_logic_vector(7 downto 0);
signal rx_eof : std_logic;
signal rx_sof : std_logic;
signal rx_mem : std_logic_vector(3 downto 0);
signal tx_ack : std_logic;
signal tx_data : std_logic_vector(7 downto 0);
signal tx_eof : std_logic;
signal tx_sof : std_logic;
begin
rst <= not rst_hw;
mdc <= (others => mdc_s);
mdio <= (others => mdio_s);
smi_inst : entity work.smi
generic map(
clockdiv => 30
-- pragma synthesis_off
/10
-- pragma synthesis_on
)
port map(
clk_i => clk_tx,
rst_i => rst,
mdio_io => mdio_s,
mdc_o => mdc_s,
busy_o => smi_busy_s,
data_o => open,
phyaddr_i => "00001",
regaddr_i => regaddr_s,
data_i => smi_data_s,
strb_i => smi_strb_s,
rw_i => '0'
);
initphy : process(clk_tx, rst) is
procedure sendsmi(regaddr : in std_logic_vector(4 downto 0);
data : in std_logic_vector(15 downto 0);
nextstate : in smiinit_t) is
begin
case sendstate is
when IDLE =>
regaddr_s <= regaddr;
smi_data_s <= data;
if smi_busy_s = '0' then
smi_strb_s <= '1';
sendstate <= STROBE;
end if;
when STROBE =>
initstate <= nextstate;
sendstate <= IDLE;
end case;
end procedure sendsmi;
begin
if rst = '1' then
regaddr_s <= (others => '0');
smi_data_s <= (others => '0');
smi_strb_s <= '0';
rst_rxtx <= '1';
initstate <= RESET;
sendstate <= IDLE;
delaycounter <= (others => '0');
elsif rising_edge(clk_tx) then
smi_strb_s <= '0';
rst_rxtx <= '1';
case initstate is
when RESET =>
sendsmi((others => '0'), x"8000", DELAY);
when DELAY =>
delaycounter <= delaycounter + 1;
if delaycounter = DELAYCNTVAL then -- Set to 100000
initstate <= INIT;
end if;
when INIT =>
sendsmi((others => '0'), "00" & '1' & '1' & "000" & '1' & "00000000", INIT_COMPLETE);
when INIT_COMPLETE =>
initstate <= INIT_COMPLETE;
rst_rxtx <= '0';
end case;
end if;
end process initphy;
ethmac_rx_inst : entity work.ethmac_rx
port map(
clk_50 => clk_rx,
rst => rst,
rmii_rx => rmii_rx,
rmii_dv => rmii_rxen,
start_of_frame => rx_sof,
end_of_frame => rx_eof,
data_out => rx_data,
data_strb => rx_strb,
crc_check_valid => rx_crc
);
receiver : process(clk_rx, rst) is
begin
if rst = '1' then
rx_state <= RXSOFWAIT;
rx_mem <= (others => '0');
data_out <= (others => '0');
elsif rising_edge(clk_rx) then
case rx_state is
when RXSOFWAIT =>
if rx_sof = '1' then
rx_state <= RXDATA;
end if;
when RXDATA =>
if rx_strb = '1' then
rx_mem <= rx_data(3 downto 0);
rx_state <= RXCRCCHECK;
end if;
when RXCRCCHECK =>
if rx_eof = '1' then
rx_state <= RXSOFWAIT;
if rx_crc = '1' then
data_out <= rx_mem(3 downto 0);
end if;
end if;
end case;
end if;
end process receiver;
ethmac_tx_inst : entity work.ethmac_tx
port map(
clk_50 => clk_tx,
rst => rst,
tx_ready => open,
start_of_frame => tx_sof,
end_of_frame => tx_eof,
data_in => tx_data,
data_ack => tx_ack,
abort => '0',
rmii_tx => rmii_tx,
rmii_txen => rmii_txen
);
sender : process(clk_tx, rst_rxtx) is
variable dummycnt : integer range 0 to 511 := 0;
begin
if rst_rxtx = '1' then
tx_state <= TXWAIT;
tx_sof <= '0';
tx_eof <= '0';
tx_data <= x"00";
dummycnt := 0;
elsif rising_edge(clk_tx) then
case tx_state is
when TXWAIT =>
tx_sof <= '1';
tx_state <= TXSEND;
tx_data <= "0000" & data_in;
dummycnt := 0;
when TXSEND =>
if tx_ack = '1' then
tx_sof <= '0';
dummycnt := dummycnt + 1;
if dummycnt = 500 then
tx_eof <= '1';
end if;
if dummycnt = 501 then
tx_eof <= '0';
tx_state <= TXWAIT;
end if;
end if;
end case;
end if;
end process sender;
end architecture RTL;

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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- Implementation of the SMI
-- Only write Access implemented
-- I think i won't implement read access because.........IT'S FUCKING USELESS
entity smi is
generic(
clockdiv : integer := 64
);
port(
clk_i : in std_logic;
rst_i : in std_logic;
mdio_io : inout std_logic;
mdc_o : out std_logic;
busy_o : out std_logic;
data_o : out std_logic_vector(15 downto 0);
phyaddr_i : std_logic_vector(4 downto 0);
regaddr_i : std_logic_vector(4 downto 0);
data_i : in std_logic_vector(15 downto 0);
strb_i : in std_logic;
rw_i : in std_logic --Read/write. 0=write, 1=read
);
end entity smi;
architecture RTL of smi is
type smistate_t is (IDLE, PRE, SOF, OPC, PHYADDR, REGADDR, TURN, DATA, CONCL);
signal state_s : smistate_t;
signal fedge_strb_s : std_logic;
signal datashift_s : std_logic_vector(15 downto 0);
signal regaddr_s : std_logic_vector(4 downto 0);
signal phyaddr_s : std_logic_vector(4 downto 0);
signal bitcounter_s : integer range 0 to 32;
signal mdc_o_s : std_logic;
begin
mdc_o <= mdc_o_s;
div : process(clk_i, rst_i) is
variable counter : integer := 0;
begin
if rst_i = '1' then
fedge_strb_s <= '0';
counter := 0;
mdc_o_s <= '0';
elsif rising_edge(clk_i) then
fedge_strb_s <= '0';
counter := counter + 1;
if counter = clockdiv then
mdc_o_s <= not mdc_o_s;
counter := 0;
if mdc_o_s = '1' then
fedge_strb_s <= '1';
end if;
end if;
end if;
end process div;
smishift : process(clk_i, rst_i) is
begin
if rst_i = '1' then
mdio_io <= '1';
state_s <= IDLE;
busy_o <= '1';
elsif rising_edge(clk_i) then
busy_o <= '1';
if state_s = IDLE then
mdio_io <= '1';
busy_o <= '0';
bitcounter_s <= 0;
if (strb_i = '1') then
state_s <= PRE;
busy_o <= '1';
--Load data
phyaddr_s <= phyaddr_i;
regaddr_s <= regaddr_i;
datashift_s <= data_i;
end if;
elsif state_s = CONCL then
mdio_io <= '1';
busy_o <= '0';
state_s <= IDLE;
bitcounter_s <= 0;
elsif fedge_strb_s = '1' then
mdio_io <= '1';
bitcounter_s <= bitcounter_s + 1;
case state_s is
when PRE =>
if fedge_strb_s = '1' then
--Mdio idle high for 32 cycles
if (bitcounter_s = 31) then
bitcounter_s <= 0;
state_s <= SOF;
end if;
end if;
when SOF =>
if bitcounter_s = 0 then
mdio_io <= '0';
elsif bitcounter_s = 1 then
bitcounter_s <= 0;
--Mdio idle high
state_s <= OPC;
end if;
when OPC => --Write OPCODE
if bitcounter_s = 0 then
if rw_i = '1' then
mdio_io <= '1';
else
mdio_io <= '0';
end if;
elsif bitcounter_s = 1 then
bitcounter_s <= 0;
if rw_i = '1' then
mdio_io <= '0';
else
mdio_io <= '1';
end if;
state_s <= PHYADDR;
end if;
when PHYADDR =>
if bitcounter_s = 4 then
bitcounter_s <= 0;
state_s <= REGADDR;
end if;
mdio_io <= phyaddr_s(4);
phyaddr_s <= phyaddr_s(3 downto 0) & '0';
when REGADDR =>
if bitcounter_s = 4 then
bitcounter_s <= 0;
state_s <= TURN;
end if;
mdio_io <= regaddr_s(4);
regaddr_s <= regaddr_s(3 downto 0) & '0';
when TURN =>
if rw_i = '1' then
mdio_io <= 'Z';
end if;
if bitcounter_s = 1 then
bitcounter_s <= 0;
state_s <= DATA;
end if;
when DATA =>
if bitcounter_s = 15 then
bitcounter_s <= 0;
state_s <= CONCL;
end if;
if rw_i = '1' then
mdio_io <= 'Z';
--Not implemented => =>
else
mdio_io <= datashift_s(15);
datashift_s <= datashift_s(14 downto 0) & '0';
end if;
when others =>
null; -- This should not happen
end case;
end if;
end if;
end process smishift;
data_o <= (others => '0');
end architecture RTL;

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#include <stdio.h>
int main(void)
{
unsigned char data[] =
{
0xFF, 0xDE, 0xAD, 0xBE, 0xEF, 0x00, 1, 2,3,4,5,6,1,2,0xAA,1,2,3
};
unsigned int crc_table[] =
{
0x4DBDF21C, 0x500AE278, 0x76D3D2D4, 0x6B64C2B0,
0x3B61B38C, 0x26D6A3E8, 0x000F9344, 0x1DB88320,
0xA005713C, 0xBDB26158, 0x9B6B51F4, 0x86DC4190,
0xD6D930AC, 0xCB6E20C8, 0xEDB71064, 0xF0000000
};
unsigned int n, crc=0;
for (n=0; n<sizeof(data); n++)
{
crc = (crc >> 4) ^ crc_table[(crc ^ (data[n] >> 0)) & 0x0F]; /* lower nibble */
crc = (crc >> 4) ^ crc_table[(crc ^ (data[n] >> 4)) & 0x0F]; /* upper nibble */
}
for (n=0; n<4; n++) /* display the CRC, lower byte first */
{
printf("%02X ", crc & 0xFF);
crc >>= 8;
}
printf("\n");
return 0;
}

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