207 lines
6.5 KiB
VHDL
207 lines
6.5 KiB
VHDL
-------------------------------------------------------------------------------
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-- Title : Ethernet TX Core
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-- Project : EthMAC
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-------------------------------------------------------------------------------
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-- File : design/ethmac_tx.vhd
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-- Author : Mario Hüttel <mario.huettel@gmx.net>
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-- Standard : VHDL'93/02
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-------------------------------------------------------------------------------
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-- Description: LED Demonstration for Ethernet RX + TX
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-------------------------------------------------------------------------------
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-- Copyright (c) 2016
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--
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-- This file is part of EthMAC.
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--
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-- EthMAC is free software: you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation, version 2 of the License.
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--
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-- This code is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this code. If not, see <http://www.gnu.org/licenses/>.
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--
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-------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity ethmac_tx is
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generic(
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IFACE_WIDTH : natural := 2);
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port(
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clk_50 : in std_logic;
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rst : in std_logic;
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tx_ready : out std_logic;
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start_of_frame : in std_logic;
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end_of_frame : in std_logic;
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data_in : in std_logic_vector(7 downto 0);
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data_ack : out std_logic;
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abort : in std_logic;
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--- RMII Interface
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rmii_tx : out std_logic_vector(IFACE_WIDTH -1 downto 0);
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rmii_txen : out std_logic
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);
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end entity ethmac_tx;
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architecture RTL of ethmac_tx is
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constant DIBIT_COUNT : natural := 8 / IFACE_WIDTH;
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constant PREAMBLE_BYTE : std_logic_vector(7 downto 0) := x"55";
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constant PREAMBLE_SFD : std_logic_vector(7 downto 0) := x"D5";
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type eth_tx_state_t is (INIT, PREAMBLE, DATA, CRC, IPG);
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signal crc_data_in : std_logic_vector(7 downto 0);
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signal crc_init : std_logic;
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signal crc_data_out : std_logic_vector(7 downto 0);
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signal crc_data_valid : std_logic;
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signal crc_calc : std_logic;
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signal dibit_counter : integer range 0 to DIBIT_COUNT - 1 := 0;
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signal byte_counter : integer range 0 to 15 := 0;
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signal tx_state : eth_tx_state_t;
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signal data_reg : std_logic_vector(7 downto 0);
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signal eof_reg : std_logic;
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signal byte_counter_disable : std_logic;
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begin
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ethfcs_inst : entity work.ethfcs
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port map(
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CLOCK => clk_50,
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RESET => rst,
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DATA => crc_data_in,
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LOAD_INIT => crc_init,
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CALC => crc_calc,
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D_VALID => crc_data_valid,
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CRC => crc_data_out,
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CRC_REG => open,
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CRC_VALID => open
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);
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eth_tx_fsm : process(clk_50, rst) is
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begin
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if rst = '1' then
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crc_data_in <= (others => '0');
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crc_data_valid <= '0';
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crc_calc <= '0';
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crc_init <= '0';
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dibit_counter <= 0;
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byte_counter <= 0;
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rmii_txen <= '0';
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rmii_tx <= (others => '0');
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tx_state <= INIT;
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data_reg <= (others => '0');
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data_ack <= '0';
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elsif rising_edge(clk_50) then
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crc_init <= '0';
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crc_calc <= '0';
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rmii_txen <= '0';
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data_ack <= '0';
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crc_data_valid <= '0';
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-- Shift data register
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data_reg <= std_logic_vector(to_unsigned(0, IFACE_WIDTH)) & data_reg(7 downto IFACE_WIDTH);
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-- Increment counters:
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if dibit_counter = DIBIT_COUNT - 1 then
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dibit_counter <= 0;
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if byte_counter_disable /= '1' then
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if byte_counter = 15 then
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report "Byte Counter overflow" severity error;
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end if;
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byte_counter <= byte_counter + 1;
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end if;
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else
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dibit_counter <= dibit_counter + 1;
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end if;
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if abort = '1' then
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report "Ethernet Transfer aborted in state " & eth_tx_state_t'image(tx_state) severity note;
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tx_state <= INIT;
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else
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case tx_state is
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when INIT =>
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byte_counter_disable <= '1';
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-- Wait for start of frame
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if start_of_frame = '1' then
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crc_init <= '1';
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tx_state <= PREAMBLE;
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byte_counter_disable <= '0';
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dibit_counter <= 0;
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byte_counter <= 0;
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eof_reg <= '0';
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end if;
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when PREAMBLE =>
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rmii_txen <= '1';
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byte_counter_disable <= '0';
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if (byte_counter = 7 and dibit_counter = DIBIT_COUNT -1) then -- Last dibit of preamble+SFD
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rmii_tx <= PREAMBLE_SFD(7 downto 8 - IFACE_WIDTH);
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-- latch data_in and continue to data phase
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data_reg <= data_in;
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data_ack <= '1';
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tx_state <= DATA;
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eof_reg <= end_of_frame;
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crc_data_valid <= '1';
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crc_calc <= '1';
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crc_data_in <= data_in;
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else
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rmii_tx <= PREAMBLE_BYTE(IFACE_WIDTH -1 downto 0);
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end if;
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when DATA =>
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rmii_txen <= '1';
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crc_calc <= '1';
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byte_counter_disable <= '1';
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rmii_tx <= data_reg(IFACE_WIDTH - 1 downto 0);
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if dibit_counter = DIBIT_COUNT - 1 and eof_reg = '0' then -- Ladt dibit sent => latch new data
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data_reg <= data_in;
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data_ack <= '1';
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eof_reg <= end_of_frame;
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crc_data_valid <= '1';
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crc_data_in <= data_in;
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elsif dibit_counter = DIBIT_COUNT - 1 and eof_reg = '1' then -- Last dibit sent, no further data => CRC
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tx_state <= CRC;
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data_reg <= crc_data_out;
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crc_data_valid <= '1';
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byte_counter <= 0;
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byte_counter_disable <= '0';
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crc_calc <= '0';
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end if;
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when CRC =>
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byte_counter_disable <= '0';
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rmii_txen <= '1';
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rmii_tx <= data_reg(IFACE_WIDTH - 1 downto 0);
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if dibit_counter = DIBIT_COUNT - 1 then -- Either latch new CRC data or proceed to IPG when CRC is finished.
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if byte_counter = 3 then
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byte_counter <= 0;
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tx_state <= IPG;
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else
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data_reg <= crc_data_out;
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crc_data_valid <= '1';
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end if;
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end if;
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when IPG =>
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rmii_txen <= '0';
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byte_counter_disable <= '0';
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if byte_counter = 11 and dibit_counter = DIBIT_COUNT - 1 then
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tx_state <= INIT;
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end if;
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end case;
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end if; -- abort condition
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end if; -- rising edge end process eth_tx_fsm;
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end process eth_tx_fsm;
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tx_ready <= '1' when tx_state = INIT else '0';
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end architecture RTL;
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