59 lines
1.8 KiB
VHDL
59 lines
1.8 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity avalon2wb is
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generic (
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ADDR_WIDTH_G : natural := 32;
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DATA_WIDTH_G : natural := 32
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);
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port(
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-- Avalon Signals
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avalon_write : in std_logic;
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avalon_read : in std_logic;
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avalon_cs : in std_logic;
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avalon_waitrequest : out std_logic;
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avalon_data_in : in std_logic_vector(DATA_WIDTH_G-1 downto 0);
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avalon_data_out : out std_logic_vector(DATA_WIDTH_G-1 downto 0);
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avalon_address : in std_logic_vector(ADDR_WIDTH_G-1 downto 0);
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avalon_response : out std_logic_vector(1 downto 0);
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-- Wishbone Signals
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wb_cyc : out std_logic;
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wb_we : out std_logic;
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wb_stb : out std_logic;
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wb_ack : in std_logic;
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wb_address : out std_logic_vector(ADDR_WIDTH_G-1 downto 0);
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wb_data_out : out std_logic_vector(DATA_WIDTH_G-1 downto 0);
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wb_data_in : in std_logic_vector(DATA_WIDTH_G-1 downto 0);
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wb_err_i : in std_logic;
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wb_rty_i : in std_logic
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);
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end entity avalon2wb;
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architecture RTL of avalon2wb is
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constant RESP_OKAY : std_logic_vector(1 downto 0) := "00";
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constant RESP_SLV_ERR : std_logic_vector(1 downto 0) := "10";
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begin
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wb_address <= avalon_address;
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wb_data_out <= avalon_data_in;
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avalon_data_out <= wb_data_in;
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wb_cyc <= avalon_write or avalon_read;
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wb_stb <= avalon_cs;
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wb_we <= avalon_write and (not avalon_read);
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wait_gen : process(wb_ack, wb_rty_i, wb_err_i) is
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begin
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avalon_waitrequest <= '1';
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avalon_response <= RESP_OKAY;
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if wb_ack = '1' then
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avalon_waitrequest <= '0';
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elsif (wb_err_i = '1') or (wb_rty_i = '1') then
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avalon_waitrequest <= '0';
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avalon_response <= RESP_SLV_ERR;
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end if;
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end process wait_gen;
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end architecture RTL;
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