177 lines
5.8 KiB
Verilog
177 lines
5.8 KiB
Verilog
/////////////////////////////////////////////////////////////////////
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//// ////
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//// WISHBONE DMA WISHBONE Slave Interface ////
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//// ////
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//// ////
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//// Author: Rudolf Usselmann ////
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//// rudi@asics.ws ////
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//// ////
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//// ////
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//// Downloaded from: http://www.opencores.org/cores/wb_dma/ ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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//// ////
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//// Copyright (C) 2000-2002 Rudolf Usselmann ////
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//// www.asics.ws ////
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//// rudi@asics.ws ////
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//// ////
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//// This source file may be used and distributed without ////
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//// restriction provided that this copyright statement is not ////
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//// removed from the file and that any derivative work contains ////
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//// the original copyright notice and the associated disclaimer.////
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//// ////
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//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
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//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
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//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
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//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
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//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
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//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
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//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
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//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
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//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
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//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
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//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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/////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id: wb_dma_wb_slv.v,v 1.4 2002-02-01 01:54:45 rudi Exp $
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//
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// $Date: 2002-02-01 01:54:45 $
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// $Revision: 1.4 $
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// $Author: rudi $
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// $Locker: $
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// $State: Exp $
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//
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// Change History:
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// $Log: not supported by cvs2svn $
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// Revision 1.3 2001/10/19 04:35:04 rudi
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//
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// - Made the core parameterized
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//
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// Revision 1.2 2001/08/15 05:40:30 rudi
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//
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// - Changed IO names to be more clear.
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// - Uniquifyed define names to be core specific.
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// - Added Section 3.10, describing DMA restart.
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//
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// Revision 1.1 2001/07/29 08:57:02 rudi
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//
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//
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// 1) Changed Directory Structure
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// 2) Added restart signal (REST)
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//
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// Revision 1.2 2001/06/05 10:22:37 rudi
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//
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//
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// - Added Support of up to 31 channels
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// - Added support for 2,4 and 8 priority levels
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// - Now can have up to 31 channels
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// - Added many configuration items
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// - Changed reset to async
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//
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// Revision 1.1.1.1 2001/03/19 13:10:59 rudi
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// Initial Release
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//
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//
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//
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`include "wb_dma_defines.v"
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module wb_dma_wb_slv(clk, rst,
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wb_data_i, wb_data_o, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i,
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wb_stb_i, wb_ack_o, wb_err_o, wb_rty_o,
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// This is the register File Interface
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slv_adr, slv_din, slv_dout, slv_re, slv_we,
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// Pass through Interface
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pt_sel, slv_pt_out, slv_pt_in
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);
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parameter rf_addr = 0;
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input clk, rst;
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// --------------------------------------
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// WISHBONE INTERFACE
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input [31:0] wb_data_i;
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output [31:0] wb_data_o;
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input [31:0] wb_addr_i;
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input [3:0] wb_sel_i;
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input wb_we_i;
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input wb_cyc_i;
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input wb_stb_i;
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output wb_ack_o;
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output wb_err_o;
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output wb_rty_o;
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// This is the register File Interface
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output [31:0] slv_adr; // Slave Address
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input [31:0] slv_din; // Slave Input Data
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output [31:0] slv_dout; // Slave Output Data
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output slv_re; // Slave Read Enable
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output slv_we; // Slave Write Enable
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// Pass through Interface
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output pt_sel; // Pass Through Mode Active
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output [70:0] slv_pt_out; // Grouped WISHBONE out signals
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input [34:0] slv_pt_in; // Grouped WISHBONE in signals
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////////////////////////////////////////////////////////////////////
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//
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// Local Wires
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//
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reg slv_re, slv_we;
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wire rf_sel;
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reg rf_ack;
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reg [31:0] slv_adr, slv_dout;
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////////////////////////////////////////////////////////////////////
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//
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// Misc Logic
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//
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assign rf_sel = `WDMA_REG_SEL ;
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////////////////////////////////////////////////////////////////////
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//
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// Pass Through Logic
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//
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//assign pt_sel = !rf_sel;
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assign pt_sel = !rf_sel & wb_cyc_i;
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assign slv_pt_out = {wb_data_i, wb_addr_i, wb_sel_i, wb_we_i, wb_cyc_i, wb_stb_i};
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assign {wb_data_o, wb_ack_o, wb_err_o, wb_rty_o} = pt_sel ? slv_pt_in :
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{slv_din, rf_ack, 1'b0, 1'b0};
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////////////////////////////////////////////////////////////////////
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//
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// Register File Logic
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//
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always @(posedge clk)
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slv_adr <= #1 wb_addr_i;
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always @(posedge clk)
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slv_re <= #1 rf_sel & wb_cyc_i & wb_stb_i & !wb_we_i & !rf_ack & !slv_re;
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always @(posedge clk)
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slv_we <= #1 rf_sel & wb_cyc_i & wb_stb_i & wb_we_i & !rf_ack;
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always @(posedge clk)
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slv_dout <= #1 wb_data_i;
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always @(posedge clk)
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rf_ack <= #1 (slv_re | slv_we) & wb_cyc_i & wb_stb_i & !rf_ack ;
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endmodule
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