134 lines
3.7 KiB
VHDL
134 lines
3.7 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library design;
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use design.all;
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use design.axi3intercon_pkg.all;
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entity bench is
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end entity bench;
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architecture sim of bench is
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constant addresses : axi_slave_addresses_t := (0 => (others => '1'));
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constant masks : axi_slave_addresses_t := (0 => (0 => '0', 1 => '0', others => '1'));
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signal slaves_out : axi_slaves_out_t(0 to 0);
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signal masters_out : axi_masters_out_t(0 to 0);
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signal masters_in : axi_masters_in_t(0 to 0);
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signal aclk : std_logic;
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signal aresetn : std_logic;
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begin -- architecture sim
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clkgen : process is
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begin
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aclk <= '0';
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wait for 20 ns;
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aclk <= '1';
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wait for 20 ns;
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end process clkgen;
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rstgen : process is
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begin
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aresetn <= '0';
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wait for 30 ns;
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aresetn <= '1';
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wait;
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end process rstgen;
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test : process is
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begin
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wait until rising_edge(aclk);
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wait until rising_edge(aclk);
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wait for 100 ns;
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masters_out(0).w.wvalid <= '0';
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masters_out(0).w.wlast <= '0';
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wait until rising_edge(aclk);
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masters_out(0).ar.arid <= (3 => '0', others => '1');
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masters_out(0).ar.araddr <= (2 => '1', 4 => '1', others => '0');
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masters_out(0).ar.arlen <= std_logic_vector(to_unsigned(9, 8));
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masters_out(0).ar.arburst <= (others => '0');
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masters_out(0).ar.arprot <= (others => '0');
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masters_out(0).ar.arsize <= (1 => '1', others => '0');
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masters_out(0).ar.arvalid <= '1';
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wait until rising_edge(aclk) and masters_in(0).ar.arready = '1';
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masters_out(0).ar.arvalid <= '0';
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wait until rising_edge(aclk);
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-- Issue write request
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masters_out(0).aw.awid <= (5 => '1', others => '0');
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masters_out(0).aw.awaddr <= (4 => '1', others => '0');
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masters_out(0).aw.awlen <= std_logic_vector(to_unsigned(1, 8));
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masters_out(0).aw.awsize <= (others => '0');
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masters_out(0).aw.awburst <= (others => '0');
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masters_out(0).aw.awlock <= (others => '0');
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masters_out(0).aw.awcache <= (others => '0');
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masters_out(0).aw.awprot <= (others => '0');
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masters_out(0).aw.awvalid <= '1';
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wait until rising_edge(aclk) and masters_in(0).aw.awready = '1';
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masters_out(0).aw.awvalid <= '0';
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masters_out(0).w.wstrb <= (others => '1');
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masters_out(0).w.wdata <= x"DEADBEEF";
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masters_out(0).w.wlast <= '0';
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masters_out(0).w.wid <= (5 => '1', others => '0');
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masters_out(0).w.wvalid <= '1';
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wait until rising_edge(aclk) and masters_in(0).w.wready = '1';
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masters_out(0).w.wvalid <= '1';
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masters_out(0).w.wdata <= x"CAFEBABE";
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masters_out(0).w.wlast <= '1';
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wait until rising_edge(aclk) and masters_in(0).w.wready = '1';
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masters_out(0).w.wvalid <= '0';
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wait;
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end process;
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b_acceptor : process is
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begin
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masters_out(0).b.bready <= '0';
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wait until rising_edge(aclk) and masters_in(0).b.bvalid = '1';
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report "b_acceptor: Received B channel response wit BID " &
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integer'image(to_integer(unsigned(masters_in(0).b.bid)));
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masters_out(0).b.bready <= '1';
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wait until rising_edge(aclk);
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end process b_acceptor;
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read_acceptor : process is
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begin
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masters_out(0).r.rready <= '0';
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wait until rising_edge(aclk) and masters_in(0).r.rvalid = '1';
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report "read_acceptor: Received read with RID " &
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integer'image(to_integer(unsigned(masters_in(0).r.rid)));
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report "read_acceptor: RLAST is " & std_logic'image(masters_in(0).r.rlast);
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masters_out(0).r.rready <= '1';
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wait until rising_edge(aclk);
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end process read_acceptor;
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axi3intercon_1 : entity design.axi3intercon
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port map (
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aclk => aclk,
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aresetn => aresetn,
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masters_in => masters_in,
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masters_out => masters_out,
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slaves_in => open,
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slaves_out => slaves_out,
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address_array => addresses,
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mask_array => masks);
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end architecture sim;
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