Add simulation for toplevel
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parent
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2
sim/.gitignore
vendored
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2
sim/.gitignore
vendored
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*.o
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*.ghw
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26
sim/import-sources.sh
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26
sim/import-sources.sh
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#!/bin/bash
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if [[ -z $1 ]]; then
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echo "Specify object directory"
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exit -1
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fi
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if [[ -z $2 ]]; then
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echo "Specify source folder to scan"
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exit -1
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fi
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if [[ -z $3 ]]; then
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echo "Specify target library"
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exit -1
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fi
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echo "Scanning \"$2\" for lib \"$3\" to obj dir \"$1\""
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files=`find "$2" -name "*.vhd"`
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for file in $files; do
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echo "Importing file $file"
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ghdl -i --workdir="$1" --work="$3" "$file"
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done
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1
sim/toplevel_sim/.gitignore
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1
sim/toplevel_sim/.gitignore
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bench
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133
sim/toplevel_sim/top_bench.vhd
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sim/toplevel_sim/top_bench.vhd
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library design;
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use design.all;
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use design.axi3intercon_pkg.all;
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entity bench is
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end entity bench;
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architecture sim of bench is
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constant addresses : axi_slave_addresses_t := (0 => (others => '1'));
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constant masks : axi_slave_addresses_t := (0 => (0 => '0', 1 => '0', others => '1'));
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signal slaves_out : axi_slaves_out_t(0 to 0);
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signal masters_out : axi_masters_out_t(0 to 0);
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signal masters_in : axi_masters_in_t(0 to 0);
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signal aclk : std_logic;
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signal aresetn : std_logic;
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begin -- architecture sim
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clkgen : process is
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begin
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aclk <= '0';
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wait for 20 ns;
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aclk <= '1';
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wait for 20 ns;
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end process clkgen;
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rstgen : process is
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begin
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aresetn <= '0';
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wait for 30 ns;
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aresetn <= '1';
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wait;
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end process rstgen;
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test : process is
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begin
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wait until rising_edge(aclk);
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wait until rising_edge(aclk);
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wait for 100 ns;
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masters_out(0).w.wvalid <= '0';
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masters_out(0).w.wlast <= '0';
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wait until rising_edge(aclk);
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masters_out(0).ar.arid <= (3 => '0', others => '1');
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masters_out(0).ar.araddr <= (2 => '1', 4 => '1', others => '0');
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masters_out(0).ar.arlen <= std_logic_vector(to_unsigned(9, 8));
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masters_out(0).ar.arburst <= (others => '0');
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masters_out(0).ar.arprot <= (others => '0');
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masters_out(0).ar.arsize <= (1 => '1', others => '0');
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masters_out(0).ar.arvalid <= '1';
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wait until rising_edge(aclk) and masters_in(0).ar.arready = '1';
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masters_out(0).ar.arvalid <= '0';
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wait until rising_edge(aclk);
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-- Issue write request
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masters_out(0).aw.awid <= (5 => '1', others => '0');
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masters_out(0).aw.awaddr <= (4 => '1', others => '0');
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masters_out(0).aw.awlen <= std_logic_vector(to_unsigned(1, 8));
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masters_out(0).aw.awsize <= (others => '0');
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masters_out(0).aw.awburst <= (others => '0');
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masters_out(0).aw.awlock <= (others => '0');
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masters_out(0).aw.awcache <= (others => '0');
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masters_out(0).aw.awprot <= (others => '0');
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masters_out(0).aw.awvalid <= '1';
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wait until rising_edge(aclk) and masters_in(0).aw.awready = '1';
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masters_out(0).aw.awvalid <= '0';
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masters_out(0).w.wstrb <= (others => '1');
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masters_out(0).w.wdata <= x"DEADBEEF";
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masters_out(0).w.wlast <= '0';
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masters_out(0).w.wid <= (5 => '1', others => '0');
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masters_out(0).w.wvalid <= '1';
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wait until rising_edge(aclk) and masters_in(0).w.wready = '1';
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masters_out(0).w.wvalid <= '1';
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masters_out(0).w.wdata <= x"CAFEBABE";
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masters_out(0).w.wlast <= '1';
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wait until rising_edge(aclk) and masters_in(0).w.wready = '1';
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masters_out(0).w.wvalid <= '0';
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wait;
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end process;
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b_acceptor : process is
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begin
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masters_out(0).b.bready <= '0';
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wait until rising_edge(aclk) and masters_in(0).b.bvalid = '1';
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report "b_acceptor: Received B channel response wit BID " &
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integer'image(to_integer(unsigned(masters_in(0).b.bid)));
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masters_out(0).b.bready <= '1';
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wait until rising_edge(aclk);
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end process b_acceptor;
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read_acceptor : process is
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begin
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masters_out(0).r.rready <= '0';
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wait until rising_edge(aclk) and masters_in(0).r.rvalid = '1';
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report "read_acceptor: Received read with RID " &
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integer'image(to_integer(unsigned(masters_in(0).r.rid)));
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report "read_acceptor: RLAST is " & std_logic'image(masters_in(0).r.rlast);
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masters_out(0).r.rready <= '1';
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wait until rising_edge(aclk);
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end process read_acceptor;
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axi3intercon_1 : entity design.axi3intercon
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port map (
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aclk => aclk,
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aresetn => aresetn,
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masters_in => masters_in,
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masters_out => masters_out,
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slaves_in => open,
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slaves_out => slaves_out,
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address_array => addresses,
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mask_array => masks);
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end architecture sim;
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123
sim/toplevel_sim/toplevel-sim.gtkw
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sim/toplevel_sim/toplevel-sim.gtkw
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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[*] Tue Mar 10 18:44:35 2020
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[*]
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[dumpfile] "/home/mari/projects/fpga/axi3-interconnect/sim/toplevel_sim/wave.ghw"
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[dumpfile_mtime] "Tue Mar 10 18:29:29 2020"
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[dumpfile_size] 56058
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[savefile] "/home/mari/projects/fpga/axi3-interconnect/sim/toplevel_sim/toplevel-sim.gtkw"
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[timestart] 0
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[size] 1920 1016
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[pos] -39 -39
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*-28.000000 180000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] top.
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[treeopen] top.bench.
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[treeopen] top.bench.masters_in.
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[treeopen] top.bench.masters_in.[0].
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[treeopen] top.bench.masters_in.[0].b.
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[treeopen] top.bench.masters_out.
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[treeopen] top.bench.masters_out.[0].
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[treeopen] top.bench.masters_out.[0].ar.
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[treeopen] top.bench.slaves_out.[0].
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[treeopen] top.bench.slaves_out.[0].b.
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[sst_width] 464
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[signals_width] 307
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[sst_expanded] 1
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[sst_vpaned_height] 286
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@28
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top.bench.aresetn
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top.bench.aclk
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@200
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-Master
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-Write Channel
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@22
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#{top.bench.masters_out[0].w.wuser[3:0]} top.bench.masters_out[0].w.wuser[3] top.bench.masters_out[0].w.wuser[2] top.bench.masters_out[0].w.wuser[1] top.bench.masters_out[0].w.wuser[0]
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#{top.bench.masters_out[0].w.wstrb[3:0]} top.bench.masters_out[0].w.wstrb[3] top.bench.masters_out[0].w.wstrb[2] top.bench.masters_out[0].w.wstrb[1] top.bench.masters_out[0].w.wstrb[0]
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#{top.bench.masters_out[0].w.wdata[31:0]} top.bench.masters_out[0].w.wdata[31] top.bench.masters_out[0].w.wdata[30] top.bench.masters_out[0].w.wdata[29] top.bench.masters_out[0].w.wdata[28] top.bench.masters_out[0].w.wdata[27] top.bench.masters_out[0].w.wdata[26] top.bench.masters_out[0].w.wdata[25] top.bench.masters_out[0].w.wdata[24] top.bench.masters_out[0].w.wdata[23] top.bench.masters_out[0].w.wdata[22] top.bench.masters_out[0].w.wdata[21] top.bench.masters_out[0].w.wdata[20] top.bench.masters_out[0].w.wdata[19] top.bench.masters_out[0].w.wdata[18] top.bench.masters_out[0].w.wdata[17] top.bench.masters_out[0].w.wdata[16] top.bench.masters_out[0].w.wdata[15] top.bench.masters_out[0].w.wdata[14] top.bench.masters_out[0].w.wdata[13] top.bench.masters_out[0].w.wdata[12] top.bench.masters_out[0].w.wdata[11] top.bench.masters_out[0].w.wdata[10] top.bench.masters_out[0].w.wdata[9] top.bench.masters_out[0].w.wdata[8] top.bench.masters_out[0].w.wdata[7] top.bench.masters_out[0].w.wdata[6] top.bench.masters_out[0].w.wdata[5] top.bench.masters_out[0].w.wdata[4] top.bench.masters_out[0].w.wdata[3] top.bench.masters_out[0].w.wdata[2] top.bench.masters_out[0].w.wdata[1] top.bench.masters_out[0].w.wdata[0]
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#{top.bench.masters_out[0].w.wid[11:0]} top.bench.masters_out[0].w.wid[11] top.bench.masters_out[0].w.wid[10] top.bench.masters_out[0].w.wid[9] top.bench.masters_out[0].w.wid[8] top.bench.masters_out[0].w.wid[7] top.bench.masters_out[0].w.wid[6] top.bench.masters_out[0].w.wid[5] top.bench.masters_out[0].w.wid[4] top.bench.masters_out[0].w.wid[3] top.bench.masters_out[0].w.wid[2] top.bench.masters_out[0].w.wid[1] top.bench.masters_out[0].w.wid[0]
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@28
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top.bench.masters_out[0].w.wlast
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top.bench.masters_out[0].w.wvalid
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top.bench.masters_in[0].w.wready
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@200
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-
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-Write Address Channel
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@28
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#{top.bench.masters_out[0].aw.awprot[2:0]} top.bench.masters_out[0].aw.awprot[2] top.bench.masters_out[0].aw.awprot[1] top.bench.masters_out[0].aw.awprot[0]
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@22
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#{top.bench.masters_out[0].aw.awcache[3:0]} top.bench.masters_out[0].aw.awcache[3] top.bench.masters_out[0].aw.awcache[2] top.bench.masters_out[0].aw.awcache[1] top.bench.masters_out[0].aw.awcache[0]
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@28
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#{top.bench.masters_out[0].aw.awlock[1:0]} top.bench.masters_out[0].aw.awlock[1] top.bench.masters_out[0].aw.awlock[0]
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#{top.bench.masters_out[0].aw.awsize[2:0]} top.bench.masters_out[0].aw.awsize[2] top.bench.masters_out[0].aw.awsize[1] top.bench.masters_out[0].aw.awsize[0]
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#{top.bench.masters_out[0].aw.awburst[1:0]} top.bench.masters_out[0].aw.awburst[1] top.bench.masters_out[0].aw.awburst[0]
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@22
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#{top.bench.masters_out[0].aw.awlen[7:0]} top.bench.masters_out[0].aw.awlen[7] top.bench.masters_out[0].aw.awlen[6] top.bench.masters_out[0].aw.awlen[5] top.bench.masters_out[0].aw.awlen[4] top.bench.masters_out[0].aw.awlen[3] top.bench.masters_out[0].aw.awlen[2] top.bench.masters_out[0].aw.awlen[1] top.bench.masters_out[0].aw.awlen[0]
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#{top.bench.masters_out[0].aw.awaddr[31:0]} top.bench.masters_out[0].aw.awaddr[31] top.bench.masters_out[0].aw.awaddr[30] top.bench.masters_out[0].aw.awaddr[29] top.bench.masters_out[0].aw.awaddr[28] top.bench.masters_out[0].aw.awaddr[27] top.bench.masters_out[0].aw.awaddr[26] top.bench.masters_out[0].aw.awaddr[25] top.bench.masters_out[0].aw.awaddr[24] top.bench.masters_out[0].aw.awaddr[23] top.bench.masters_out[0].aw.awaddr[22] top.bench.masters_out[0].aw.awaddr[21] top.bench.masters_out[0].aw.awaddr[20] top.bench.masters_out[0].aw.awaddr[19] top.bench.masters_out[0].aw.awaddr[18] top.bench.masters_out[0].aw.awaddr[17] top.bench.masters_out[0].aw.awaddr[16] top.bench.masters_out[0].aw.awaddr[15] top.bench.masters_out[0].aw.awaddr[14] top.bench.masters_out[0].aw.awaddr[13] top.bench.masters_out[0].aw.awaddr[12] top.bench.masters_out[0].aw.awaddr[11] top.bench.masters_out[0].aw.awaddr[10] top.bench.masters_out[0].aw.awaddr[9] top.bench.masters_out[0].aw.awaddr[8] top.bench.masters_out[0].aw.awaddr[7] top.bench.masters_out[0].aw.awaddr[6] top.bench.masters_out[0].aw.awaddr[5] top.bench.masters_out[0].aw.awaddr[4] top.bench.masters_out[0].aw.awaddr[3] top.bench.masters_out[0].aw.awaddr[2] top.bench.masters_out[0].aw.awaddr[1] top.bench.masters_out[0].aw.awaddr[0]
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#{top.bench.masters_out[0].aw.awid[11:0]} top.bench.masters_out[0].aw.awid[11] top.bench.masters_out[0].aw.awid[10] top.bench.masters_out[0].aw.awid[9] top.bench.masters_out[0].aw.awid[8] top.bench.masters_out[0].aw.awid[7] top.bench.masters_out[0].aw.awid[6] top.bench.masters_out[0].aw.awid[5] top.bench.masters_out[0].aw.awid[4] top.bench.masters_out[0].aw.awid[3] top.bench.masters_out[0].aw.awid[2] top.bench.masters_out[0].aw.awid[1] top.bench.masters_out[0].aw.awid[0]
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@28
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top.bench.masters_out[0].aw.awvalid
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top.bench.masters_in[0].aw.awready
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@200
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-
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-Master Read Channel
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@22
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#{top.bench.masters_in[0].r.ruser[3:0]} top.bench.masters_in[0].r.ruser[3] top.bench.masters_in[0].r.ruser[2] top.bench.masters_in[0].r.ruser[1] top.bench.masters_in[0].r.ruser[0]
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@28
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#{top.bench.masters_in[0].r.rresp[1:0]} top.bench.masters_in[0].r.rresp[1] top.bench.masters_in[0].r.rresp[0]
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@22
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#{top.bench.masters_in[0].r.rdata[31:0]} top.bench.masters_in[0].r.rdata[31] top.bench.masters_in[0].r.rdata[30] top.bench.masters_in[0].r.rdata[29] top.bench.masters_in[0].r.rdata[28] top.bench.masters_in[0].r.rdata[27] top.bench.masters_in[0].r.rdata[26] top.bench.masters_in[0].r.rdata[25] top.bench.masters_in[0].r.rdata[24] top.bench.masters_in[0].r.rdata[23] top.bench.masters_in[0].r.rdata[22] top.bench.masters_in[0].r.rdata[21] top.bench.masters_in[0].r.rdata[20] top.bench.masters_in[0].r.rdata[19] top.bench.masters_in[0].r.rdata[18] top.bench.masters_in[0].r.rdata[17] top.bench.masters_in[0].r.rdata[16] top.bench.masters_in[0].r.rdata[15] top.bench.masters_in[0].r.rdata[14] top.bench.masters_in[0].r.rdata[13] top.bench.masters_in[0].r.rdata[12] top.bench.masters_in[0].r.rdata[11] top.bench.masters_in[0].r.rdata[10] top.bench.masters_in[0].r.rdata[9] top.bench.masters_in[0].r.rdata[8] top.bench.masters_in[0].r.rdata[7] top.bench.masters_in[0].r.rdata[6] top.bench.masters_in[0].r.rdata[5] top.bench.masters_in[0].r.rdata[4] top.bench.masters_in[0].r.rdata[3] top.bench.masters_in[0].r.rdata[2] top.bench.masters_in[0].r.rdata[1] top.bench.masters_in[0].r.rdata[0]
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#{top.bench.masters_in[0].r.rid[11:0]} top.bench.masters_in[0].r.rid[11] top.bench.masters_in[0].r.rid[10] top.bench.masters_in[0].r.rid[9] top.bench.masters_in[0].r.rid[8] top.bench.masters_in[0].r.rid[7] top.bench.masters_in[0].r.rid[6] top.bench.masters_in[0].r.rid[5] top.bench.masters_in[0].r.rid[4] top.bench.masters_in[0].r.rid[3] top.bench.masters_in[0].r.rid[2] top.bench.masters_in[0].r.rid[1] top.bench.masters_in[0].r.rid[0]
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@28
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top.bench.masters_in[0].r.rvalid
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top.bench.masters_in[0].r.rlast
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top.bench.masters_out[0].r.rready
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@200
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-
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-master B Channel
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@28
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#{top.bench.masters_in[0].b.bresp[1:0]} top.bench.masters_in[0].b.bresp[1] top.bench.masters_in[0].b.bresp[0]
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@22
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#{top.bench.masters_in[0].b.bid[11:0]} top.bench.masters_in[0].b.bid[11] top.bench.masters_in[0].b.bid[10] top.bench.masters_in[0].b.bid[9] top.bench.masters_in[0].b.bid[8] top.bench.masters_in[0].b.bid[7] top.bench.masters_in[0].b.bid[6] top.bench.masters_in[0].b.bid[5] top.bench.masters_in[0].b.bid[4] top.bench.masters_in[0].b.bid[3] top.bench.masters_in[0].b.bid[2] top.bench.masters_in[0].b.bid[1] top.bench.masters_in[0].b.bid[0]
|
||||
#{top.bench.masters_in[0].b.buser[3:0]} top.bench.masters_in[0].b.buser[3] top.bench.masters_in[0].b.buser[2] top.bench.masters_in[0].b.buser[1] top.bench.masters_in[0].b.buser[0]
|
||||
@28
|
||||
top.bench.masters_in[0].b.bvalid
|
||||
top.bench.masters_out[0].b.bready
|
||||
@200
|
||||
-
|
||||
-Master Read Address Channel
|
||||
@28
|
||||
#{top.bench.masters_out[0].ar.arprot[2:0]} top.bench.masters_out[0].ar.arprot[2] top.bench.masters_out[0].ar.arprot[1] top.bench.masters_out[0].ar.arprot[0]
|
||||
@22
|
||||
#{top.bench.masters_out[0].ar.arcache[3:0]} top.bench.masters_out[0].ar.arcache[3] top.bench.masters_out[0].ar.arcache[2] top.bench.masters_out[0].ar.arcache[1] top.bench.masters_out[0].ar.arcache[0]
|
||||
@28
|
||||
#{top.bench.masters_out[0].ar.arlock[1:0]} top.bench.masters_out[0].ar.arlock[1] top.bench.masters_out[0].ar.arlock[0]
|
||||
#{top.bench.masters_out[0].ar.arburst[1:0]} top.bench.masters_out[0].ar.arburst[1] top.bench.masters_out[0].ar.arburst[0]
|
||||
@c00023
|
||||
#{top.bench.masters_out[0].ar.arsize[2:0]} top.bench.masters_out[0].ar.arsize[2] top.bench.masters_out[0].ar.arsize[1] top.bench.masters_out[0].ar.arsize[0]
|
||||
@28
|
||||
top.bench.masters_out[0].ar.arsize[2]
|
||||
top.bench.masters_out[0].ar.arsize[1]
|
||||
top.bench.masters_out[0].ar.arsize[0]
|
||||
@1401203
|
||||
-group_end
|
||||
@c00022
|
||||
#{top.bench.masters_out[0].ar.arlen[7:0]} top.bench.masters_out[0].ar.arlen[7] top.bench.masters_out[0].ar.arlen[6] top.bench.masters_out[0].ar.arlen[5] top.bench.masters_out[0].ar.arlen[4] top.bench.masters_out[0].ar.arlen[3] top.bench.masters_out[0].ar.arlen[2] top.bench.masters_out[0].ar.arlen[1] top.bench.masters_out[0].ar.arlen[0]
|
||||
@28
|
||||
top.bench.masters_out[0].ar.arlen[7]
|
||||
top.bench.masters_out[0].ar.arlen[6]
|
||||
top.bench.masters_out[0].ar.arlen[5]
|
||||
top.bench.masters_out[0].ar.arlen[4]
|
||||
top.bench.masters_out[0].ar.arlen[3]
|
||||
top.bench.masters_out[0].ar.arlen[2]
|
||||
top.bench.masters_out[0].ar.arlen[1]
|
||||
top.bench.masters_out[0].ar.arlen[0]
|
||||
@1401202
|
||||
-group_end
|
||||
@22
|
||||
#{top.bench.masters_out[0].ar.araddr[31:0]} top.bench.masters_out[0].ar.araddr[31] top.bench.masters_out[0].ar.araddr[30] top.bench.masters_out[0].ar.araddr[29] top.bench.masters_out[0].ar.araddr[28] top.bench.masters_out[0].ar.araddr[27] top.bench.masters_out[0].ar.araddr[26] top.bench.masters_out[0].ar.araddr[25] top.bench.masters_out[0].ar.araddr[24] top.bench.masters_out[0].ar.araddr[23] top.bench.masters_out[0].ar.araddr[22] top.bench.masters_out[0].ar.araddr[21] top.bench.masters_out[0].ar.araddr[20] top.bench.masters_out[0].ar.araddr[19] top.bench.masters_out[0].ar.araddr[18] top.bench.masters_out[0].ar.araddr[17] top.bench.masters_out[0].ar.araddr[16] top.bench.masters_out[0].ar.araddr[15] top.bench.masters_out[0].ar.araddr[14] top.bench.masters_out[0].ar.araddr[13] top.bench.masters_out[0].ar.araddr[12] top.bench.masters_out[0].ar.araddr[11] top.bench.masters_out[0].ar.araddr[10] top.bench.masters_out[0].ar.araddr[9] top.bench.masters_out[0].ar.araddr[8] top.bench.masters_out[0].ar.araddr[7] top.bench.masters_out[0].ar.araddr[6] top.bench.masters_out[0].ar.araddr[5] top.bench.masters_out[0].ar.araddr[4] top.bench.masters_out[0].ar.araddr[3] top.bench.masters_out[0].ar.araddr[2] top.bench.masters_out[0].ar.araddr[1] top.bench.masters_out[0].ar.araddr[0]
|
||||
#{top.bench.masters_out[0].ar.arid[11:0]} top.bench.masters_out[0].ar.arid[11] top.bench.masters_out[0].ar.arid[10] top.bench.masters_out[0].ar.arid[9] top.bench.masters_out[0].ar.arid[8] top.bench.masters_out[0].ar.arid[7] top.bench.masters_out[0].ar.arid[6] top.bench.masters_out[0].ar.arid[5] top.bench.masters_out[0].ar.arid[4] top.bench.masters_out[0].ar.arid[3] top.bench.masters_out[0].ar.arid[2] top.bench.masters_out[0].ar.arid[1] top.bench.masters_out[0].ar.arid[0]
|
||||
@28
|
||||
top.bench.masters_out[0].ar.arvalid
|
||||
top.bench.masters_in[0].ar.arready
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
@ -2,7 +2,7 @@
|
||||
-- Title : toplevel entity of crossbar
|
||||
-- Project : AXI-3 Crossbar Switch
|
||||
-------------------------------------------------------------------------------
|
||||
-- File : axi3-interconnect.vhd
|
||||
-- File : axi3-interconnect.vhd
|
||||
-- Author : Mario Hüttel <mario.huettel@gmx.net>
|
||||
-- Standard : VHDL'93/02
|
||||
-------------------------------------------------------------------------------
|
||||
@ -18,7 +18,7 @@
|
||||
--
|
||||
-- This code is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
@ -39,19 +39,19 @@ use work.axi_b_router_pkg.all;
|
||||
|
||||
entity axi3intercon is
|
||||
port(
|
||||
aclk : in std_logic;
|
||||
aresetn : in std_logic;
|
||||
aclk : in std_logic;
|
||||
aresetn : in std_logic;
|
||||
masters_in : out axi_masters_in_t(0 to MASTER_COUNT - 1);
|
||||
masters_out : in axi_masters_out_t(0 to MASTER_COUNT - 1);
|
||||
slaves_in : out axi_slaves_in_t(0 to SLAVE_COUNT - 1);
|
||||
slaves_out : in axi_slaves_out_t(0 to SLAVE_COUNT - 1);
|
||||
address_array : in axi_slave_addresses_t(0 to SLAVE_COUNT - 1);
|
||||
mask_array : in axi_slave_addresses_t(0 to SLAVE_COUNT - 1)
|
||||
);
|
||||
);
|
||||
end entity axi3intercon;
|
||||
|
||||
architecture RTL of axi3intercon is
|
||||
signal rst : std_logic;
|
||||
signal rst : std_logic;
|
||||
signal write_locks : write_locks_t(0 to MASTER_COUNT - 1);
|
||||
signal write_releases : write_releases_t;
|
||||
signal aw_masters_out : axi_aw_masters_out_t(0 to MASTER_COUNT - 1);
|
||||
@ -90,8 +90,8 @@ begin
|
||||
|
||||
axi3intercon_aw_router_inst : entity work.axi3intercon_aw_router
|
||||
port map(
|
||||
aclk => aclk,
|
||||
rst => rst,
|
||||
aclk => aclk,
|
||||
rst => rst,
|
||||
masters_out => aw_masters_out,
|
||||
masters_in => aw_masters_in,
|
||||
slaves_out => aw_slaves_out,
|
||||
@ -100,7 +100,7 @@ begin
|
||||
write_releases => write_releases,
|
||||
address_array => address_array,
|
||||
mask_array => mask_array
|
||||
);
|
||||
);
|
||||
|
||||
aw_master_connect : for i in 0 to MASTER_COUNT - 1 generate
|
||||
aw_masters_out(i) <= masters_out(i).aw;
|
||||
@ -109,20 +109,20 @@ begin
|
||||
|
||||
aw_slave_connect : for i in 0 to SLAVE_COUNT - 1 generate
|
||||
aw_slaves_out(i) <= slaves_out(i).aw;
|
||||
slaves_in(i).aw <= aw_slaves_in(i);
|
||||
slaves_in(i).aw <= aw_slaves_in(i);
|
||||
end generate aw_slave_connect;
|
||||
|
||||
axi3intercon_ar_router_inst : entity work.axi3intercon_ar_router
|
||||
port map(
|
||||
aclk => aclk,
|
||||
rst => rst,
|
||||
aclk => aclk,
|
||||
rst => rst,
|
||||
masters_out => ar_masters_out,
|
||||
masters_in => ar_masters_in,
|
||||
slaves_out => ar_slaves_out,
|
||||
slaves_in => ar_slaves_in,
|
||||
address_array => address_array,
|
||||
mask_array => mask_array
|
||||
);
|
||||
);
|
||||
|
||||
ar_master_connect : for i in 0 to MASTER_COUNT - 1 generate
|
||||
ar_masters_out(i) <= masters_out(i).ar;
|
||||
@ -131,80 +131,80 @@ begin
|
||||
|
||||
ar_slave_connect : for i in 0 to SLAVE_COUNT - 1 generate
|
||||
ar_slaves_out(i) <= slaves_out(i).ar;
|
||||
slaves_in(i).ar <= ar_slaves_in(i);
|
||||
slaves_in(i).ar <= ar_slaves_in(i);
|
||||
end generate ar_slave_connect;
|
||||
|
||||
axi3_intercon_w_router_inst : entity work.axi3_intercon_w_router
|
||||
port map(
|
||||
clk => aclk,
|
||||
rst => rst,
|
||||
clk => aclk,
|
||||
rst => rst,
|
||||
masters_in => w_masters_in,
|
||||
masters_out => w_masters_out,
|
||||
slaves_in => w_slaves_in,
|
||||
slaves_out => w_slaves_out,
|
||||
write_locks => write_locks,
|
||||
write_releases => write_releases
|
||||
);
|
||||
);
|
||||
|
||||
w_master_connect : for i in 0 to MASTER_COUNT - 1 generate
|
||||
w_masters_out(i) <= masters_out(i).w;
|
||||
masters_in(i).w <= w_masters_in(i);
|
||||
masters_in(i).w <= w_masters_in(i);
|
||||
end generate w_master_connect;
|
||||
|
||||
w_slave_connect : for i in 0 to SLAVE_COUNT - 1 generate
|
||||
w_slaves_out(i) <= slaves_out(i).w;
|
||||
slaves_in(i).w <= w_slaves_in(i);
|
||||
slaves_in(i).w <= w_slaves_in(i);
|
||||
end generate w_slave_connect;
|
||||
|
||||
axi3_intercon_r_router_inst : entity work.axi3_intercon_r_router
|
||||
port map(
|
||||
clk => aclk,
|
||||
rst => rst,
|
||||
clk => aclk,
|
||||
rst => rst,
|
||||
slaves_in => r_slaves_in,
|
||||
slaves_out => r_slaves_out,
|
||||
masters_in => r_masters_in,
|
||||
masters_out => r_masters_out
|
||||
);
|
||||
);
|
||||
|
||||
r_master_connect : for i in 0 to MASTER_COUNT - 1 generate
|
||||
r_masters_out(i) <= masters_out(i).r;
|
||||
masters_in(i).r <= r_masters_in(i);
|
||||
masters_in(i).r <= r_masters_in(i);
|
||||
end generate r_master_connect;
|
||||
|
||||
r_slave_connect : for i in 0 to SLAVE_COUNT - 1 generate
|
||||
r_slaves_out(i) <= slaves_out(i).r;
|
||||
slaves_in(i).r <= r_slaves_in(i);
|
||||
slaves_in(i).r <= r_slaves_in(i);
|
||||
end generate r_slave_connect;
|
||||
|
||||
axi3_intercon_b_router_inst : entity work.axi3_intercon_b_router
|
||||
port map(
|
||||
clk => aclk,
|
||||
rst => rst,
|
||||
clk => aclk,
|
||||
rst => rst,
|
||||
slaves_in => b_slaves_in,
|
||||
slaves_out => b_slaves_out,
|
||||
masters_in => b_masters_in,
|
||||
masters_out => b_masters_out
|
||||
);
|
||||
);
|
||||
|
||||
b_master_connect : for i in 0 to MASTER_COUNT - 1 generate
|
||||
b_masters_out(i) <= masters_out(i).b;
|
||||
masters_in(i).b <= b_masters_in(i);
|
||||
masters_in(i).b <= b_masters_in(i);
|
||||
end generate b_master_connect;
|
||||
|
||||
b_slave_connect : for i in 0 to SLAVE_COUNT - 1 generate
|
||||
b_slaves_out(i) <= slaves_out(i).b;
|
||||
slaves_in(i).b <= b_slaves_in(i);
|
||||
slaves_in(i).b <= b_slaves_in(i);
|
||||
end generate b_slave_connect;
|
||||
|
||||
-- ERROR slave connections
|
||||
|
||||
axi3decerr_inst : entity work.axi3decerr
|
||||
port map(
|
||||
clk => aclk,
|
||||
rst => rst,
|
||||
clk => aclk,
|
||||
rst => rst,
|
||||
slave_in => decerr_in,
|
||||
slave_out => decerr_out
|
||||
);
|
||||
);
|
||||
|
||||
decerr_in.ar <= ar_slaves_in(SLAVE_COUNT);
|
||||
decerr_in.aw <= aw_slaves_in(SLAVE_COUNT);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user