124 lines
12 KiB
Plaintext
124 lines
12 KiB
Plaintext
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[*]
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[*] GTKWave Analyzer v3.3.104 (w)1999-2020 BSI
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[*] Tue Mar 10 18:44:35 2020
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[*]
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[dumpfile] "/home/mari/projects/fpga/axi3-interconnect/sim/toplevel_sim/wave.ghw"
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[dumpfile_mtime] "Tue Mar 10 18:29:29 2020"
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[dumpfile_size] 56058
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[savefile] "/home/mari/projects/fpga/axi3-interconnect/sim/toplevel_sim/toplevel-sim.gtkw"
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[timestart] 0
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[size] 1920 1016
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[pos] -39 -39
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*-28.000000 180000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
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[treeopen] top.
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[treeopen] top.bench.
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[treeopen] top.bench.masters_in.
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[treeopen] top.bench.masters_in.[0].
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[treeopen] top.bench.masters_in.[0].b.
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[treeopen] top.bench.masters_out.
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[treeopen] top.bench.masters_out.[0].
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[treeopen] top.bench.masters_out.[0].ar.
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[treeopen] top.bench.slaves_out.[0].
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[treeopen] top.bench.slaves_out.[0].b.
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[sst_width] 464
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[signals_width] 307
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[sst_expanded] 1
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[sst_vpaned_height] 286
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@28
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top.bench.aresetn
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top.bench.aclk
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@200
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-Master
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-Write Channel
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@22
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#{top.bench.masters_out[0].w.wuser[3:0]} top.bench.masters_out[0].w.wuser[3] top.bench.masters_out[0].w.wuser[2] top.bench.masters_out[0].w.wuser[1] top.bench.masters_out[0].w.wuser[0]
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#{top.bench.masters_out[0].w.wstrb[3:0]} top.bench.masters_out[0].w.wstrb[3] top.bench.masters_out[0].w.wstrb[2] top.bench.masters_out[0].w.wstrb[1] top.bench.masters_out[0].w.wstrb[0]
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#{top.bench.masters_out[0].w.wdata[31:0]} top.bench.masters_out[0].w.wdata[31] top.bench.masters_out[0].w.wdata[30] top.bench.masters_out[0].w.wdata[29] top.bench.masters_out[0].w.wdata[28] top.bench.masters_out[0].w.wdata[27] top.bench.masters_out[0].w.wdata[26] top.bench.masters_out[0].w.wdata[25] top.bench.masters_out[0].w.wdata[24] top.bench.masters_out[0].w.wdata[23] top.bench.masters_out[0].w.wdata[22] top.bench.masters_out[0].w.wdata[21] top.bench.masters_out[0].w.wdata[20] top.bench.masters_out[0].w.wdata[19] top.bench.masters_out[0].w.wdata[18] top.bench.masters_out[0].w.wdata[17] top.bench.masters_out[0].w.wdata[16] top.bench.masters_out[0].w.wdata[15] top.bench.masters_out[0].w.wdata[14] top.bench.masters_out[0].w.wdata[13] top.bench.masters_out[0].w.wdata[12] top.bench.masters_out[0].w.wdata[11] top.bench.masters_out[0].w.wdata[10] top.bench.masters_out[0].w.wdata[9] top.bench.masters_out[0].w.wdata[8] top.bench.masters_out[0].w.wdata[7] top.bench.masters_out[0].w.wdata[6] top.bench.masters_out[0].w.wdata[5] top.bench.masters_out[0].w.wdata[4] top.bench.masters_out[0].w.wdata[3] top.bench.masters_out[0].w.wdata[2] top.bench.masters_out[0].w.wdata[1] top.bench.masters_out[0].w.wdata[0]
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#{top.bench.masters_out[0].w.wid[11:0]} top.bench.masters_out[0].w.wid[11] top.bench.masters_out[0].w.wid[10] top.bench.masters_out[0].w.wid[9] top.bench.masters_out[0].w.wid[8] top.bench.masters_out[0].w.wid[7] top.bench.masters_out[0].w.wid[6] top.bench.masters_out[0].w.wid[5] top.bench.masters_out[0].w.wid[4] top.bench.masters_out[0].w.wid[3] top.bench.masters_out[0].w.wid[2] top.bench.masters_out[0].w.wid[1] top.bench.masters_out[0].w.wid[0]
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@28
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top.bench.masters_out[0].w.wlast
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top.bench.masters_out[0].w.wvalid
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top.bench.masters_in[0].w.wready
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@200
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-
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-Write Address Channel
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@28
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#{top.bench.masters_out[0].aw.awprot[2:0]} top.bench.masters_out[0].aw.awprot[2] top.bench.masters_out[0].aw.awprot[1] top.bench.masters_out[0].aw.awprot[0]
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@22
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#{top.bench.masters_out[0].aw.awcache[3:0]} top.bench.masters_out[0].aw.awcache[3] top.bench.masters_out[0].aw.awcache[2] top.bench.masters_out[0].aw.awcache[1] top.bench.masters_out[0].aw.awcache[0]
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@28
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#{top.bench.masters_out[0].aw.awlock[1:0]} top.bench.masters_out[0].aw.awlock[1] top.bench.masters_out[0].aw.awlock[0]
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#{top.bench.masters_out[0].aw.awsize[2:0]} top.bench.masters_out[0].aw.awsize[2] top.bench.masters_out[0].aw.awsize[1] top.bench.masters_out[0].aw.awsize[0]
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#{top.bench.masters_out[0].aw.awburst[1:0]} top.bench.masters_out[0].aw.awburst[1] top.bench.masters_out[0].aw.awburst[0]
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@22
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#{top.bench.masters_out[0].aw.awlen[7:0]} top.bench.masters_out[0].aw.awlen[7] top.bench.masters_out[0].aw.awlen[6] top.bench.masters_out[0].aw.awlen[5] top.bench.masters_out[0].aw.awlen[4] top.bench.masters_out[0].aw.awlen[3] top.bench.masters_out[0].aw.awlen[2] top.bench.masters_out[0].aw.awlen[1] top.bench.masters_out[0].aw.awlen[0]
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#{top.bench.masters_out[0].aw.awaddr[31:0]} top.bench.masters_out[0].aw.awaddr[31] top.bench.masters_out[0].aw.awaddr[30] top.bench.masters_out[0].aw.awaddr[29] top.bench.masters_out[0].aw.awaddr[28] top.bench.masters_out[0].aw.awaddr[27] top.bench.masters_out[0].aw.awaddr[26] top.bench.masters_out[0].aw.awaddr[25] top.bench.masters_out[0].aw.awaddr[24] top.bench.masters_out[0].aw.awaddr[23] top.bench.masters_out[0].aw.awaddr[22] top.bench.masters_out[0].aw.awaddr[21] top.bench.masters_out[0].aw.awaddr[20] top.bench.masters_out[0].aw.awaddr[19] top.bench.masters_out[0].aw.awaddr[18] top.bench.masters_out[0].aw.awaddr[17] top.bench.masters_out[0].aw.awaddr[16] top.bench.masters_out[0].aw.awaddr[15] top.bench.masters_out[0].aw.awaddr[14] top.bench.masters_out[0].aw.awaddr[13] top.bench.masters_out[0].aw.awaddr[12] top.bench.masters_out[0].aw.awaddr[11] top.bench.masters_out[0].aw.awaddr[10] top.bench.masters_out[0].aw.awaddr[9] top.bench.masters_out[0].aw.awaddr[8] top.bench.masters_out[0].aw.awaddr[7] top.bench.masters_out[0].aw.awaddr[6] top.bench.masters_out[0].aw.awaddr[5] top.bench.masters_out[0].aw.awaddr[4] top.bench.masters_out[0].aw.awaddr[3] top.bench.masters_out[0].aw.awaddr[2] top.bench.masters_out[0].aw.awaddr[1] top.bench.masters_out[0].aw.awaddr[0]
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#{top.bench.masters_out[0].aw.awid[11:0]} top.bench.masters_out[0].aw.awid[11] top.bench.masters_out[0].aw.awid[10] top.bench.masters_out[0].aw.awid[9] top.bench.masters_out[0].aw.awid[8] top.bench.masters_out[0].aw.awid[7] top.bench.masters_out[0].aw.awid[6] top.bench.masters_out[0].aw.awid[5] top.bench.masters_out[0].aw.awid[4] top.bench.masters_out[0].aw.awid[3] top.bench.masters_out[0].aw.awid[2] top.bench.masters_out[0].aw.awid[1] top.bench.masters_out[0].aw.awid[0]
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@28
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top.bench.masters_out[0].aw.awvalid
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top.bench.masters_in[0].aw.awready
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@200
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-
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-Master Read Channel
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@22
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#{top.bench.masters_in[0].r.ruser[3:0]} top.bench.masters_in[0].r.ruser[3] top.bench.masters_in[0].r.ruser[2] top.bench.masters_in[0].r.ruser[1] top.bench.masters_in[0].r.ruser[0]
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@28
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#{top.bench.masters_in[0].r.rresp[1:0]} top.bench.masters_in[0].r.rresp[1] top.bench.masters_in[0].r.rresp[0]
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@22
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#{top.bench.masters_in[0].r.rdata[31:0]} top.bench.masters_in[0].r.rdata[31] top.bench.masters_in[0].r.rdata[30] top.bench.masters_in[0].r.rdata[29] top.bench.masters_in[0].r.rdata[28] top.bench.masters_in[0].r.rdata[27] top.bench.masters_in[0].r.rdata[26] top.bench.masters_in[0].r.rdata[25] top.bench.masters_in[0].r.rdata[24] top.bench.masters_in[0].r.rdata[23] top.bench.masters_in[0].r.rdata[22] top.bench.masters_in[0].r.rdata[21] top.bench.masters_in[0].r.rdata[20] top.bench.masters_in[0].r.rdata[19] top.bench.masters_in[0].r.rdata[18] top.bench.masters_in[0].r.rdata[17] top.bench.masters_in[0].r.rdata[16] top.bench.masters_in[0].r.rdata[15] top.bench.masters_in[0].r.rdata[14] top.bench.masters_in[0].r.rdata[13] top.bench.masters_in[0].r.rdata[12] top.bench.masters_in[0].r.rdata[11] top.bench.masters_in[0].r.rdata[10] top.bench.masters_in[0].r.rdata[9] top.bench.masters_in[0].r.rdata[8] top.bench.masters_in[0].r.rdata[7] top.bench.masters_in[0].r.rdata[6] top.bench.masters_in[0].r.rdata[5] top.bench.masters_in[0].r.rdata[4] top.bench.masters_in[0].r.rdata[3] top.bench.masters_in[0].r.rdata[2] top.bench.masters_in[0].r.rdata[1] top.bench.masters_in[0].r.rdata[0]
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#{top.bench.masters_in[0].r.rid[11:0]} top.bench.masters_in[0].r.rid[11] top.bench.masters_in[0].r.rid[10] top.bench.masters_in[0].r.rid[9] top.bench.masters_in[0].r.rid[8] top.bench.masters_in[0].r.rid[7] top.bench.masters_in[0].r.rid[6] top.bench.masters_in[0].r.rid[5] top.bench.masters_in[0].r.rid[4] top.bench.masters_in[0].r.rid[3] top.bench.masters_in[0].r.rid[2] top.bench.masters_in[0].r.rid[1] top.bench.masters_in[0].r.rid[0]
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@28
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top.bench.masters_in[0].r.rvalid
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top.bench.masters_in[0].r.rlast
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top.bench.masters_out[0].r.rready
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@200
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-
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-master B Channel
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@28
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#{top.bench.masters_in[0].b.bresp[1:0]} top.bench.masters_in[0].b.bresp[1] top.bench.masters_in[0].b.bresp[0]
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@22
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#{top.bench.masters_in[0].b.bid[11:0]} top.bench.masters_in[0].b.bid[11] top.bench.masters_in[0].b.bid[10] top.bench.masters_in[0].b.bid[9] top.bench.masters_in[0].b.bid[8] top.bench.masters_in[0].b.bid[7] top.bench.masters_in[0].b.bid[6] top.bench.masters_in[0].b.bid[5] top.bench.masters_in[0].b.bid[4] top.bench.masters_in[0].b.bid[3] top.bench.masters_in[0].b.bid[2] top.bench.masters_in[0].b.bid[1] top.bench.masters_in[0].b.bid[0]
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#{top.bench.masters_in[0].b.buser[3:0]} top.bench.masters_in[0].b.buser[3] top.bench.masters_in[0].b.buser[2] top.bench.masters_in[0].b.buser[1] top.bench.masters_in[0].b.buser[0]
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@28
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top.bench.masters_in[0].b.bvalid
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top.bench.masters_out[0].b.bready
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@200
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-
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-Master Read Address Channel
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@28
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#{top.bench.masters_out[0].ar.arprot[2:0]} top.bench.masters_out[0].ar.arprot[2] top.bench.masters_out[0].ar.arprot[1] top.bench.masters_out[0].ar.arprot[0]
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@22
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#{top.bench.masters_out[0].ar.arcache[3:0]} top.bench.masters_out[0].ar.arcache[3] top.bench.masters_out[0].ar.arcache[2] top.bench.masters_out[0].ar.arcache[1] top.bench.masters_out[0].ar.arcache[0]
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@28
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#{top.bench.masters_out[0].ar.arlock[1:0]} top.bench.masters_out[0].ar.arlock[1] top.bench.masters_out[0].ar.arlock[0]
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#{top.bench.masters_out[0].ar.arburst[1:0]} top.bench.masters_out[0].ar.arburst[1] top.bench.masters_out[0].ar.arburst[0]
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@c00023
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#{top.bench.masters_out[0].ar.arsize[2:0]} top.bench.masters_out[0].ar.arsize[2] top.bench.masters_out[0].ar.arsize[1] top.bench.masters_out[0].ar.arsize[0]
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@28
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top.bench.masters_out[0].ar.arsize[2]
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top.bench.masters_out[0].ar.arsize[1]
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top.bench.masters_out[0].ar.arsize[0]
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@1401203
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-group_end
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@c00022
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#{top.bench.masters_out[0].ar.arlen[7:0]} top.bench.masters_out[0].ar.arlen[7] top.bench.masters_out[0].ar.arlen[6] top.bench.masters_out[0].ar.arlen[5] top.bench.masters_out[0].ar.arlen[4] top.bench.masters_out[0].ar.arlen[3] top.bench.masters_out[0].ar.arlen[2] top.bench.masters_out[0].ar.arlen[1] top.bench.masters_out[0].ar.arlen[0]
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@28
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top.bench.masters_out[0].ar.arlen[7]
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top.bench.masters_out[0].ar.arlen[6]
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top.bench.masters_out[0].ar.arlen[5]
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top.bench.masters_out[0].ar.arlen[4]
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top.bench.masters_out[0].ar.arlen[3]
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top.bench.masters_out[0].ar.arlen[2]
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top.bench.masters_out[0].ar.arlen[1]
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top.bench.masters_out[0].ar.arlen[0]
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@1401202
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-group_end
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@22
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#{top.bench.masters_out[0].ar.araddr[31:0]} top.bench.masters_out[0].ar.araddr[31] top.bench.masters_out[0].ar.araddr[30] top.bench.masters_out[0].ar.araddr[29] top.bench.masters_out[0].ar.araddr[28] top.bench.masters_out[0].ar.araddr[27] top.bench.masters_out[0].ar.araddr[26] top.bench.masters_out[0].ar.araddr[25] top.bench.masters_out[0].ar.araddr[24] top.bench.masters_out[0].ar.araddr[23] top.bench.masters_out[0].ar.araddr[22] top.bench.masters_out[0].ar.araddr[21] top.bench.masters_out[0].ar.araddr[20] top.bench.masters_out[0].ar.araddr[19] top.bench.masters_out[0].ar.araddr[18] top.bench.masters_out[0].ar.araddr[17] top.bench.masters_out[0].ar.araddr[16] top.bench.masters_out[0].ar.araddr[15] top.bench.masters_out[0].ar.araddr[14] top.bench.masters_out[0].ar.araddr[13] top.bench.masters_out[0].ar.araddr[12] top.bench.masters_out[0].ar.araddr[11] top.bench.masters_out[0].ar.araddr[10] top.bench.masters_out[0].ar.araddr[9] top.bench.masters_out[0].ar.araddr[8] top.bench.masters_out[0].ar.araddr[7] top.bench.masters_out[0].ar.araddr[6] top.bench.masters_out[0].ar.araddr[5] top.bench.masters_out[0].ar.araddr[4] top.bench.masters_out[0].ar.araddr[3] top.bench.masters_out[0].ar.araddr[2] top.bench.masters_out[0].ar.araddr[1] top.bench.masters_out[0].ar.araddr[0]
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#{top.bench.masters_out[0].ar.arid[11:0]} top.bench.masters_out[0].ar.arid[11] top.bench.masters_out[0].ar.arid[10] top.bench.masters_out[0].ar.arid[9] top.bench.masters_out[0].ar.arid[8] top.bench.masters_out[0].ar.arid[7] top.bench.masters_out[0].ar.arid[6] top.bench.masters_out[0].ar.arid[5] top.bench.masters_out[0].ar.arid[4] top.bench.masters_out[0].ar.arid[3] top.bench.masters_out[0].ar.arid[2] top.bench.masters_out[0].ar.arid[1] top.bench.masters_out[0].ar.arid[0]
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@28
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top.bench.masters_out[0].ar.arvalid
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top.bench.masters_in[0].ar.arready
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[pattern_trace] 1
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[pattern_trace] 0
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