fpga/axi3-interconnect
1
1
Fork 0
Code Issues Pull Requests Releases Wiki Activity

address to slave is now masked

Browse Source
This commit is contained in:
Mario Hüttel 2016-08-23 17:57:57 +02:00
parent 4ee6195c4d
commit 3d7b14c6ff
2 changed files with 16 additions and 8 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/master2slave/axi3-interconnect-ar-router.vhd
View File

@ -59,10 +59,14 @@ begin
if masters_out(i).arvalid = '1' then
slave_idx(i) := calculate_slave(masters_out(i).araddr, address_array, mask_array);
if slave_in_use(slave_idx(i)) /= '1' then
slave_in_use(slave_idx(i)) := '1';
masters_in(i).arready <= '1';
slave_in_use(slave_idx(i)) := '1';
masters_in(i).arready <= '1';
-- Write request to slave
slaves_in(slave_idx(i)).araddr <= masters_out(i).araddr;
if slave_idx(i) = SLAVE_COUNT then
slaves_in(slave_idx(i)).araddr <= masters_out(i).araddr;
else
slaves_in(slave_idx(i)).araddr <= masters_out(i).araddr and (not mask_array(slave_idx(i)));
end if;
slaves_in(slave_idx(i)).arid <= std_logic_vector(to_unsigned(i, RID_SLAVE_BITS - RID_MASTER_BITS)) & masters_out(i).arid;
slaves_in(slave_idx(i)).arburst <= masters_out(i).arburst;
slaves_in(slave_idx(i)).arcache <= masters_out(i).arcache;

14
src/master2slave/axi3-interconnect-aw-router.vhd
View File

@ -63,12 +63,16 @@ begin
if masters_out(i).awvalid = '1' then -- check awready. just to prevent glitches
slave_idx := calculate_slave(masters_out(i).awaddr, address_array, mask_array);
if slave_in_use(slave_idx) /= '1' then
awready_s(i) <= '1';
write_locks_s(i).slave_idx <= slave_idx;
write_locks_s(i).locked <= '1';
slave_in_use(slave_idx) := '1';
awready_s(i) <= '1';
write_locks_s(i).slave_idx <= slave_idx;
write_locks_s(i).locked <= '1';
slave_in_use(slave_idx) := '1';
-- output request to slave
slaves_in(slave_idx).awaddr <= masters_out(i).awaddr;
if slave_idx = SLAVE_COUNT then
slaves_in(slave_idx).awaddr <= masters_out(i).awaddr;
else
slaves_in(slave_idx).awaddr <= masters_out(i).awaddr and (not mask_array(slave_idx));
end if;
slaves_in(slave_idx).awid <= std_logic_vector(to_unsigned(i, WID_SLAVE_BITS - WID_MASTER_BITS)) & masters_out(i).awid;
slaves_in(slave_idx).awburst <= masters_out(i).awburst;
slaves_in(slave_idx).awcache <= masters_out(i).awcache;