fpga/axi3-interconnect
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fixed entity name of aw router

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This commit is contained in:
Mario Hüttel 2016-08-21 15:41:09 +02:00
parent 73c1db7798
commit 438c23290e
3 changed files with 20 additions and 24 deletions
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6
src/axi3-interconnect-aw-router.vhd
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@ -5,7 +5,7 @@ use ieee.numeric_std.all;
use work.axi3intercon_pkg.all; use work.axi3intercon_pkg.all;
use work.axi_aw_router_pkg.all; use work.axi_aw_router_pkg.all;
entity axi3intecon_aw_router is entity axi3intercon_aw_router is
port( port(
aclk : in std_logic; aclk : in std_logic;
rst : in std_logic; rst : in std_logic;
@ -16,8 +16,8 @@ entity axi3intecon_aw_router is
write_locks : out write_locks_t(0 to MASTER_COUNT - 1); write_locks : out write_locks_t(0 to MASTER_COUNT - 1);
write_releases : in write_release_t write_releases : in write_release_t
); );
end entity axi3intecon_aw_router; end entity axi3intercon_aw_router;
architecture RTL of axi3intecon_aw_router is architecture RTL of axi3intercon_aw_router is
begin begin
end architecture RTL; end architecture RTL;

6
src/axi3-interconnect.vhd
View File

@ -34,8 +34,7 @@ begin
end if; end if;
end process reset_sync; end process reset_sync;
axi3intercon_aw_router_inst : entity work.axi3intercon_aw_router
axi3intecon_aw_router_inst : entity work.axi3intecon_aw_router
port map( port map(
aclk => aclk, aclk => aclk,
rst => rst, rst => rst,
@ -57,7 +56,4 @@ begin
slaves_in(i).aw <= aw_slaves_in(i); slaves_in(i).aw <= aw_slaves_in(i);
end generate aw_slave_connect; end generate aw_slave_connect;
end architecture RTL; end architecture RTL;