fpga/axi3-interconnect
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modified types to *_t, aw router created and connected

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This commit is contained in:
Mario Hüttel 2016-08-21 15:37:35 +02:00
parent 6aaf75421a
commit 73c1db7798
4 changed files with 150 additions and 73 deletions
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23
src/axi3-interconnect-aw-router.vhd Normal file
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@ -0,0 +1,23 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi3intercon_pkg.all;
use work.axi_aw_router_pkg.all;
entity axi3intecon_aw_router is
port(
aclk : in std_logic;
rst : in std_logic;
masters_out : in axi_aw_masters_out_t(0 to MASTER_COUNT - 1);
masters_in : out axi_aw_masters_in_t(0 to MASTER_COUNT - 1);
slaves_out : in axi_aw_slaves_out_t(0 to SLAVE_COUNT - 1);
slaves_in : out axi_aw_slaves_in_t(0 to SLAVE_COUNT - 1);
write_locks : out write_locks_t(0 to MASTER_COUNT - 1);
write_releases : in write_release_t
);
end entity axi3intecon_aw_router;
architecture RTL of axi3intecon_aw_router is
begin
end architecture RTL;

23
src/axi3-interconnect-aw-router_pkg.vhd Normal file
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@ -0,0 +1,23 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi3intercon_pkg.all;
package axi_aw_router_pkg is
type axi_aw_masters_in_t is array (natural range <>) of master_aw_in_t;
type axi_aw_masters_out_t is array (natural range <>) of master_aw_out_t;
type axi_aw_slaves_out_t is array (natural range <>) of slave_aw_out_t;
type axi_aw_slaves_in_t is array (natural range <>) of slave_aw_in_t;
type write_lock_t is record
locked : std_logic;
slave_idx : integer range 0 to SLAVE_COUNT - 1;
end record write_lock_t;
type write_locks_t is array (natural range <>) of write_lock_t;
subtype write_release_t is std_logic_vector(0 to MASTER_COUNT -1);
end package axi_aw_router_pkg;
-- package body filename is
-- end package body filename;

46
src/axi3-interconnect.vhd
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@ -1,27 +1,29 @@
library ieee; library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_1164.all;
use ieee.numeric_std.all; use ieee.numeric_std.all;
-- "work" denotes the curent library. Similar to this in C++, C# etc... -- "work" denotes the curent library. Similar to this in C++, C# etc...
use work.axi3intercon_pkg.all; use work.axi3intercon_pkg.all;
use work.axi_aw_router_pkg.all;
entity axi3intercon is entity axi3intercon is
generic(
constant MASTER_COUNT : natural := 1;
constant SLAVE_COUNT : natural := 1
);
port( port(
aclk : in std_logic; aclk : in std_logic;
aresetn : in std_logic; aresetn : in std_logic;
masters_in : out axi_masters_in(0 to MASTER_COUNT - 1); masters_in : out axi_masters_in_t(0 to MASTER_COUNT - 1);
masters_out : in axi_masters_out(0 to MASTER_COUNT - 1); masters_out : in axi_masters_out_t(0 to MASTER_COUNT - 1);
slaves_in : out axi_masters_in(0 to SLAVE_COUNT - 1); slaves_in : out axi_slaves_in_t(0 to SLAVE_COUNT - 1);
slaves_out : in axi_masters_out(0 to SLAVE_COUNT - 1) slaves_out : in axi_slaves_out_t(0 to SLAVE_COUNT - 1)
); );
end entity axi3intercon; end entity axi3intercon;
architecture RTL of axi3intercon is architecture RTL of axi3intercon is
signal rst : std_logic; signal rst : std_logic;
signal write_locks : write_locks_t(0 to MASTER_COUNT - 1);
signal write_releases : write_release_t;
signal aw_masters_out : axi_aw_masters_out_t(0 to MASTER_COUNT - 1);
signal aw_masters_in : axi_aw_masters_in_t(0 to MASTER_COUNT - 1);
signal aw_slaves_out : axi_aw_slaves_out_t(0 to SLAVE_COUNT - 1);
signal aw_slaves_in : axi_aw_slaves_in_t(0 to SLAVE_COUNT - 1);
begin begin
reset_sync : process(aclk, aresetn) is reset_sync : process(aclk, aresetn) is
begin begin
@ -31,5 +33,31 @@ begin
rst <= '0'; rst <= '0';
end if; end if;
end process reset_sync; end process reset_sync;
axi3intecon_aw_router_inst : entity work.axi3intecon_aw_router
port map(
aclk => aclk,
rst => rst,
masters_out => aw_masters_out,
masters_in => aw_masters_in,
slaves_out => aw_slaves_out,
slaves_in => aw_slaves_in,
write_locks => write_locks,
write_releases => write_releases
);
aw_master_connect : for i in 0 to MASTER_COUNT-1 generate
aw_masters_out(i) <= masters_out(i).aw;
masters_in(i).aw <= aw_masters_in(i);
end generate aw_master_connect;
aw_slave_connect : for i in 0 to SLAVE_COUNT-1 generate
aw_slaves_out(i) <= slaves_out(i).aw;
slaves_in(i).aw <= aw_slaves_in(i);
end generate aw_slave_connect;
end architecture RTL; end architecture RTL;

131
src/axi3-interconnect_pkg.vhd
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@ -17,6 +17,9 @@ package axi3intercon_pkg is
constant USER_BITS : natural := 4; constant USER_BITS : natural := 4;
constant MASTER_COUNT : natural := 2;
constant SLAVE_COUNT : natural := 2;
-- Constant definitions for signals -- Constant definitions for signals
--Definitions for burst size --Definitions for burst size
@ -41,7 +44,7 @@ package axi3intercon_pkg is
constant AXI_RESP_LOCKED : std_logic_vector(1 downto 0) := "10"; constant AXI_RESP_LOCKED : std_logic_vector(1 downto 0) := "10";
-- type declarations for AW channel -- type declarations for AW channel
type master_aw_out is record type master_aw_out_t is record
awid : std_logic_vector(WID_MASTER_BITS - 1 downto 0); -- Write transaction ID awid : std_logic_vector(WID_MASTER_BITS - 1 downto 0); -- Write transaction ID
awaddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Write address awaddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Write address
awlen : std_logic_vector(7 downto 0); -- Burst length - 1; awlen : std_logic_vector(7 downto 0); -- Burst length - 1;
@ -51,13 +54,13 @@ package axi3intercon_pkg is
awcache : std_logic_vector(3 downto 0); -- caching info awcache : std_logic_vector(3 downto 0); -- caching info
awprot : std_logic_vector(2 downto 0); -- protection info awprot : std_logic_vector(2 downto 0); -- protection info
awvalid : std_logic; -- Data valid awvalid : std_logic; -- Data valid
end record master_aw_out; end record master_aw_out_t;
type master_aw_in is record type master_aw_in_t is record
awready : std_logic; awready : std_logic;
end record master_aw_in; end record master_aw_in_t;
type slave_aw_in is record type slave_aw_in_t is record
awid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0); -- Write transaction ID awid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0); -- Write transaction ID
awaddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Write address awaddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Write address
awlen : std_logic_vector(7 downto 0); -- Burst length - 1; awlen : std_logic_vector(7 downto 0); -- Burst length - 1;
@ -67,12 +70,12 @@ package axi3intercon_pkg is
awcache : std_logic_vector(3 downto 0); -- caching info awcache : std_logic_vector(3 downto 0); -- caching info
awprot : std_logic_vector(2 downto 0); -- protection info awprot : std_logic_vector(2 downto 0); -- protection info
awvalid : std_logic; -- Data valid awvalid : std_logic; -- Data valid
end record slave_aw_in; end record slave_aw_in_t;
subtype slave_aw_out is master_aw_in; subtype slave_aw_out_t is master_aw_in_t;
-- type decalatations for AR cahnnel -- type decalatations for AR cahnnel
type master_ar_out is record type master_ar_out_t is record
arid : std_logic_vector(WID_MASTER_BITS - 1 downto 0); -- Write transaction ID arid : std_logic_vector(WID_MASTER_BITS - 1 downto 0); -- Write transaction ID
araddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Write start address araddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Write start address
arlen : std_logic_vector(7 downto 0); -- Burst length - 1; arlen : std_logic_vector(7 downto 0); -- Burst length - 1;
@ -82,13 +85,13 @@ package axi3intercon_pkg is
arcache : std_logic_vector(3 downto 0); -- caching info arcache : std_logic_vector(3 downto 0); -- caching info
arprot : std_logic_vector(2 downto 0); -- protection info arprot : std_logic_vector(2 downto 0); -- protection info
arvalid : std_logic; -- Data valid arvalid : std_logic; -- Data valid
end record master_ar_out; end record master_ar_out_t;
type master_ar_in is record type master_ar_in_t is record
awready : std_logic; awready : std_logic;
end record master_ar_in; end record master_ar_in_t;
type slave_ar_in is record type slave_ar_in_t is record
arid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0); -- Read transaction ID arid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0); -- Read transaction ID
araddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Read start address araddr : std_logic_vector(DATA_BITS - 1 downto 0); -- Read start address
arlen : std_logic_vector(7 downto 0); -- Burst length - 1; arlen : std_logic_vector(7 downto 0); -- Burst length - 1;
@ -98,121 +101,121 @@ package axi3intercon_pkg is
arcache : std_logic_vector(3 downto 0); -- caching info arcache : std_logic_vector(3 downto 0); -- caching info
arprot : std_logic_vector(2 downto 0); -- protection info arprot : std_logic_vector(2 downto 0); -- protection info
arvalid : std_logic; -- Data valid arvalid : std_logic; -- Data valid
end record slave_ar_in; end record slave_ar_in_t;
subtype slave_ar_out is master_ar_in; subtype slave_ar_out is master_ar_in_t;
-- type decalarations for W channel -- type decalarations for W channel
type master_w_out is record type master_w_out_t is record
wid : std_logic_vector(WID_MASTER_BITS - 1 downto 0); wid : std_logic_vector(WID_MASTER_BITS - 1 downto 0);
wdata : std_logic_vector(DATA_BITS - 1 downto 0); wdata : std_logic_vector(DATA_BITS - 1 downto 0);
wstrb : std_logic_vector(DATA_STROBES - 1 downto 0); wstrb : std_logic_vector(DATA_STROBES - 1 downto 0);
wlast : std_logic; wlast : std_logic;
wuser : std_logic_vector(USER_BITS - 1 downto 0); -- user defined wuser : std_logic_vector(USER_BITS - 1 downto 0); -- user defined
wvalid : std_logic; wvalid : std_logic;
end record master_w_out; end record master_w_out_t;
type slave_w_in is record type slave_w_in_t is record
wid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0); wid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0);
wdata : std_logic_vector(DATA_BITS - 1 downto 0); wdata : std_logic_vector(DATA_BITS - 1 downto 0);
wstrb : std_logic_vector(DATA_STROBES - 1 downto 0); wstrb : std_logic_vector(DATA_STROBES - 1 downto 0);
wlast : std_logic; wlast : std_logic;
wuser : std_logic_vector(USER_BITS - 1 downto 0); -- user defined wuser : std_logic_vector(USER_BITS - 1 downto 0); -- user defined
wvalid : std_logic; wvalid : std_logic;
end record slave_w_in; end record slave_w_in_t;
type master_w_in is record type master_w_in_t is record
wready : std_logic; wready : std_logic;
end record master_w_in; end record master_w_in_t;
subtype slave_w_out is master_w_in; subtype slave_w_out is master_w_in_t;
-- Type declarations for R channel -- Type declarations for R channel
type master_r_in is record type master_r_in_t is record
rid : std_logic_vector(RID_MASTER_BITS - 1 downto 0); rid : std_logic_vector(RID_MASTER_BITS - 1 downto 0);
rdata : std_logic_vector(DATA_BITS - 1 downto 0); rdata : std_logic_vector(DATA_BITS - 1 downto 0);
rresp : std_logic_vector(1 downto 0); rresp : std_logic_vector(1 downto 0);
rlast : std_logic; rlast : std_logic;
ruser : std_logic_vector(USER_BITS - 1 downto 0); ruser : std_logic_vector(USER_BITS - 1 downto 0);
rvalid : std_logic; rvalid : std_logic;
end record master_r_in; end record master_r_in_t;
type slave_r_out is record type slave_r_out_t is record
rid : std_logic_vector(RID_SLAVE_BITS - 1 downto 0); rid : std_logic_vector(RID_SLAVE_BITS - 1 downto 0);
rdata : std_logic_vector(DATA_BITS - 1 downto 0); rdata : std_logic_vector(DATA_BITS - 1 downto 0);
rresp : std_logic_vector(1 downto 0); rresp : std_logic_vector(1 downto 0);
rlast : std_logic; rlast : std_logic;
ruser : std_logic_vector(USER_BITS - 1 downto 0); ruser : std_logic_vector(USER_BITS - 1 downto 0);
rvalid : std_logic; rvalid : std_logic;
end record slave_r_out; end record slave_r_out_t;
type master_r_out is record type master_r_out_t is record
rready : std_logic; rready : std_logic;
end record master_r_out; end record master_r_out_t;
subtype slave_r_in is master_r_out; subtype slave_r_in is master_r_out_t;
-- Type declarations for B channel -- Type declarations for B channel
type master_b_in is record type master_b_in_t is record
bid : std_logic_vector(WID_MASTER_BITS - 1 downto 0); bid : std_logic_vector(WID_MASTER_BITS - 1 downto 0);
bresp : std_logic_vector(1 downto 0); bresp : std_logic_vector(1 downto 0);
buser : std_logic_vector(USER_BITS - 1 downto 0); buser : std_logic_vector(USER_BITS - 1 downto 0);
bvalid : std_logic; bvalid : std_logic;
end record master_b_in; end record master_b_in_t;
type slave_b_out is record type slave_b_out_t is record
bid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0); bid : std_logic_vector(WID_SLAVE_BITS - 1 downto 0);
bresp : std_logic_vector(1 downto 0); bresp : std_logic_vector(1 downto 0);
buser : std_logic_vector(USER_BITS - 1 downto 0); buser : std_logic_vector(USER_BITS - 1 downto 0);
bvalid : std_logic; bvalid : std_logic;
end record slave_b_out; end record slave_b_out_t;
type master_b_out is record type master_b_out_t is record
bready : std_logic; bready : std_logic;
end record master_b_out; end record master_b_out_t;
subtype slave_b_in is master_b_out; subtype slave_b_in_t is master_b_out_t;
-- Combined definitions -- Combined definitions
type axi_master_in is record type axi_master_in_t is record
aw : master_aw_in; aw : master_aw_in_t;
ar : master_ar_in; ar : master_ar_in_t;
w : master_w_in; w : master_w_in_t;
r : master_r_in; r : master_r_in_t;
b : master_b_in; b : master_b_in_t;
end record axi_master_in; end record axi_master_in_t;
type axi_master_out is record type axi_master_out_t is record
aw : master_aw_out; aw : master_aw_out_t;
ar : master_ar_out; ar : master_ar_out_t;
w : master_w_out; w : master_w_out_t;
r : master_r_out; r : master_r_out_t;
b : master_b_out; b : master_b_out_t;
end record axi_master_out; end record axi_master_out_t;
type axi_slave_in is record type axi_slave_in_t is record
aw : slave_aw_in; aw : slave_aw_in_t;
ar : slave_ar_in; ar : slave_ar_in_t;
w : slave_w_in; w : slave_w_in_t;
r : slave_r_in; r : slave_r_in;
b : slave_b_in; b : slave_b_in_t;
end record axi_slave_in; end record axi_slave_in_t;
type axi_slave_out is record type axi_slave_out_t is record
aw : slave_aw_out; aw : slave_aw_out_t;
ar : slave_ar_out; ar : slave_ar_out;
w : slave_w_out; w : slave_w_out;
r : slave_r_out; r : slave_r_out_t;
b : slave_b_out; b : slave_b_out_t;
end record axi_slave_out; end record axi_slave_out_t;
-- Array definitions -- Array definitions
type axi_masters_in is array (natural range <>) of axi_master_in; type axi_masters_in_t is array (natural range <>) of axi_master_in_t;
type axi_masters_out is array (natural range <>) of axi_master_out; type axi_masters_out_t is array (natural range <>) of axi_master_out_t;
type axi_slaves_in is array (natural range <>) of axi_slave_in; type axi_slaves_in_t is array (natural range <>) of axi_slave_in_t;
type axi_slaves_out is array (natural range <>) of axi_slave_out; type axi_slaves_out_t is array (natural range <>) of axi_slave_out_t;
end package axi3intercon_pkg; end package axi3intercon_pkg;